US007345713B2
`
`(12) United States Patent
`Arai et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,345,713 B2
`Mar. 18, 2008
`
`(54) VIDEO DISPLAY APPARATUS FOR
`CORRECTING LUMINANCE DIFFERENCE
`
`7/1993 Bilbrey et a1. ............ .. 348/578
`5,227,863 A *
`5,359,342 A * 10/1994 Nakai et a1. ................ .. 345/89
`
`BETWEEN DISPLAY PIXELS
`
`6,020,868 A *
`
`2/2000 Greene et a1. .............. .. 345/88
`
`(75) Inventors, Takayuki Arai’ Fukaya (JP); Tsutomu
`
`6,396,508 Bl *
`
`5/2002 Noecker ................... .. 345/693
`
`
`
`Masao sakamotos Fukaya Yanamoto, Fukaya (JP); Toshio
`
`
`
`Obayashi, Fukaya (JP)
`
`(73) Assignee: Kabushiki Kaisha Toshiba, Tokyo (JP)
`
`( * ) Not1ce:
`
`_
`
`_
`
`_
`
`_
`
`Subject to any d1scla1mer, the term of this
`patent is extended or adjusted under 35
`U50 1540)) by 558 days-
`
`_
`
`(21) Appl. No.: 11/028,503
`
`22 E1 d:
`(
`)
`16
`
`J . 4 2005
`an ’
`
`(65)
`
`Prior Publication Data
`US 2005/0151883 A1
`Jul. 14, 2005
`
`Foreign Application Priority Data
`(30)
`Jan. 9, 2004
`(JP)
`........................... .. 2004-004782
`
`(51) Int. Cl.
`(200601)
`H04N 5/5 7
`(200601)
`H04N 5/14
`(2006.01)
`G09G 5/02
`(52) US. Cl. .................... .. 348/687; 348/672; 348/679;
`348/790; 345/ 600; 345/ 63
`(58) Field of Classi?cation Search ______ __ 348/6724675,
`348/678, 679, 687, 790, 791, 7 954803; 345/589,
`345/593, 6004605, 63, 77, 78
`See application ?le for complete search history.
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`
`
`* 2003/0095085 A1* 5/2003 Abe ........................ .. 345/74.1 Yoshida et . . . . . . . . . . . ..
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`
`2001-075542
`2004-157309
`
`3/2001
`6/2004
`
`* cited by examiner
`
`Primary ExamineriVictor R. Kostak
`(74) Attorney, Agent, or FirmiPillsbury Winthrop ShaW
`Pittman, LLP
`
`(57)
`
`ABSTRACT
`
`An analog-to-digital converter converts a video signal into a
`digital video signal consisting of N bits and outputs the
`converted signal. A correction value memory stores correc
`tion data Consisting of M bits Which is used to Correct the
`difference in luminance between display pixels on a display.
`A multiplier multiplies the video signal consisting of N bits
`output from the analog-to-digital converter by the correction
`data consisting of M bits stored in the correction value
`memory, and outputs a video signal consisting of L bits With
`Wh1ch the dliference 1n luminance between display pixels on
`the display is corrected.
`
`4,897,639 A *
`
`1/1990 Kanayama ................. .. 345/82
`
`5 Claims, 5 Drawing Sheets
`
`11
`2
`Analog _FlGB
`video signal
`_
`,
`———> Analog-to-digrtal
`converter
`
`A
`
`9
`
`(it hits)
`
`i2
`
`D
`
`><
`
`9
`
`(L bits
`
`710
`
`Data interpolation
`21"“ (correction bit control)
`Bil
`Bzi
`Correction
`Correction
`Clock _* Address
`Hsync—> generation —+ value
`value
`vsync
`circuit
`memory 1
`memory 2
`
`13
`a
`A I
`I,
`i
`Signal iliiB dtlVBl'
`
`—
`I
`d_
`Scanning I P]
`line driver__
`anar 'sp ay
`_
`
`i5
`
`22
`
`147:
`
`23
`
`1e
`
`17
`
`Non-volatile memory ~18
`
`1
`
`Inter Partes Review of RE 43,707
`IPR 2014-00778
`Exhibit 1024
`
`

`
`U.S. Patent
`
`Mar. 18,2008
`
`Sheet 1 of 5
`
`US 7,345,713 B2
`
`13
`12
`11
`
` Video signal
`
`i
`Analog-to-digital
`
`
`converter
`
`Address
` ADR
`generation
`circuit
`
`
`
`
`
`Pixel
`
`number
`
`1
`
`La
`
`0.8
`
`1
`
`1.2
`
`—-_—*
`Luminance X
`
`FlG.2
`
`2
`
`

`
`U.S. Patent
`
`Mar. 18, 2008
`
`Sheet 2 0f 5
`
`US 7,345,713 B2
`
`12
`
`n 0 - -
`
`.
`
`11
`Analog R65
`D
`
`————>Video Signal A a1 gin digital A
`converter
`(N bits).
`0
`(M bits}
`Data interpolation
`.
`
`15
`2
`
`20
`
`-
`
`-
`
`13
`2
`Sugnal lme dnver
`T |
`|
`|
`|
`
`I
`
`-
`
`‘
`_
`
`35
`
`1‘;
`
`-
`(P b?s) m5
`‘Suing-n9 — Planardisplay
`.
`Correctlon value memory me "191 __
`‘
`_
`A
`a
`_
`(P buts)‘,
`14b
`18M Non-valatile memory
`
`Cluck _)_ Address.
`Hsyn0+ gpnqrahon
`Vsync
`GH'CUH
`
`F I (5.3
`
`Y Y Y Y —> 1
`3
`2
`1
`0
`b9
`FIG.4A
`
`1
`1
`Y Y Y Y 1
`1
`b8 b7 b6 b5
`b4 b3 b2 b1
`F|G.4B
`
`1
`b0
`
`3
`
`

`
`U.S. Patent
`
`Mar. 18, 2008
`
`Sheet 3 0f 5
`
`US 7,345,713 B2
`
`Analog RGB
`video signal
`
`FIG.5
`
`Y Y Y Y ——>
`
`1
`
`1YYYY
`1
`
`F1G.6A
`
`YYYY-->
`
`1
`
`1
`1YYYY
`
`4
`
`

`
`U.S. Patent
`
`Mar. 18, 2008
`
`Sheet 4 0f 5
`
`US 7,345,713 B2
`
`17a (Correction with 4 bits)
`/
`I
`
`’\-*17
`
`\
`17b (Correction with 6 bits)
`
`F I G. 7
`
`11
`Analog HGB
`310 d’ ital
`video signal An I
`convegter 9
`
`—————> ao -
`
`- r
`
`I;
`(N bus)
`
`,
`
`.12
`6% I?
`(L bgs)
`
`,
`
`I
`
`>
`
`13
`'2
`Signal line dnver
`
`.
`
`.
`
`> .
`
`Data interpolation
`21“ (correction bit control)
`
`l
`
`B1
`Correction
`Clock _" Address
`Hsync—> generation > value
`vsync
`circuit
`memory 1
`
`A
`B2
`Correction
`value
`memory 2
`
`-
`
`_.__
`_
`Scanning __ Pl
`line driver __
`anar d'splay
`
`—
`
`i5
`
`22
`
`140 V
`
`23
`
`re
`
`17
`
`Non-volatile memory ~18
`
`5
`
`

`
`U.S. Patent
`
`Mar. 18, 2008
`
`Sheet 5 0f 5
`
`US 7,345,713 B2
`
`F | G. 9
`
`F | G. 1 0
`
`Pixel
`number
`
`V
`Pixel T
`number
`
`5
`5
`
`number
`
`——>
`Luminance x
`
`——>
`Luminance x
`
`F|G.11 n
`
`0.6
`
`0.8
`
`j
`1.0
`
`1.2
`
`1.4
`
`Luminancex
`
`6
`
`

`
`US 7,345,713 B2
`
`1
`VIDEO DISPLAY APPARATUS FOR
`CORRECTING LUMINANCE DIFFERENCE
`BETWEEN DISPLAY PIXELS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is based upon and claims the bene?t of
`priority from prior Japanese Patent Application No. 2004
`004782, ?led Jan. 9, 2004, the entire contents of Which are
`incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a video display apparatus,
`and more particularly to a video display apparatus Which
`corrects irregularities in luminance for each pixel generated
`in a planar display or the like.
`2. Description of the Related Art
`In a video display apparatus having a plurality of light
`emitting elements, there is a problem that irregularities in
`luminance, color or the like are generated due to irregulari
`ties in luminance characteristics betWeen the respective light
`emitting elements. In order to solve this problem, such a
`technique as described in Jpn. Pat. Appln. KOKAI Publica
`tion No. 2001-75542 is disclosed.
`In the above-described reference, a video displayed in a
`display apparatus is imaged by a camera, the video signal is
`subjected to analog-to-digital conversion, the converted
`signal is further processed into correction information, the
`correction information is Written in a non-volatile memory,
`and the video signal to be displayed in the display apparatus
`is corrected by using the Written correction information.
`When irregularities in luminance characteristics betWeen
`the respective light emitting elements are corrected by using
`such a technique as disclosed in Jpn. Pat. Appln. KOKAI
`Publication No. 2001-75542, irregularities in luminance of
`the display is suppressed, Whereas there occurs a problem
`such as a reduction in luminance or a reduction in contrast.
`When the degree of irregularities in luminance of the display
`is large in particular, the problem of a reduction in lumi
`nance or a reduction in contrast is serious.
`
`BRIEF SUMMARY OF THE INVENTION
`
`2
`Irregularities in luminance of the display are corrected
`While suppressing a reduction in performances, such as a
`reduction in luminance or a reduction in contrast, of the
`display as much as possible.
`Additional advantages of the invention Will be set forth in
`the description Which folloWs, and in part Will be obvious
`from the description, or may be learned by practice of the
`invention. The advantages of the invention may be realiZed
`and obtained by means of the instrumentalities and combi
`nations particularly pointed out hereinafter.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`The accompanying draWings, Which are incorporated in
`and constitute a part of the speci?cation, illustrate embodi
`ments of the invention, and together With the general
`description given above and the detailed description of the
`embodiments given beloW, serve to explain the principles of
`the invention.
`FIG. 1 is a block diagram illustrating a video display
`apparatus according to a ?rst embodiment of the present
`invention;
`FIG. 2 is a vieW schematically shoWing irregularities in
`luminance of each general pixel in a planar display 17;
`FIG. 3 is a block diagram shoWing a structure obtained by
`further concretiZing the ?rst embodiment according to the
`present invention;
`FIG. 4A and 4B are vieWs illustrating interpolation pro
`cessing of correction data;
`FIG. 5 is a block diagram shoWing a structure of a second
`embodiment according to the present invention;
`FIG. 6A and 6B are vieWs illustrating selective interpo
`lation processing of correction data according to second
`embodiment;
`FIG. 7 is a vieW illustrating a scheme of a third embodi
`ment according to the present invention;
`FIG. 8 is a block diagram illustrating the third embodi
`ment according to the present invention;
`FIG. 9 is a vieW shoWing a distribution before correcting
`pixel irregularities in a planar display;
`FIG. 10 is a vieW shoWing a distribution after correcting
`pixel irregularities in the planar display; and
`FIG. 11 is a vieW shoWing a distribution after correcting
`pixel irregularities in the planar display.
`
`20
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`According to an embodiment of the present invention,
`there is provided A video display apparatus Which displays
`a video image based on a video signal in a video display
`portion comprising a plurality of pixels, comprising:
`a video signal conversion portion Which converts the
`video signal into a digital video signal consisting of N
`bits (N is an integer) and outputs the converted signal;
`a correction data storage portion Which stores correction
`data consisting of M bits (M is an integer) With respect
`to a pixel having a light emission luminance exceeding
`a predetermined threshold value in the video display
`portion; and
`a video signal output portion Which outputs a video signal
`consisting of L bits (L is an integer) With Which a
`difference in characteristics betWeen display pixels in
`the video display portion is corrected, based on the
`video signal consisting of N bits output from the video
`signal conversion portion and the correction data con
`sisting of M bits stored in the correction data storage
`portion.
`
`60
`
`65
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`Embodiments according to the present invention Will noW
`be described hereinafter With reference to the accompanying
`draWings.
`
`EMBODIMENT 1
`
`FIG. 1 is a block diagram illustrating a video display
`apparatus according to the ?rst embodiment of the present
`invention.
`Reference numeral 11 denotes an analog-to-digital con
`verter; reference numeral 12, a multiplier; reference numeral
`13, a signal line drive circuit; reference numeral 14a, a
`correction value memory; reference numeral 15, an address
`generation circuit; reference numeral 16, a scanning line
`drive circuit; and reference numeral 17, a planar display. It
`is to be noted that a ?eld emission display (FED), an
`electroluminescent display, a liquid crystal, a plasma display
`or the like is used as the planar display 17. A video image
`
`7
`
`

`
`US 7,345,713 B2
`
`25
`
`30
`
`35
`
`20
`
`3
`is displayed in this planar display 17 based on a video signal
`subjected to processing described beloW. Further, the ana
`log-to-digital converter 11 is a converter Which converts an
`analog signal into a digital signal, and comprises a semi
`conductor IC or the like.
`When a broadcast signal is received through a non
`illustrated broadcast receiving device (a tuner), a video
`signal is demodulated. This demodulated video signal is
`converted into a video signal having an analog RGB format
`(an analog RGB video signal) by predetermined processing
`and input to the analog-to-digital converter 11. The analog
`to-digital converter 11 converts the input analog RGB video
`signal into digital video data A composed of N bits and
`outputs this data to the multiplier 12. That is, the analog
`to-digital converter 11 is an video signal conversion pro
`cessing portion Which converts the analog RGB video signal
`into the digital video data A composed of N bits.
`It is to be noted that the apparatus can be con?gured in
`such a manner that a digital video signal having an arbitrary
`bit number is input to the video signal conversion processing
`portion. In such a case, the input digital signal is converted
`into digital video data A composed of N bits and output.
`Irregularities in luminance of respective display pixels in
`the planar display 17 are previously measured by using an
`imaging device or the like. The correction value memory
`14a stores data (correction data) Which is used to correct the
`irregularities in luminance of the display pixels in the planar
`display 17. Correction data B output from the correction
`value memory 14a is digital data composed of M bits. As to
`the correction data, a display screen of, e.g., raster White
`(When all the display pixels are driven With each data of R,
`G and B being determined as a maximum value) is imaged
`by using a CCD camera or the like, a luminance distribution
`is measured, and the correction data is determined in accor
`dance With each display luminance distribution.
`A clock signal (clock), a horizontal synchronization signal
`(Hsync) and a vertical synchronization signal (V sync) are
`input to the address generation circuit 15 from a non
`illustrated timing generation circuit. The address generation
`circuit 15 outputs an address signal ADR based on the signal
`clock, the signal Hsync and the signal Vsync. This address
`signal ADR is an address Which is used to read a correction
`value stored in the correction value memory 14a, and
`corresponds to an address of a display pixel on the planar
`display 17. The video data A is corrected based on the
`correction data B read from the correction value memory
`1411. That is, the video data of a corresponding pixel on the
`planar display 17 is corrected by using the correction data B.
`50
`The multiplier 12 multiplies the digital video data A
`consisting of N bits output from the analog-to-digital con
`verter 11 by the correction data B consisting of M bits output
`from the correction value memory 14a, and outputs the most
`signi?cant L-bit data Which is a result of the multiplication
`as video data C. That is, the multiplier 12 outputs the digital
`video data C consisting of L bits With Which a difference in
`luminance characteristics betWeen the display pixels in the
`planar display is corrected. The digital video data C con
`sisting of L bits output from the multiplier 12 is input to the
`signal line drive circuit 13.
`The signal line drive circuit 13 receives the video data C
`With Which a difference in the luminance characteristics
`betWeen the display pixels is corrected, and provides a
`display pixel drive voltage Which is required to perform
`gradation display to the planar display 17 in a one-scanning
`line unit. In the planar display 17, sWitching elements and
`
`4
`display pixels are provided in the vicinity of each intersec
`tion of a plurality of signal lines 1311 and a plurality of
`scanning lines 1611.
`The scanning line drive circuit 16 sequentially supplies
`ON signals to the sWitching elements corresponding to one
`scanning line of the planar display 17 from the top scanning
`line in accordance With each horizontal scanning period. As
`a result, a drive voltage (a video signal) in the one-scanning
`line unit from the signal line drive circuit 13 is sequentially
`supplied to pixels corresponding to one scanning line of the
`planar display 17 from the top scanning line. In this manner,
`the planar display 17 displays a video image corresponding
`to the video data C input to the signal line drive circuit 13.
`The correction data Will noW be described.
`FIG. 2 is a vieW schematically shoWing irregularities in
`luminance for pixels in a general planar display 17.
`In this example, it is assumed that a luminance distribu
`tion of the planar display 17 When a video signal having the
`same gradation value of R, G and B (Which is so-called
`raster White) is input is a distribution shoWn in FIG. 2. That
`is, a horizontal axis represents a luminance, and an average
`luminance of all pixels is illustrated as 1.0. Furthermore, a
`vertical axis represents the number of pixels in the planar
`display 17 Which are turned on With a luminance x (a
`luminance value represented by the horizontal axis).
`In order to reduce irregularities in luminance of the planar
`display 17, the video data A is corrected in this embodiment.
`That is, in cases Where irregularities in luminance are
`generated When the video signal having the same gradation
`value of R, G and B of, e. g., raster White is input to the planar
`display 17, the video data A is corrected so that a pixel
`having a high luminance is displayed With the same lumi
`nance as a pixel having a loW luminance. Speci?cally, each
`of R, G and B signals of the video data A is multiplied by
`the correction data B Which is required to reduce the
`gradation value With respect to a pixel having a high
`luminance.
`For example, in FIG. 2, correction can be performed by
`multiplying each of R, G and B signals of the video data A
`by the correction data Which is required to reduce the
`gradation value With respect to a pixel having a luminance
`higher than a target luminance La so that all pixels having
`the luminance higher than the luminance La can be dis
`played With the luminance La. As Will be described later, the
`target luminance La can be appropriately set in accordance
`With each display. If the target luminance is set to, e.g.,
`0.8the correction is carried out so that a display pixel having
`a luminance higher than 0.8 can be displayed With the
`luminance 0.8.
`An operation of the multiplier 12 Will noW be described
`taking LIMINIIO (bits) as an example. In this case, the
`multiplier 12 multiplies the video dataAconsisting of 10 bits
`by the correction data B consisting of 10 bits, and outputs the
`most signi?cant 10 bits corresponding to a result of the
`multiplication as video data C. That is, the multiplier 12
`multiplies the video data A consisting of 10 bits by the
`correction data B consisting of 10 bits, and divides the
`multiplication result by 2 to the 10th poWer (:1024).
`A further concrete embodiment according to this embodi
`ment Will noW be described With reference to FIG. 3. As
`compared With FIG. 1, in the embodiment shoWn in FIG. 3,
`a non-volatile memory 18 and a data interpolation portion 20
`are additionally provided.
`The correction value memory 14b comprises a semicon
`ductor memory such as a DRAM or an SRAM, and this is
`a non-volatile memory Which cannot keep data stored
`therein for a long time When a poWer is not supplied thereto
`
`40
`
`45
`
`55
`
`60
`
`65
`
`8
`
`

`
`US 7,345,713 B2
`
`5
`(When the power supply is turned o?). The non-volatile
`memory 16 comprises a semiconductor memory such as an
`EEPROM, and can keep data stored therein even When a
`poWer is not supplied thereto.
`Whether the poWer is supplied to the correction value
`memory 14b can be detected by a non-illustrated CPU.
`When turning off the poWer supply of the display apparatus
`(With respect to the correction value memory 14b) is
`instructed by a user through a non-illustrated operation
`portion, the CPU transfers correction data stored in the
`correction value memory 14b from the correction value
`memory 14b to the non-volatile memory 18. Moreover,
`When turning on the poWer supply of the display apparatus
`(With respect to the correction value memory 14b), the CPU
`transfers correction data stored in the non-volatile memory
`18 from the non-volatile memory 18 to the correction value
`memory 14b.
`Correction data B consisting of P bits (the bit number is
`P) stored in the correction value memory 14b is input to the
`data interpolation portion 20. The data interpolation portion
`20 converts the input correction data B consisting of P bits
`into interpolation data C consisting of M bits Whose bit
`number is larger than P, and outputs the converted data. The
`interpolation data C consisting of M bits output from the
`data interpolation portion 20 is input to the multiplier 12.
`The multiplier 12 multiplies N-bit data (video data A)
`supplied from the analog-to-digital converter 11 by the
`M-bit data (interpolation data C) fed from the data interpo
`lation portion 20, and outputs the most signi?cant L bits
`Which is a result of the multiplication as video data D.
`Interpolation processing of the correction data in the data
`interpolation portion 20 Will noW be more concretely
`described hereinafter. Here, a description Will be given on an
`example Where the video data A consists of 10 bits, the
`correction data B consists of four bits, the interpolation data
`C consists of 10 bits and the video data D consists of 10 bits.
`The correction data stored in the non-volatile memory 18
`consists of four bits like the correction data B. Therefore, the
`non-volatile memory 18 stores the data Whose bit number is
`smaller than 10 bits of the video data A.
`FIG. 4 is a vieW illustrating the interpolation processing
`of the correction data.
`It is assumed that the correction data B consisting of four
`bits output from the correction value memory 14b is repre
`45
`sented by binary digits YYYY as shoWn in FIG. 4A. YYYY
`shoWn in FIG. 4B represents the correction data B consisting
`of four bits Which is input to the data interpolation portion
`20. That is, FIG. 4 shoWs the processing Which assigns the
`correction data B consisting of four bits to predetermined
`bits in the data consisting of 10 bits in the data interpolation
`portion 20. In this example, the correction data B is assigned
`to the predetermined bits (b(bit)4 to b7) in the 10-bit data,
`and bits (b0 to b3, b8 and b9) other than the predetermined
`bits are determined as 1, thereby creating the interpolation
`data C consisting of 10 bits.
`As described in conjunction With FIG. 1, the video data A
`consisting of 10 bits and the interpolation data C consisting
`of 10 bits are input to the multiplier 12 and subjected to an
`arithmetic operation (multiplication). As a result, the video
`data D Which is digital data consisting of 10 bits With Which
`a difference in luminance characteristics betWeen display
`pixels in the planar display 17 is corrected is output from the
`multiplier 12. Speci?cally, the multiplier 12 outputs the most
`signi?cant 10 bits of an operation result of the above
`described arithmetic operation (multiplication) as the video
`data D.
`
`55
`
`50
`
`60
`
`65
`
`20
`
`25
`
`30
`
`35
`
`40
`
`6
`In this example, giving a description on the above
`described arithmetic operation provided that the video data
`A is A, the interpolation data C is C and the video data D is
`D, D:A><C/ 1024 can be represented. That is, since the video
`data A is data obtained by digitiZing the original input video
`signal (the analog RGB video signal), the video data D is
`data obtained by multiplying the original input video signal
`(the analog RGB video signal) by C/ 1024 (1024:2 to the
`10th poWer).
`Additionally, in this example, When the correction data B
`output from the correction value memory 14b changes by
`binary 1, the interpolation data C output from the data
`interpolation portion 20 varies by decimal 16.
`That is, When the correction data B changes by “1” on the
`decimal base, the original input video signal (the analog
`RGB video signal) varies by an amount corresponding to
`16/1024z0.016 times. Based on this, it can be understood
`that the video signal can be corrected in increments of
`approximately 1.6%. The correction data B has 15 patterns
`of 0000 to 1110, and the input video signal When the
`correction data B:1111 is output to the signal line driver 13
`as it is. Therefore, the interpolation data C output from the
`data interpolation portion 20 can take values from
`1100001111 to 1111111111. Amaximum value ofchange is
`(16/1024)><15z0.234. Therefore, the correction of approxi
`mately 23.4% is possible (Dz0.766A).
`A correction range and a correction accuracy are deter
`mined in accordance With a position of the correction data B
`indicated by YYYY in FIG. 4B. For example, When the
`correction data B is assigned to b5 to b8 in the 10-bit data
`(When the data is shifted to the left side by one bit), the
`correction range becomes approximately double, but the
`correction accuracy is approximately half. Conversely, When
`the correction data is shifted to the right side by one bit, the
`correction range becomes approximately half, but the cor
`rection accuracy is approximately double. Further, one or
`both of the range and the accuracy of correction can be
`changed by varying the bit number of the correction data. A
`position and the bit number of the correction data B in the
`interpolation data C can be set in accordance With charac
`teristics and a use application of the planar display 17.
`A capacity of the correction value memory 14b required
`in this embodiment is 4 (gradations)><1280 (a horizontal
`direction)><3 (RGB)><720 (a vertical direction)z11.1 Mbits.
`When a memory for 10-bit data is used in accordance With
`the video data A as the correction value memory like a
`conventional video display apparatus, a capacity of 10
`(gradations)><1280><3><720z27.6 Mbits is required. Accord
`ing to the above-described method, hoWever, since a data
`quantity of the correction data can be reduced, it is suf?cient
`for the correction value memory that a capacity of 11.1
`Mbits is assured. As compared With the conventional cor
`rection value memory, therefore, the correction value
`memory according to this embodiment can reduce a capacity
`of 27.6-11.1:approximately 16.5 Mbits.
`Furthermore, When the poWer supply of the apparatus is
`turned o?‘, the correction data B stored in the correction
`value memory 14b is transferred and stored in the non
`volatile memory 18 as described above. At this moment,
`according to this embodiment, since a data quantity of the
`correction data B is small, the memory capacity used in the
`non-volatile memory 18 can be likeWise reduced.
`When reduction quantities of the memory capacities used
`in both the correction value memory 14b and the non
`volatile memory 18 are added, a capacity of approximately
`16.5+approximately 16.5:approximately 33.0 Mbits can be
`reduced based on the above description.
`
`9
`
`

`
`US 7,345,713 B2
`
`7
`EMBODIMENT 2
`
`A second embodiment according to the present invention
`Will noW be described. FIG. 5 is a block diagram showing a
`structure of the second embodiment. Like reference numer
`als denote structures equivalent to those in the foregoing
`embodiment, thereby eliminating the explanation.
`Reference numeral 21 denotes a data interpolation portion
`according to the second embodiment. The data interpolation
`portion 21 has a correction bit control portion added to the
`data interpolation portion 20 in the ?rst embodiment.
`The data interpolation portion (the correction bit control
`portion) 21 outputs from a correction value memory 14b
`data consisting of M bits by using correction data consisting
`of P bits Which is used to correct, especially, the difference
`in luminance characteristics betWeen display pixels in a
`planar display.
`The data interpolation portion 21 according to the second
`embodiment “selectively” interpolates the correction data B
`consisting of P bits output from the correction value memory
`14b in the data consisting of M bits. That is, the data
`interpolation portion 21 assigns the correction data B con
`sisting of P bits to predetermined bits in the M-bit data,
`determines bits to Which the correction data is not assigned
`as 1, creates interpolation data C, and outputs the created
`data to a multiplier 12.
`Concrete processing Which selectively interpolates the
`correction data in the interpolation data Will noW be
`described hereinafter provided that video data A output from
`an analog-to-digital converter 11 consists of 10 bits, correc
`tion data B output from the correction value memory 14b
`consists of four bits, interpolation data C output from the
`data interpolation portion 21 consists of 10 bits and video
`data D output from the multiplier 12 consists of 10 bits.
`FIG. 6 is a vieW illustrating the selective interpolation
`processing for the correction data according to this embodi
`ment of the present invention. First, a user uses an operation
`portion (not shoWn) of this video display apparatus in order
`to select a correction mode required to set the precision of
`the correction. When the correction mode is selected, cor
`rection data according to the mode is loaded from the
`non-volatile memory 18 to the correction value memory
`14b.
`A description Will be ?rst given as to an example Where
`a correction mode required to perform the correction With a
`large (rough) correction range is selected.
`FIG. 6A is a vieW illustrating a state of interpolation of the
`correction data When the correction mode With a large
`correction range is selected. Binary numeral YYYY on the
`left side in FIG. 6A indicates correction data B consisting of
`four bits input to the data interpolation portion 21. The right
`side in FIG. 6A indicates interpolation data C1 consisting of
`10 bits output from the data interpolation portion 21. The
`interpolation data C1 is data b0 to b9 consisting of 10 bits.
`Since the correction mode With a large correction range is
`selected in this example, the four-bit correction data is
`assigned to, e.g., b4 to b7 in the 10-bit data. Furthermore,
`other six bits to Which the correction data B is not assigned
`are determined as 1. Then, like the ?rst embodiment, the
`interpolation data C1 (1 lYYYYlll on the binary base) is
`output from the data interpolation portion 21.
`The interpolation data C1 (llYYYYllll) from the data
`interpolation portion 21 is multiplied by the digital video
`data A output from the analog-to-digital converter 11 in the
`multiplier 12. The rough correction can be performed With
`respect to the digital video data A in increments of approxi
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`mately 1.6% based on YYYY in the interpolation data C1.
`In this example, a maximum correctable range is approxi
`mately 23.4% (D:0.766A).
`It is to be noted that the description has been given as to
`the example Where the four-bit correction data B is assigned
`to b(bit)4 to b7 in the 10-bit data as an example of the
`correction mode With a large correction range. As described
`above, hoWever, When the correction data B is assigned to
`higher order bits, e.g., b5 to b8, b6 to b9 or the like in the
`10-bit data, the correction range becomes larger. Such a
`range can be used as one of the correction mode alternatives.
`An example Where a correction mode required to perform
`correction With a small (?ne) correction range is selected
`Will noW be described.
`FIG. 6B is a vieW illustrating a state of interpolation of the
`correction data When a correction mode With a small cor
`rection range is selected. Binary numeral YYYY on the left
`side of FIG. 6B indicates correction data B consisting of four
`bits input to the data interpolation portion (the correction bit
`control portion) 21. The right side of FIG. 6B indicates
`interpolation data C2 consisting of 10 bits output from the
`data interpolation portion 21. The interpolation data C2 is
`data b0 to b9 consisting of 10 bits.
`Since the correction mode With a small correction range
`is selected, the correction data B (binary numeral YYYY)
`Whose bit number is four is assigned to, e.g., bits b3 to b6
`in the 10-bit data. Moreover, other bits to Which the correc
`tion data B is not assigned are determined as 1. Then, the
`interpolation data C2 (binary numeral 111YYYY111) is
`output from the data interpolation portion 21.
`The interpolation data C2 (binary numeral 111YYYY111)
`from the data interpolation portion 21 is multiplied by the
`digital video data A output from the analog-to-digital con
`verter 11 by the multiplier 12. When data in the correction
`value memory changes by 1, the interpolation data C2 varies
`by 8 (:2 to the third poWer) on the decimal base. In this
`example, 8/ 1024z0.008 (approximately 0.8%) is achieved.
`That is, the correction can be performed With respect to the
`digital video data A in increments of approximately 0.8%.
`The correction data B has 15 patterns of 0000 to 1110 and,
`When the correction data BIl 111, the video data A is output
`from the multiplier 12 as it is. Therefore, the interpolation
`data C2 output from the data interpolation portion 20 can
`take values from 1110000111 to 1111111111. Additionally,
`8/1024><15z0.117 (approximately 11.7%) is attained. There
`fore, a