United States Patent [19J
`Miller
`
`[54] PROGRAMMABLE ARITHMETIC LOGIC
`UNIT
`Inventor: Gary I. Miller, Los Angeles, Calif.
`[75]
`[73] Assignee: The Unite States of America as
`represented by tbe Secretary of tbe
`Air Force, Washington, D.C.
`[21] Appl. No.: 357,440
`[22] Filed:
`Mar. 12, 1982
`Int. C1.3 .•••.................... G06F 7/50; H03K 19/20
`[51]
`[52] u.s. Cl ...................................... 3641716; 364!749
`[58] Field of Search ....................... 364/716, 736, 749;
`307/465
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,751,650 8/1973 Koehn ................................. 364/716
`3,875,391 4/1975 Shapiro et al ....................... 235/156
`4,025,771 5/1977 Lynch, Jr. et al .................. 235/156
`4,041,461 8/1977 Kratz et al .......................... 364/200
`4,075,704 2/1978 O'Leary .............................. 3641748
`4,110,822 8/1978 Porter et al ......................... 364/200
`OTHER PUBLICATIONS
`Kogge, "The Microprogramming of Pipelined Proces-
`
`[11]
`
`[45]
`
`4,454,589
`Jun. 12, 1984
`
`sors", IBM Federal Systems Division, Owego, N.Y.,
`pp. 63-69.
`
`Primary Examiner-David H. Malzahn
`Attorney, Agent, or Firm-Donald J. Singer; Willard R.
`Matthews
`
`[57]
`ABSTRACf
`A programmable arithmetic logic unit for performing
`high speed bit sliced, pipelined computations at very
`low power is fabricated as an LSI component using
`CMOS/SOS technology. It is microprogrammable and
`operates in conjunction with a fast microprogram store
`program memory and controller. Dual input ports
`which supply data from eight sources are latched and
`operated on while new data is simultaneously fetched.
`Instruction bits shift data in either port left or right,
`select complements and select an operand between de(cid:173)
`vice input and output data in one port. The data pro(cid:173)
`cessed in each port is compared and is added to provide
`a latched tri-state output to an external device.
`
`5 Claims, 1 Drawing Figure
`
`D.l/7.11 .INPUTol
`
`SEI.GCT
`.11!1/7'"8
`
`:(JUT
`
`WEBASTO EX. 1025
`WEBASTO ROOF SYSTEMS, INC. v. UUSI, LLC
`IPR2014-00650
`Page 1
`
`

`

`\0
`00
`Ul
`~ ...
`Ul
`~
`~ ...
`
`~
`00
`
`c... = ? -J'> -\0
`
`~ a ('D a
`e . en .
`
`I
`•• "'-17
`
`-
`
`I
`I -rT •
`
`I
`
`>OUT
`
`:OUT
`~Ot.l-r
`
`NO OP
`Sr;ftJIE
`
`C41l7lY ZN
`
`l
`
`I
`
`14
`
`/Brr
`
`0UrPvr
`:-4-
`.3' $T,t?7"G
`ovr
`
`C/nf7(y 4
`
`Oi.lrPUr GA//18/..E
`
`COMPARE 1; ~rN~ur }"11$~1/.DG
`I yiN:--·--.----.• ~ SG~'l~f.
`
`eONT7i>OL
`
`ri,Y?OVT
`
`-
`
`11
`-~ .. 10
`
`J l'11MPLG'M.gtT'
`.
`
`I
`
`f6
`
`I
`
`~8/r
`.SGLECT
`
`3
`
`.S£L.FCT
`
`C£ OCI('
`
`,I~
`
`$8/rs'
`SGL.GCT
`
`•
`
`,
`
`1
`
`,
`
`Pt:nf!T • .
`?li~Nr
`
`Pd'RT
`LEFT
`
`3B/7S
`SclGC7'
`
`ZJR'T/1 ./NPI.I'TJ
`
`.D;t:?T~ .TNPVTS
`
`Page 2
`
`

`

`1
`
`4,454,589
`
`PROGRAMMABLE ARITHMETIC LOGIC UNIT
`
`2
`controlled by the program memory. One channel also
`includes an operand select function. Data from the two
`signal processing channels are summed in a full adder
`and its three state output is latched and strobed through
`STATEMENT OF GOVERNMENT INTEREST
`The invention described herein may be manufactured 5 lin output AND gate. A compare function is also pro-
`vided for the two signal processing channels. Five 4 bit
`and used by or for the Government for govermtJ.ental
`purposes without the payment of any royalty thereon.
`slice devices are cascaded in a pipeline configuration to
`provide a full multiply function with a 4 bit multiplier
`and a 16 bit multiplicand.
`BACKGROUND OF THE INVENTION
`This invention relates to signal processing circuits 10
`It is a principal object of the invention is to provide a
`and in particular to an LSI-CMOS/SOS implemented
`new and improved programmable arithmetic logic unit.
`It is another object of the invention to provide a
`programmable arithmetic logic unit.
`programmable arithmetic logic unit that performs at
`The signal processing requirements of advanced
`higher speeds than currently available devices of that
`radar and communications systems are currently calling
`for higher speed digital data processing with low power 15 type.
`It is another object of the invention to provide a
`devices. A typical signal processing application in this
`category is the USAF "HALO signal processor" which
`programmable arithmetic logic unit that has lower
`requires high speed (8-16 MHz) bit sliced, pipelined
`power requirements than currently available devices.
`It is another object of the invention to provide a low
`computation of large arrays in space at low power.
`State-of-the-art signal processing elements are gener- 20 power high' speed programmable arithmetic logic unit
`that is fabri9ated as a CMOS/SOS LSI circuit.
`ally incapable of producing these processing speeds at
`It is another object of the invention to provide a low
`acceptable power levels. The most effective processing
`power high speed programmable arithmetic logic unit
`element currently available is the RCA Corporation
`in which all operations are programmable and are per(cid:173)
`"ATMAC data execution unit" that is developed from
`CMOS/SOS for very high. speed and low power. se- 25 formed simultaneously in one clock period.
`quential operation. The ATMAC un~t, :however, does
`These together with other objects, features and ad-
`vantages of the invention will become more readily
`not execute its arithmetic operation simultaneously and
`therefore is effectively slower than the processing
`apparent from the following detailed description when
`speeds required. Also the ATMAC unit cannot input
`taken in conjunction with the illustrative embodiment in
`and output data simultaneously and it utilizes a single 30
`the accompanying drawing.
`
`h s ared bus. The single shared bus us~s more power Que
`DESCRIPTION OF THE DRAWING
`to the additional capacitance loads t:Q.at must be driven.
`The sole FIGURE of the drawing is a functional
`The programmable arithip.etic logic unit of the pres-
`ent invention is microprogrammable and operates in
`conjunction with a fast· microprogram store (control 35 bloc~ diagram of the programmable arithmetic logic
`unit of the invention.
`store) program memory and a program controller. As
`distinguished from the RCA device and other prior art
`DETAILED DESCRIPTION OF THE
`processing elements it performs all of its operations
`PREFERRED EMBODIMENT
`simultaneously at high Speed:-low power factor related
`The programmable arithmetic unit (PAU) of the in-
`to the CMOS/SOS technology. Power requirements 40
`are reduced by means of an 8:1 input multiplexer and
`vention is preferably fabricated as an LSI circuit utiliz-
`separate input and output buses. It simultaneously per-
`ing CMOS/SOS techniques. Multiple cascaded slice
`elements are arranged in a pipeline configuration to
`forms duel port 8: 1 input data selection and fetch, shifts
`either port left or right, complements, adds, compares,
`achieve a full multiplier function. The sole FIGURE of
`and provides a latched tri-state output to an external 45 the drawing illustrates the PAU circuit configuration of
`device. All of these operations are programmable and
`one slice. The circuit comprises two signal processing
`are performed simultaneously in one clock period. The
`chamiels designated as LEFT PORT and RIGHT
`overall effect of the combination of techniques and
`PORT. The first channel comprises input multiplexer 1,
`improvements is to provide a processing device having
`latch 2, operand select multiplexer 3, shift multiplexer 4,
`increased processing speed and reduced power require- 50 data . complement function 5; and complement select
`multiplexer 6. The second channel comprises input
`ments.
`multiplexer 7, latch 8, shift multiplexer 9, data comple(cid:173)
`ment function 10 and complement select multiplexer 11.
`The outputs of the signal processing channels are
`summed in full adder 12 and outputted through output
`latch 13 and output AND gate 14. Compare function 16
`compares channel data and its output is latched by latch
`17. Latches 13 and 17 are strobed through AND gate 15
`by the system clock. The P AU is designed to operate
`with a high speed program memory and a program
`address controller. Structurally, each 4 bit slice PAU
`device requires 103 pins including 2 pins for power. All
`operations hereinafter described occur simultaneously
`in one clock tick in a pipelined fashion. The program
`memory supplies a 14 bit instruction word to the PAU.
`Six bits of the word selects input data for 2 ports from
`8 sources each. The data is latched and operated on
`during the next clock while new data is simultaneously
`
`SUMMARY OF THE INVENTION
`The invention is a programmable arithmetic logic
`unit designed for use as a signal processing element in 55
`the filter and encoder units of a signal processor. It
`operates in conjunction with a fast microprocessor store
`program memory and a program controller. Structur(cid:173)
`ally it is fabricated as a layered LSI circuit using
`CMOS/SOS technology. Functionally it comprises two 60
`signal processing channels each having a latched input
`multiplexer that accepts 4 bit words from 8 separate
`sources and selects data to be operated on in response to
`select signals from the program memory. The data are
`latched and operated on during the next clock while 65
`new data is simultaneously fetched. Each channel also
`includes a shift multiplexer, a data complement function
`and a complement select multiplexer, all functions being
`
`Page 3
`
`

`

`3
`fetched. The left input port receives an instruction bit to
`select between output and input data as an operand.
`Two instruction bits are received by each port to cause
`a 1 bit shift in the left or right direction or none. The
`MSB's and LSB's are transferred between the 4 bit 5
`slices for cascading the shift operation. One instruction
`bit is received by each port to select the complement of
`the word for subtraction. The two ports are next fed
`into a full adder whose output is latched by the clock.
`"Carry In" and "Carry Out" are used to cascade the 10
`chips. The adder along with the shift multiplexer and
`complement provide a 1 bit multiplier capability with
`each clock tick. The multiplier or divider word must be
`decoded externally, such as in the address controller to
`determine if the multiplicand is added to the product. 15
`The output latch is not updated during a no-op instruc-
`tion. Five slices are required to perform a full multiply
`function with a four bit multiplier and a 16 bit multipli-
`cand.
`While the invention has been described in its pres- 20
`ently preferred embodiment it is understood that the
`words which have been used are words of description
`
`~~~;~~:w :~~~: ~p~~~~:~o~l::s t!~yc~;nr::~ew:~~~
`
`4
`of said first shift multiplexer and outputting one of
`said received outputs in response to a select signal
`from said program memory;
`said second channel comprising
`a second input multiplexer receiving n, m bit data
`inputs, n being an integer, said second input multi-
`plexer being controlled by a select signal from said
`program memory,
`a second latch means receiving and outputting the
`output of said second input multiplexer, said sec-
`ond latch means being strobed by a clock and hold-
`ing the output of said second input multiplexer
`during a clock count,
`a second shift multiplexer receiving the output of said
`second latch means and outputting shifted and
`non-shifted data in response to shift signals from
`said program memory,
`a second data complement means receiving the out-
`put of said second shift multiplexer, and
`a second complement select multiplexer receiving the
`output of said second data complement means and
`the output of said second shift multiplexer and
`
`~:~:~~:~ ~:~f :r:! r:~i;~~;:u:e:~;;~:~~
`
`4,454,589
`
`out departing from the scope and spirit of the invention 25
`adder means receiving the output of said first channel
`in its broader aspects.
`What is claimed is:
`complement select multiplexer and the output of
`said second channel complement select multiplexer
`1. In combination with a high speed program mem-
`and providing an arithmetic logic unit output
`ory and a program address controller a programmable
`therefrom.
`arithmetic logic unit having an output, said programma- 30
`2. In combination with a high speed program mem-
`ble arithmetic logic unit comprising:
`ory and a program address controller a programmable
`at least one m bit circuit element, m being an integer,
`having first and second channels,
`arithmetic logic unit as defined in claim 1 including
`said frrst channel comprising
`an output latch receiving the output of said adder
`a first input multiplexer receiving n, m bit data inputs, 35
`means and being strobed by a clock, and
`an AND gate receiving the output of said output
`n being an integer, said first input multiplexer being .
`latch and an output enable signal from said pro-
`controlled by a select signal from said program
`gram memory and outputting a three state output.
`memory,
`a first latch means receiving and outputting the out-
`3. In combination with a high speed program mem-
`put of said first input multiplexer, said first latch 40 ory and a program address controller a programmable
`means being strobed by a clock and holding the
`arithmetic logic unit as defmed in claim 2 including a
`output of said frrst input multiplexer during a clock
`comparison circuit, said comparison circuit comprising
`count,
`a comparator means receiving the output of said frrst
`an operand select multiplexer receiving the output of
`channel operand select multiplexer and the output
`said first latch means and the output of said pro- 45
`of said second channel latch means, and
`grammable arithmetic logic unit and outputting
`an output latch receiving the output of said com para-
`one of said received outputs in response to a select
`tor means.
`4. In combination with a high speed program mern-
`signal from said program memory,
`a first shift multiplexer receiving the output of said
`ory and a program address controller a programmable
`operand select multiplexer and outputting shifted 50 arithmetic logic unit as defmed in claim 3 wherein m=4
`and non-shifted data in response to shift signals
`and n = 8.
`from said program memory,
`5. In combination with a high speed program mern-
`a first data complement means receiving the output of
`ory and a program address controller a programmable
`arithmetic logic unit as defined in claim 4 wherein said
`said first shift multiplexer and
`a complement select multiplexer receiving the output 55 m bit circuit elements are LSI CMOS/SOS slices.
`• * *
`*
`of said frrst data complement means and the output
`
`60
`
`65
`
`Page 4
`
`