1
`
`GOOGLE-1018
`Google Inc. v. Micrografx LLC
`IPR2014-00532
`
`

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`U.S. Patent Nov. 11,1986
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`U. S. Patent Nov. 11,1986
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`U.S. Patent Nov. 11, 1986
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`U.S. Patent Nov. 11,1986
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`U.S. Patent Nov. 11,1986
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`Sheet 10 ofll 4,622,633
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`
`U.S. Patent Nov. 11,1986
`
`Sheet 11 ofll 4,622,633
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`

`
`1
`
`4,622,633
`
`OBJECT BUILDING ME'I'I'IOD FOR SELF
`CONFIGURING COMPUTER NETWORK
`
`BACKGROUND OF THE INVENTION
`
`The invention relates to computer networks, espe-
`cially computer networks having a large number of
`nodes, for example, up to one hundred. and relates more
`particularly to networks wlich autornatically reconfig-
`ure themselves when hardware modules or software
`modules are added to or removed from the network.
`Various computer networks are known in which
`multiple individual computers are interconnected and
`cooperate in various ways with each other. For exam-
`ple. one well known computer network is widely anar-
`keted under the trademark ETI-IERNET. For more
`general
`information on computer networks, see the
`textbook "Computer Networks", by A. S. Tannen-
`baum. Prentice-Hall, Inc.. 1931. Also see U.S. Pat. No.
`4,131,936. which represents the closest prior art pres-
`ently known. Other U.S. patents that generally disclose
`computer networks include U.S. Pat. Nos. 3.735.365.
`4,181,936. 3.753.234, 3.934.232, 3,818,114. 3310.351.
`4.099.233. 4.079.433, 4.110.823, 3,4-8{l,9l4. 3.593.300,
`3,629,854, 4,240,140, 4,385,350 and 4,360,369.
`One area of growth in the use of computer networks
`has been in the field of “factory control", i.e.. use of
`computer networks to accomplish control of manufac-
`turing processes and controlling robots in manufactur-
`ing operations. Although state-of-the-art microproces-
`sors and microcomputers have quite limited computing
`power,
`they nevertheless have sufiicient computing
`power to perform one or more related or unrelated
`control functions. But they do not have enough com-
`puting power to control all related interfaces in the
`system. In accordance with the concept of computer
`networking. additional processors or microcomputers
`are connected to the same bus, i.e., the network system
`bus. in order to provide computing needed for control-
`ling additional processing operations, robots, etc.
`In
`many instarlces. there is no requirement for the separate
`processors to be able to communicate with each other,
`but in other instances. it would be very desirable if they
`could efficiently communicate with each other.
`The prior networking systems have had some serious
`shortcomings, including the requirement of requiring
`custom wiring or rewiring of hardware when additional
`processors or 1/0 interface boards are added to the
`system. Furthermore. addition of additional processors
`and/or "interfaces" has generally required that
`the
`software in the computer network also be modified,
`usually requiring considerable time. eifort and expense.
`in order to allow continued operation of the computer
`network. In computer networks in which there are a
`large number (more than four or live) separate proces-
`sors, bus arbitration systems including complex hard-
`ware and software have been required. The amount of
`time each processor spends “waiting” for accem to the
`network system bus rises rapidly as the number of pro-
`cessors incresses. In factory control environments, reli-
`ability is of extreme importance for network control
`systems, since system "down time" can be extremely
`expensive. Therefore, it is extremely important in fac-
`tory control computer systems to avoid hardware and
`software errors that typically accompany expansion or
`modification of the system. As mentioned above. cus-
`tom hardware reconfiguration and software modifica-
`tion is usually required and errors frequently occur. For
`
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`example, strapping switches frequently are improperly
`reset when new module are added to the systems. Soft-
`ware modifications and software "modules" added to
`the system frequently contain errors and need consider-
`able debugging to make the entire system function prop-
`erly.
`In prior network systems in which multiple proces-
`sors and their associated memories are connected to a
`common network system bus. a particular procmsor
`that requests access to the system bus often has to wait
`in a "queueing" line, unless there is complex software in
`a system that maintains that processor's position in the
`queueing line while it continues another task.
`In prior networking systems, every time a new func-
`tion is added to a new network. every processor in the
`system needs to know how to obtain acess to the new
`function. This ordinarily requires modification of all of
`the software programs already in the system. since each
`of the local procasors in prior systems completely ef-
`fectuate their own messages.
`Indefinite amounts of waiting time for a processor
`requesting access to the network bus are unacceptable
`in a real time operating system. In order to avoid this
`problem, sortie prior systems. for example, the Intel
`MUI..'I'I-BUS structure. has been used in conjunction
`with dual port random access memories which isolate
`the various local processors from the network bus. This
`technique has the advantage that it eliminates the. re-
`quirement for a processor initiating a communication
`and a dwlination processor to both stop their present
`tasks and make themselves available in order to accom-
`plish the communication between them. but the initiat-
`ing processor needs to stop its present task and make
`itself available until the message is communicated.
`A practical limitation of previous networking systems
`is related to the physical structure of the printed circuit
`boards and the mother board into which the various
`boards (including the processors and the interface
`boards) are plugged. Some manufacturers have pro-
`vided "piggyback" boards which are plugged into a
`main processor board. but this is a very clumsy ap-
`proach and limits the number of interface boards that
`can be used. Another approach that has been used is to
`run ribbon cables from connectors on various processor
`boards to a separate board rack into which interface
`boards are connected. Again, this has been a clumsy
`solution. Another approach that has been used is to
`provide separate "local" buses for the individual pro-
`cessors. But this approach has generally. required "cus-
`tom" wiring when additional interface boards are added
`to the system. because there has been no practical way
`of achieving a satisfactory length for the local printed
`circuit conductors constituting the local buses as addi-
`tioual interface boards are plugged in.
`Up to now, no one has ever provided a satisfactory
`solution of the problems amociated with a computer
`network that needs to be operable on any scale from
`very small (wherein only one or two processors are
`required) to very large (where. for example. up to one
`hundred or more processors are needed). No one has
`adequately addressed or solved the problems that arise
`when it is desired to add computing power to a preexist-
`ing computer network in which additional computing
`power is required in such a manner that tasks presently
`assigned to certain processors need to be shared with
`the newly added processors, without requiring exten-
`sive hardware. and/or especially software modification.
`
`13
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`

`
`4,622,633
`
`3
`Up to now. no one has solved the problems associated
`with long waiting tints by individual local processors
`that need to transmit messages to other procemors when
`large numbers of local processors are connected to the
`network and concurrently request access to the system
`bus.
`
`SUMMARY OF THE INVENTION
`
`25
`
`35
`
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`
`Accordingly. it is an object of the invention to pro-
`vide a computer network that can be conveniently
`scaled from small smile operation with only one or a few
`processors to a large number of processors.
`It is another object of the invention to provide a
`computer network in which a large number of proces-
`sors can be added without proportionately increasing
`the amount of time that is required for a particular pro-
`cessor to spend sending and/or receiving message to
`other processors.
`It is another object of the invention to greatly reduce
`the complexity of the problems associated with com-
`plex bus arbitration schemes of the prior art.
`It is another object of the invention to provide a
`computer network which can be expanded by merely
`plugging in additional processors or interface modules
`and which is operable without modification of either
`hardware or software presently in the system.
`It is another object of the invention to avoid the need
`for resetting strapping switches when interfaces (i.e..
`input/output interface circuit board) or processors are
`added to or removed from a computer network system.
`It is another object of the invention to provide a
`completely modular network system,
`in which both
`hardware and software are modular and can be added to
`or removed from the system without undue difficulty.
`It is another object of the invention to provide a
`computer network system that automatically reconfig-
`ures itself when hardware modules or software modula
`are added to or removed.
`Briefly described. and in accordance with one em-
`bodiment thereof. the invention provides a method of 40
`operating a computer system including a first processor
`and a plurality of removable interface circuits by stor-
`ing in a data base a plurality of hardware descriptors
`each including a separate identifier for each interface
`circuit that can be plugged into the computer system.
`and also storing in the data base a plurality of compo-
`nent lists each corresponding to separate interface cir-
`cuits and each including a name and at least one attri-
`bute of each component of the interface circuit. and also
`storing in the data base software templates each includ-
`ing descriptions of data structures descriptive of the
`various components, names of code elements to be in-
`cluded in a software object to be built and representing
`a particular one of the interface circuits, and pointers to
`software to be executed to build such software objects.
`To build a software object corresponding to one of the
`interface circuits. one of the hardware dacriptors is
`obtained from the data base. ‘I‘hat hardware descriptor
`is used to obtain a list of components of the subject
`interface circuit. The name of the component is then
`used to obtain a software template from the data base
`corresponding to a component of the interface circuit.
`The software template then is used by the software
`pointed to in order to build a software object that it
`represents at least one function that can be performed
`by that component. An object name is assigned to the
`built software object and entered with the software
`object into the data base. During execution of the user
`
`65
`
`4
`process. the ob}ect name is used to obtain the software
`object from the data base. Any interface circuit that
`contains only components for which templates are
`stored in the data base can be inserted into or removed
`from the computer system without modification to the
`operating software of the computer system.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of the self-configuring
`computer network system of the present invention.
`FIG. 2 is a block diagram of the system processor unit
`(SPU) in the diagram of FIG-. 1.
`FIG. is a block diagram of a dedicated processor unit
`that can be used in an alternate embodiment of the in-
`vention.
`FIG. 4 is a bloclt diagram of a local processor unit
`[LPU) in a diagram of FIG. I.
`FIG. 5 is a detailed block diagram of an interface
`circuit in the diagram of FIG. 1.
`FIG. 6 is a detailed block diagram showing interface
`circuitry included in the local processors in the diagram
`of FIG. 1.
`FIG. 6A is a detailed block diagram of one of the
`address decode circuits in FIG. 6.
`FIG. 6B is a detailed block diagram of the interrupt
`circuit in FIG. 6.
`FIGS. ‘IA-TF constitute a program flow chart of the
`start up procedures for the processors in FIG. 1.
`FIG. I is a flow diagram of an initialization procedure
`executed by the local mm in the block diagram of
`FIG. 1.
`FIG. 9 is a flow chart of an initialization program
`executed by the local processors in FIG. 1 in conjunc-
`tion with the system procemor therein to assign ad-
`dresses to the individual local processors.
`routine in
`FIG. ltl is a flow chart of an
`which the system processor of FIG. I automatically
`assigns addresses to the local processors therein.
`FIG. 11 is a flow chart of a routine which can be
`executed by the system processor and local processors
`in the diagram of FIG. 1 to automatically build subrou-
`tines which represent the circuitry on the various inter-
`face boards connected to the systems.
`FIGS. 12A—‘.l2F constitute a program flow chart of
`the message-passing procedure between different user
`programs that can be executed by the system of FIG. 1.
`FIG. 13 is a perspective diagram that better illustrates
`the connections to the segmented local bus of FIG. 1.
`DESCRIPTION OF THE INVENTION
`
`Before describing the basic functions that the self
`configuring computer network system of the present
`invention provides in order to meet the foregoing objec-
`tives,
`it will be helpful to first understand the basic
`structure of the system as indicated in FIG. 1. and the
`structure of the system processor unit (SPU). local pro-
`cessor units (LPUs}, and interface circuits or boards.
`The structure shown in FIGS- 1-4 will therefore be
`described first. Then, the local bus interface circuitry
`and its basic operation will be described with reference
`to FIG. 5 and the system bus interface and its basic
`operation will be described with reference to FIGS. 6,
`6A and 6B. Then.
`initialization procedures. object
`building, and message passing processes that are parts of
`the present invention will be described in detail.
`Referring now to FIG. 1, self-configuring computer
`network 10 includes a system bus 20 which is connected
`to system processor 18 and a plurality of local proces-
`
`14
`
`14
`
`

`
`5
`
`ll}
`
`15
`
`20
`
`25
`
`35
`
`40
`
`5
`sors 11, 14, 16, etc. System processor 18 is occasionally
`alternately referred to herein as the "communications
`processor", as its primary function is to coordinate
`communications between user programs or "processes"
`that reside in the various local processors 11, 14, etc.
`Eachofthelocalprocessorsisalsoconnectedtoa
`"local bus". For example, local processor 11 is con-
`nected to local bus 21, local promor 12 is connected
`tolocalbus22and localprocessor ltiisconnectedto
`local bus 23.
`As shown in FIGS. 1 and 13, each local bus is con-
`nected to a plurality of removable interface circuits,
`referred to herein as interface boards. Interface boards
`12 and 13 are connected to local bus 21. interface board
`15 is connected to local bus 22 and interface boards 17
`are connected to local bus 23. Each local procmor,
`each interface board, and the system processor is dis-
`posed on a separate printed circuit board with an edge
`connecter that is pluggable into a “mother board" 801
`(FIG. 13) on which the local buses and the systems bus
`are printed.
`System processor 18 also has a local bus 24 connected
`to it. to which one or more interface boards such as 19
`can be connected (although often it would not be neces-
`sary for system processor 18 to utilize a local bus.)
`In accordance with the present invention. each of the
`local buses such as 21 through 24 is “segmented” on the
`mother board 301 into which the various processor
`boards and interface boards are inserted. Any number
`of local processor boards and associated interface
`boards can be plugged into the mother board in such a
`way as to automatically "define" the needed local buses
`to effectuate communication between the local proces-
`sors and their associated interface boards. The physical
`act of plugging in a local processor board connects it to
`only one adjacent segment of the local bus structure.
`The act of plugging in an interface board in the adjacent
`slot of the mother board automatically connects both
`adjacent local bus segments together and hence. extends
`the local bus to the next adjacent slot. However, plug-
`ginginalocalprocessorboardbreakstheconnection,
`because it does not connect one segment of the local bus
`to the next.
`This structure can be understood by reference to
`FIGS. 1 and 13, in which, (by way of example) local
`processor 11 has an edge connector conductor 26.
`Local bus 21 consists of three "segments" 27A. 2'73, and
`27C, etc. These three segments are separated from each
`other by edge connector receiving slots 28A, 28B, 28C,
`and 28D. The opposed ends ofeach ofthebussegments
`27A, 27B, 27C, et.c.. each of which is composed of cor-
`responding segments of all of the conductors that con-
`stitute local bus 21, are connected to edge connector
`receiving slot conductors. FIG. 13 illustrates this struc-
`ture more clearly. In FIG. 13, reference numeral 801
`designates the mother board. Reference numerals 27A-1
`and 27A-2 designate several of the conductors of local
`bus segment 27A in FIG. 1, reference numerals 27D-2
`and 2713-2 designate several conductors of local bus
`segment 27D in FIG. 1 and reference numerals 2713-2
`and 278-2 designate several conductors of local bus
`segment 273 in FIG. 1. Reference numerals 25A-1 and
`2513-1 designate female connectors which are connected
`to local bus segment conductors 27A-2 and 2713-2. re-
`spectively. Rigid male connector conductors 26-1 and
`26-2 are attached to the front side of local procr
`board 11, and are connected to appropriate conductors
`(not shown) thereon. Male connector conductors 26-1
`
`4,622,633
`
`6
`and 26-1 extend into female connectors 25A-I and 25B-
`I, respectively, but are not short circuited together and
`do not electrically connect local bus segment conduc-
`tors 2?D-2 and 27A-2 together. Similarly, male connec-
`tor conductors 26-3 and 26-4 are not short circuitcd
`together and do not electrically connect bus conductors
`27A-1 and 27D-1 together. In contrast. however, each
`pair of male connector conductors such as 26-3 and 26-4
`on every interface board such as 12 is short-circuited
`together by a "jumper” such as 62A or 62]! in FIG. 13.
`Hence. local bus conductor 27B-2 is shorted to local bus
`conductor 273-2, and local bus conductor I'M-1 is
`shorted to local bus conductor 27B-1. Thus, inserting a
`processor board such as 11 does not extend the local bus
`20 by shorting corresponding conductors of adjacent
`local bus segments together, but
`inserting interface
`boards such as 12 into consecutively adjacent "slots"
`(i.e.. female connectors such as 25A-1 and 2513-!) of
`mother board I01 does extend the local bus to the
`needed length.
`Titus. the edge connectors of each of the interface
`boards shown in FIG. 1 includes a plurality of edge
`connectors which, in efiect, “jumper” the correspond-
`ing edge connector slot conductors together by means
`of the jumpers 62. For example. if interface board 12 is
`inserted into slot 2813, the edge connector
`con-
`ductors, designated by reference numeral 29, electri-
`cally connect the conductors of local bus segment 27A
`to corresponding ones of local bus segment 2713. Thus.
`it can be seen how continued insertion of interface cards
`12, 13. etc. into consecutively adjacent slots extends the
`length oflocal bus 21 as needed.
`The interfaces (i.e.. interface boards} such as 12, 13,
`15, etc.
`typically include memory, digital-to-analog
`converters,
`analog-to-digital
`converters.
`keyboard
`monitors. disc controllers, etc.
`Referring now to FIG. 2, system processor 18 of
`FIG. 1 includes a system bus interface circuit 43, which
`simply includes ordinary three-state buffers. some of
`which are bi-directional. Both system bus 20 and inter-
`nal bus 38 include an address bus, a data bus, and a
`control bus including one or more interrupt conductors
`and an acknowledge conductor. A microprocessor 35 is
`a connected to internal bus 38. Power on reset circuitry
`37 is connected to microprocessor 35 and. in fact, is
`connected to other circuitry in the system requiring a
`power on reset signal, as subsequently explained, by
`conductor 122 of FIGS. 5 and 6A and 6B. A DUART
`(universal asynchronous receiver-transmitter), which
`can be implemented by means of a Signetics 2681 inte-
`grated circuit, designated by reference numeral 39, is
`connected to internal bus 38. Conventional RS232 ports
`44 and 45 are connected to the A and B inputs of
`DUART 39. An RS422 interface is connected to port B
`of DUART 39. These components are readily available
`from various manufacturers. Also. a read only memory,
`interrupt circuitry ill and memory circuitry 41 are con-
`nected to internal bus 38. ROM 36 contains identifica-
`tion information and a routine which bootstraps the user
`program into memory 41 for system processor 18. Inter-
`cal bus 38 is coupled to local bus 21 (which also includes
`an address bus. a data bus, and a control bus) by means
`of local bus interface circuitry 42A, subsequently de-
`scribed with reference to FIGS. 6, GA and GB.
`The read only memory 36 can be implemented by any
`of various electrically programmable read only memo-
`ries that are readily commercially available. Micro-
`processor 35 can be implemented by means of a two-
`
`15
`
`15
`
`

`
`4,622,633
`
`7
`chip pair consisting of a 16032 and a 16201 microproces-
`sor and timing chip set manufactured by National Semi-
`conductor Corporation. A Motorola 68(1)’)
`Inicro-
`processor could also be used, although the specific pro-
`gram printouts enclosed herewith pertain to the Na-
`tional Semiconductor chip pair.
`The local bus interface 42A of system processor 18
`has the property that it makes connection only to local
`bus segments on the right hand side of its edge connec-
`tor, so it does not "extend" the local bus 24 by the rrrere
`act of plugging system processor 18 into an edge con-
`nector receiving slot of the abovt.~mentioned mother
`board.
`
`Referring now to FIG. 3. a “dedicated“ processor
`that can be used in one embodiment of the invention is
`shown, and is designated by reference numeral 85. This
`dedicated
`r is used where only one local pro-
`cemor unit is required. and there is only one local bus in
`the entire system. In this instance. no system bus 20 is
`needed, nor is the system processor 18 needed, since
`there is no inulti-processor communication. The dedi-
`cated processor unit 85 is similar to the local processor
`next described with reference to FIG. 4. except that it
`makes no connection to system bus 20 and therefore
`needs no system bus interface circuitry 35, nor does it
`require any dual port RAM 74 (FIG. 4) Instead. a mem-
`ory 91 that is similar to memory 41 of system processor
`18 is connected to internal bus 38. The DUART 88 and
`the serial communication interface device generally
`designated by 90 can be identical to those in the system
`processor 18 and local processor 11, as can local bus
`interface circuit 42. Therefore, it will be convenient to
`now thoroughly describe the bloclt diagram of local
`processor 11 with reference to FIG. 4.
`Referring now to FIG. 4, local processor 11 includes
`system bus interface circuitry 75, which includes a. plu-
`rality of suitable buffer circuits that connect the individ-
`ual conductors ofsystem bus 20 to one port of dual port
`RAM 74. Dual port RAM 74 iucluda an Intel 8206 and
`S207 chip set, which includes a dynamic RAM control-
`ler and an error correction chip. It also includes a plu-
`rality of 64K by 1 dynamic RAMs that are readily avail-
`able from Intel and others. The second port of dual port
`RAM 74 is connected to bus 71. As before. the system
`bus 20 and the internal bus '71 each include a bi-direc-
`tional data bus, an address bus, and a control bus includ-
`ing interrupt and acknowledge lines. Internal bus 11 is
`connected to microprocessor '70, an identification ROM
`1'3 which also includes a bootstrap subroutine, interrupt
`circuitry 77, and a DUART 76. Ports A and B of
`DUART '16 are connected to conventional serial I/0
`circuits, as previously described with reference to FIG.
`2. Internal bus 72 is also connected to local bus interface
`circuit 42 and includes a plurality ofjumper conductors
`62 corresponding to each conductor of each of the local
`bus segments of local bus 21. The details of local bus
`interface circuit 42 are described thoroughly with refer-
`ence to FIG. 5.
`It should be noted that the lower port of dual port
`RAM '74 has priority over the upper port, which is
`coupled to the system bus 20. because the task being
`executed by microprocessor '70 (which is identical to
`microprocessor 35 in FIG. 2) is usually a real time task
`which cannot be interrupted (for example, in a machine
`control or process control application), unless permis-
`sion for the interrupt is given by microprocessor ‘T0 of
`local processor 11.
`
`8
`Referring now to FIG. 5. the circuitry in a typical
`interface circuit, designated by reference numeral 120,
`is shown. This circuit could be any of the interface
`circuits such as 12, I3, 15, 1'! of FIG. 1. Interface board
`120 includes base address register 12!, which has its
`data inputs connected to data bus 21D, which has 16
`conductors. The ruet input R of base address register
`121 (which is implemented by means of 2?4LSl75 quad
`D type integrated circuits. has its reset input cormected
`to "power on reset" conductor 122. Power on reset
`conductor 12 can be considered to be a conductor of
`system bus 120 and goes to a logical "1" level when the
`system 10 (FIG. 1) is "
`up",
`i.e., when the
`power is turned on.
`The outputs of base address register 121 are respec-
`tively connected to one set of inputs of an 8-bit digital
`comparator, which is implemented by means of a
`7-=|LS683 integrated circuit, and also are connected to
`the inputs of a 8-bit interrupt vector butfer 124, which
`can be implented by means of any ordinary buffer
`circuits. The outputs of interrupt buffer 124 are con-
`nected to respective conductors of data bus 21D.
`A set of inputs of comparator 123 are also connected
`to the respective eight conductors of data bus 21D.
`When a "1" level is applied on conductor 125 to the
`enable input of comparator 123, and the address on
`address bus 21A matches that stored in address bus 121,
`a "I" level called BEN (board Enable) is produced on
`conductor 126; this signal enables an address decoder
`127. Address decoder 121 is implemented by a 741.8133
`3-to-8 line decoder/demultiplexer integrated circuit,
`and has as its address inputs the four most significant
`bits of addras bus 21A. The eight outputs of decoder
`127 are generally designated by reference number 128,
`some of which go to a block of circuitry daignated by
`reference numer 129. Block 129 represents the main
`functional part of interface circuit 120. and performs
`various analo9 and/or di9ital interfacing functions to
`couple peripheral devices into data network 7|}. This
`function is not per se part of the invention, and so its
`details are not set forth. One of the address decoder
`outputs 123A is connected to an enable input of identifi-
`cation ROM 130. which contains information indicating
`the type of interface circuitry block 129 contains. and
`how much memory space or 1/0 (input/output) address
`space must be allocated to interface circuit 120.
`One output 12813 of address decoder 121
`fed back
`to the clock input of base address register 121. An “ini-
`tialization” llip flop 131 has its D input connected to the
`D0 conductor 21B-0 conductor of local data bus 2113.
`This Dll conductor of local data bus 213 is also con-
`nected to the D-input of interrupt flip-flop 132. The
`cloclt input of initialization flip-flop 131 is conn