`
`In support of Counter Simulation
`
`I, Chun Lu, declare as follows:
`
`1, I am an integrated circuit (IC) designer with 12 years of industry working experience in Silicon
`
`Valley, USA. And I'm currently a Senior Design Director at Integrated Memory Logic, Limited
`(IML) in San Jose, CA, USA.
`
`2. I’ve read the book Digital Design (3rd Edition) by M. Morris Mano. And implemented the BCD
`
`Ripple Counter example shown in Figure 7-14 of the book using SPICE Simulator and Dongbu
`BDlSDX process model, please see the schematic in Figure 1 below.
`
`3, Then I run the simulation to show the timing diagram'In Figure 2 beiow, whichmatches the
`timing” diagram in Figure 7—15 in the Mano book mentioned above.
`
`4, Then with the same circuit, I expanded one of the pulses used above to keep input signal high,
`and as a result all output states remain in previous states. See Figure 3 below.
`
`5, All simulation mentioned above were performed by myself, on Samsung NP7ODZSB-501UB
`notebook computer. using SPICE Simulator, In my home at 4146 Voltaire St. San Jose, CA. USA,
`on Aprii 5, 2014.
`'
`
`6, I also summarized my opinion above in a PowerPoint file and provided to AIP Patent & Law
`'
`
`7, I can be reached at email address of chun.lu@gmai|.com
`
`I do solemnly declare and affirm that under the penalties of perjury that the contents of this
`affidavit are true to the best of my knowledge. information, and beiief. Executed this 16‘“ day of
`April 2014, in San Jose, CA, USA.
`
`
`
`
`
`Page 1
`
`Skyworks Ex. 2003
` Kinetic v. Skyworks
` Case IPR2014-00530
`
`
`
`
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`
`Figure 1. Simulation Schematic
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`
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`Page 4
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`Page 5
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