`
`(19) Japan Patent Office (JP)
`
`(12) Japanese Unexamined Utility
`Model Application Publication (U)
`
`
`
`
`
`Identification codes
`353 D
`
`JPO file numbers
`7368-5B
`
`(11) Japanese Unexamined Utility
`Model Application Publication
`Number
`H7-20636
`(43) Publication date: April 11, 1995
`Technical indications
`
`(51) Int. Cl.6
` G06F 13/00
`
`
` FI
`
`
`
`
`Request for examination: Not yet requested Number of claims: 1 OL (Total of 3 pages)
`
`Exhibit Kap No. 13
`
`
`
`
`(21) Application number
`
`(22) Date of application
`
`Japanese Utility Model
`Application H5-49607
`September 13, 1993
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(71) Applicant
`
`(72) Inventor
`
`(74) Agent
`
`000006507
`Yokogawa Electric Corporation
`9-32 Naka-cho 2-chome, Musashino-shi,
`Tokyo-to
`SAWAMOTO, Noriaki
`c/o Yokogawa Electric Corporation
`9-32 Naka-cho 2-chome, Musashino-shi,
`Tokyo-to
`Patent Attorney OZAWA, Shinsuke
`
`
`
`
`
`Reception data
`
`Latch circuit
`
`4: Interface circuit
`
`CA signal
`
`Receiver
`
`Counter
`
`44: Inverter
`
`BB signal
`
`2: Device
`
`
`
`3: Communication line
`
`apparatus
`processing
`Information
`
`
`
`
`1
`
`
`(54) (Title of the Invention) Interface circuit
`
`
`(57) (Abstract)
`(Purpose) To construct a dedicated reception device
`compatible with the RS-232C (D) standard with a
`simple hardware configuration and without software
`settings.
`(Constitution) The receiver receives reception data and
`communication
`control
`signals. When
`the
`communication control signal is off, a counter is reset
`and when it is on, the number of rising edges or falling
`edges of the reception data is counted. A latch circuit
`latches the count of the counter with the timing with
`which the communication control signal changes from
`on to off, and outputs the latched count. This output
`constitutes the reception data.
`
`
`
`
`
`
`Page 1
`
`Skyworks Ex. 2007
`Kinetic v. Skyworks
`Case IPR2014-00529
`
`

`

`
`
`
`(Scope of utility model registration claims)
`(Claim 1) An interface circuit based on the RS-232C standard,
`characterized in that it comprises:
`a receiver which receives, via a communication line, serially
`transmitted reception data and a communication control
`signal which is on when reception data is being sent to an
`interface circuit and is off when such reception data is not
`being sent;
`a counter which is reset when the communication control
`signal received by this receiver is off and which counts the
`number of rising edges or falling edges of the reception data
`when said communication control signal is on; and
`a latch circuit which latches the count of said counter with the
`timing with which the communication control signal received
`by the receiver changes from on to off, and which outputs the
`latched count,
`wherein the output of said latched circuit is taken as the
`reception data.
`
`
`
`
`(FIG. 1)
`
`2: Device
`
`(Brief description of the drawings)
`(FIG. 1) is a diagram illustrating an example of embodiment
`of the present invention.
`(FIG. 2) is a time chart of signals in the circuit of FIG. 1.
`(FIG. 3) is a drawing illustrating the correspondence
`relationship of signals in the circuit of FIG. 1.
`(FIG. 4) is a drawing illustrating an application example of an
`interface circuit pertaining to the present invention.
`(FIG. 5) is a drawing which illustrates the correspondence
`relationship of signals in the device of FIG. 4.
`(Description of references)
`1
`Information processing apparatus
`2 Device
`3 Communication line
`4
`Interface circuit
`41 Receiver
`42 Counter
`43 Latch circuit
`
`(FIG. 3)
`
`BB signal
`
`Output of latch
`circuit 43
`
`Transmission data from infor-
`mation processing apparatus 1
`
`BB signal
`
`44: Inverter
`
`Counter
`
`Receiver
`
`Information
`processing
`apparatus
`
`3: Communication
`line
`
`CA signal
`
`Latch
`circuit
`
`Reception
`data
`
`4: Interface circuit
`
`CA signal
`
`BB1 signal
`
`BB2 signal
`
`BB3 signal
`
`BB4 signal
`
`BB5 signal
`
`
`
`
`
`(FIG. 2)
`
`(FIG. 4)
`
`3: Communication line
`
`2: Device
`
`Start bit
`
`8-bit reception data
`
`Stop bit
`time
`
`Interface
`circuit
`
`Digital output
`conversion circuit
`
`Pilot lamp
`illumination
`device
`
`Pilot lamp
`illumination
`device
`
`
`
`Information
`processing
`apparatus
`
`2
`
`Page 2
`
`

`

`
`
`
`
`
`
`
`
`(FIG. 5)
`
`A1
`Extinguished
`Extinguished
`Illuminated
`Illuminated
`
`
`A2
`Extinguished
`Illuminated
`Extinguished
`Illuminated
`
`Output of interface
`circuit 4
`2
`3
`4
`5
`
`3
`
`Page 3
`
`

`

`
`(Detailed description of the invention)
`
`
`(0001)
`
`(Field of industrial application)
`
`The present invention relates to interface circuits based on the RS-232C standard
`and RS-232D standard (hereinafter, these standards will be referred to collectively as RS-
`232C (D) standard). More specifically, the invention relates to an RS-232C (D) interface
`circuit capable of receiving data with a simple configuration without communication
`parameter settings.
`
`
`(0002)
`
`(Prior art)
`
`Currently, interface circuits based on the RS-232C (D) standard are installed in
`many information processing apparatuses. When a device having an RS-232C (D)
`standard interface circuit is to be connected to an information processing apparatus
`having an RS-232C (D) standard interface circuit (here, an apparatus to be connected to
`an information processing apparatus will be referred to as a “device”), the interface
`circuit requires a dedicated LSI to perform serial/parallel conversion, a baud rate
`frequency generator, a processor unit and other hardware, and software settings such as
`data length, communication speed and the like are necessary.
`
`Therefore, even in the case of a simple dedicated reception device which receives
`several items of data from an information processing apparatus, it is necessary to provide
`hardware and perform software settings as described above.
`
`In this way, currently, RS-232C (D) standard interface circuits involve troublesome
`construction of the device both in terms of hardware and in terms of software even when
`one wishes to connect a simple device.
`
`
`(0003)
`
`(Problem to be solved by the invention)
`
`The purpose of the present invention, which was made in order to resolve the
`problem described above, is to implement an interface circuit which makes it possible to
`construct a dedicated reception device compliant with the RS-232C (D) standard with a
`simple hardware configuration and without software settings by combining a counter and
`a latch circuit.
`
`
`4
`
`Page 4
`
`

`

`
`
`
`(0004)
`
`
`(Means for solving the problem)
`
`The present invention is an interface circuit based on the RS-232C standard,
`
`characterized in that it comprises:
`
`a receiver which receives, via a communication line, serially transmitted reception
`data and a communication control signal which is on when reception data is being sent to
`an interface circuit and is off when such reception data is not being sent;
`
`a counter which is reset when the communication control signal received by this
`receiver is off and which counts the number of rising edges or falling edges of the
`reception data when said communication control signal is on; and
`
`a latch circuit which latches the count of said counter with the timing with which the
`communication control signal received by the receiver changes from on to off, and which
`outputs the latched count,
`
`wherein the output of said latched circuit is taken as the reception data.
`
`
`(0005)
`
`(Operation)
`
`In the present invention, the receiver receives reception data and communication
`control signals. A rest occurs when the communication control signal is off, and the
`number of rising edges or falling edges of the reception data is counted when the
`communication control signal is on. The latch circuit latches the count of the counter with
`the timing with which the communication control signal changes from on to off, and
`outputs the latched count. This output is taken as the reception data.
`
`
`(0006)
`
`(Examples of embodiment)
`
`The present invention will be described below using the drawings.
`
`FIG. 1 is a diagram illustrating an example of embodiment of the present invention.
`
`In FIG. 1, 1 is an information processing apparatus, and 2 is a device which
`communicates with information processing apparatus 1 via a communication line 3. In
`the example of embodiment, device 2 is a dedicated reception device which receives
`
`
`5
`
`Page 5
`
`

`

`
`
`data from information processing apparatus 1. 4 is an interface circuit of the present
`invention, which is provided inside device 2. This interface circuit 4 is compliant with the
`RS-232C (D) standard.
`
`
`(0007)
`
`In interface circuit 4, 41 is a receiver, which receives signals sent through
`communication line 3 and outputs reception data (BB signal) and a communication
`control signal (signal CA) inside interface circuit 4. The CA signal is on when
`information processing apparatus 1 is transmitting data to device 2 and is off otherwise.
`
`42 is a counter, which is reset when the CA signal is off and which counts the
`number of rising edges or falling edges of the BB signal when the CA signal is on.
`
`43 is a latch circuit, which is given the count of counter 42 and which latches the
`count given from counter 42 with the edge timing with which the CA signal changes
`from on to off. The latch circuit 43 outputs the latched count. This output is taken as the
`reception data. The latch circuit 43 updates the output each time the count is latched.
`
`44 is an inverter, which inverts the CA signal outputted by receiver 41 and provides
`it to the counter 42.
`
`
`(0008)
`
`The operation of a circuit configured in this manner will be described.
`
`FIG. 2 is a time chart illustrating an example of the signals in the circuit of FIG. 1.
`
`In this time chart, signal off corresponds to low level and signal on to high level.
`Five examples, BB1 through BB5, are presented for the BB signal. The reception data is
`8-bit data. A start bit and stop bit are added respectively before and after the reception
`data. The start bit is necessarily low level, and the stop bit is necessarily high level. The
`beginning and end of reception data are identified on the basis of these bits.
`
`
`(0009)
`
`
`
`6
`
`Page 6
`
`

`

`
`
` When the pattern of the BB signal is BB1 through BB5, the output of the latch
`circuit 43 and the transmission data from the information processing apparatus 1 are as
`shown in FIG. 3. In FIG. 3, $ represents a hexadecimal number. As shown in FIG. 3, the
`BB signal takes on various patterns depending on the transmission data from the
`information processing apparatus 1, and the output of the latch circuit 43 differs
`depending on the pattern.
`
`
`(0010)
`
`It is also possible for signal on to be high level and for signal off to be low level.
`
`
`(0011)
`
`FIG. 4 is a drawing illustrating an application example of an interface circuit of the
`present invention. In this example, the interface circuit is applied to a 2-bit digital output
`apparatus. In FIG. 4, parts which are the same as in FIG. 1 are assigned the same
`reference symbols.
`
`In FIG. 4, 5 is a digital output conversion circuit which converts the output of
`interface circuit 4 into a 2-bit digital signal, and 61 and 62 are a pilot lamp illumination
`apparatus which illuminates a pilot lamp based on a digital signal converted in digital
`output conversion circuit 5.
`
`In this application example, the output of the interface circuit 4 of the present
`invention is employed as the input of the digital output conversion circuit 5.
`
`
`(0012)
`
`FIG. 5 is a drawing which shows the correspondence relationship between the
`output of interface circuit 4 and the pilot lamp illumination state. In FIG. 5, A1 and A2 are
`pilot lamp illumination states illuminated respectively by pilot lamp illumination
`apparatuses 61 and 62.
` When the output of interface circuit 4 is 1, the previous illumination state is
`maintained.
`
`
`(0013)
`
`(Effect of the invention)
`
`According to the present invention, a dedicated reception device compliant with the
`RS-232C (D) standard can be configured by combining a counter and a latch circuit, and
`thus there is no need for a dedicated LSI to perform serial/parallel conversion, a baud rate
`frequency generator, a processor unit and other hardware of the sort required in the prior
`art. Furthermore, there is no need for software settings such as data length and
`communication speed. It is thus possible to construct a dedicated reception device
`compliant with the RS-232C (D) standard with a simple hardware configuration and
`without software settings.
`
`7
`
`Page 7
`
`

`

`
`
`The interface circuit of the present invention allows connection of any information
`
`processing apparatus having an RS-232C (D) standard interface circuit. RS-232C (D)
`standard interface circuits are widely used, and thus the interface circuit of the present
`invention allows connection to many information processing apparatuses.
`
`
`
`8
`
`Page 8
`
`

`

`f6
`
`TRANSPERFECT
`
`City of New York, State of New York, County of New York
`
`to the best of my
`I, Mamiko Taniguchi, hereby certify that the following is,
`knowledge and belief, a true and accurate translation of the document, “Japanese
`Pat. App. H07-20636,” from Japanese into English.
`
`
`
`1 o Taniguchiz'
`
`/
`
`Sworn to before me this
`
`Friday, April 18, 2014
`
`Signature,
`
`otary Public
`
`
`
`
`
`
`
`RYAN ALEXANDER DROST
`t r Public -Stata of New York
`N° 3 yNo. 01DR6262048
`Qualified in NEW YORK County
`My Commission Expires MAY 21, 2016
`
`
`
`
`
`
`
`Stamp, Notary Public
`State of New York
`
`Page 9
`
`