USOO7921320B2
`
`(12) United States Patent
`US 7,921,320 B2
`(10) Patent N0.:
`
`D’Angelo et al. Apr. 5, 2011 (45) Date of Patent:
`
`
`(54) SINGLE WIRE SERIAL INTERFACE
`
`(56)
`
`References Cited
`
`(75)
`
`Inventors: Kevin P. D’Angelo, Santa Clara, CA
`(US); David Alan Brown, Los Gatos,
`CA (US); John Sung K. So, Freemont,
`CA (US); Jan Nilsson, Sunnyvale, CA
`(US); Richard K Williams, Cupertino,
`CA (US)
`
`(73) Assignee: Advanced Analogic Technologies, Inc.,
`Sunnyvale, CA (US)
`
`U.S. PATENT DOCUMENTS
`
`231,087 A
`447,918 A
`540,168 A
`597,062 A
`1,231,013 A
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`2,149,343 A
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`
`(Continued)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 31 days.
`
`CN
`
`FOREIGN PATENT DOCUMENTS
`1639672 A
`7/2005
`
`(21)
`
`Appl. N0.: 11/582,927
`
`(22)
`
`Filed:
`
`Oct. 17, 2006
`
`(65)
`
`Prior Publication Data
`
`US 2007/0038879 A1
`
`Feb. 15, 2007
`
`Related U.S. Application Data
`
`(63)
`
`(60)
`
`(51)
`
`(52)
`
`(58)
`
`Continuation of application No. 10/144,333, filed on
`May 13, 2002, now Pat. No. 7,127,631.
`
`Provisional application No. 60/368,474, filed on Mar.
`28, 2002.
`
`Int. Cl.
`G06F 1/04
`G06F 1/00
`
`(2006.01)
`(2006.01)
`(2006.01)
`G06M 3/00
`(2006.01)
`H03K 21/00
`U.S. Cl.
`............ 713/502; 713/500; 713/600; 377/1;
`377/27
`
`Field of Classification Search .................. 713/500,
`713/502, 600
`See application file for complete search history.
`
`(Continued)
`OTHER PUBLICATIONS
`
`Ullah, Zafar, “SX Reset Considerations”, UBICOM, Nov. 2000*
`
`(Continued)
`
`Primary Examiner 7 Ji H Bae
`(74) Attorney, Agent, or Firm 7 DLA Piper LLP (US)
`
`ABSTRACT
`(57)
`A single wire serial interface for power ICs and other devices
`is provided. To use the interface, a device is configured to
`include an EN/SET input pin. A counter within the device
`counts clock pulses sent to the EN/SET input pin. The output
`of the counter is passed to a ROM or other decoder circuit.
`The ROM selects an operational state for the device that
`corresponds to the value of the counter. In this way, control
`states may be selected for the device by sending correspond-
`ing clock pulses to the EN/SET pin. Holding the EN/SET pin
`high causes the device to maintain its operational state. Hold-
`ing the EN/SET pin low for a predetermined timeout period
`resets the counter and causes the device to adopt a predeter-
`mined configuration (such as off) until new clock pulses are
`received at the EN/SET pin.
`
`47 Claims, 4 Drawing Sheets
`
`206
`
`EN/SET
`
`Kinetic Technologies,
`
`Inc.
`
`Exhibit 1001
`
`Page 1
`
`

`

`US 7,921,320 B2
`
`Page 2
`
`U.S. PATENT DOCUMENTS
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`
`CN
`EP
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`JP
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`KR
`KR
`W0
`
`Office Action in Inter Partes Reexamination U.S. Appl. No.
`95/000,501, to USP 7,127,631, parent of current application.
`“SX Reset Considerations,” Application Note 18, Zafar Ullah,
`Ubicom, Inc., Mountain View, CA, marked Nov. 2000.
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`McGraw Hill, New York, 1997, pp. 7-12.
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`Logic, Inc., Austin, Texas, marked 2000, pp. 1-25.
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`ter (Preliminary),” Samsung Electronics, Korea, marked Dec. 7,
`2001, pp. 10-1 through 10-10.
`“Using a UART to Implement a l-Wire Bus Master,” Application
`Note 214, Maxim Integrated Products, Sunnyvale, CA, marked Sep.
`10, 2002, pp. 1-10.
`“Using an API to Control the DS 1WM 1-Wire® Bus Master,” Appli—
`cation Note 120, Maxim Integrated Products, Sunnyvale, CA,
`marked Mar. 8, 2002, pp. 1-8.
`“Interfacing the Maxim l-Wire Master (DS 1WM) to an ARM7 Pro-
`cessor,” Application Note 145, Maxim Integrated Products, Sunny-
`vale, CA, marked Jul. 5, 2001, pp. 1-3.
`Web page relating to “Book of iButton® Standards,” Application
`Note 93 7, Maxim Integrated Products, Sunnyvale, CA, marked Jan.
`16, 2002, pp. 1-2.
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`10/447,764.
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`10/447,764.
`Examiner-Initiated Interview Summary Record dated Feb. 1, 2006
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`Notice of Allowance and Notice of Allowability dated Mar. 9, 2006
`for US. Appl. No. 10/447,764.
`Non-final Office Action mailed Jan. 10, 2005.
`Response to Non-final Office Action mailed Jan. 10, 2005.
`Final Office Action mailed May 26, 2005.
`Response to Final Office Action mailed May 26, 2005.
`Advisory Action mailed Aug. 26, 2005.
`Amendment and Response filed Oct. 25, 2005.
`Non-final Office Action mailed Dec. 27, 2005.
`Response to Non-final Office Action mailed Dec. 27, 2005.
`Notice ofAllowance mailed Jun. 9, 2006.
`Request for Inter Partes Reexamination, filed Oct. 3, 2009.
`Order Granting Request for Inter Partes Reexamination, mailed Dec.
`29, 2009.
`Notice of Prior or Concurrent Proceedings, filed Mar. 9, 2010.
`PCT/USZOO3/009636, International Search Report, mailed Sep. 30,
`2003.
`Korean Patent Application No. 10-2004-7013451, Korean Intellec-
`tual Property Office Notice of Preliminary Rejection, mailed Oct. 30,
`2009 (Korean Language).
`Korean Patent Application No. 10-2004-7013451, Korean Intellec-
`tual Property Office Notice of Preliminary Rejection, mailed Oct. 30,
`2009 (English Language Translation).
`Korean Patent Application No. 10-2004-7013451, English Transla-
`tion of Claims Pending, dated Dec. 4, 2009.
`Complaint for Patent Infringement, filed by Advanced Analogic
`Technologies, Inc. on Mar. 27, 2009, Without exhibits.
`First Amended Complaint for Patent Infringement, filed by Advanced
`Analogic Technologies, Inc. on Jul. 24, 2009, Without exhibits.
`Answer and Counterclaims to First Amended Complaint, filed by
`Kinetic Technologies, Inc. on Aug. 7, 2009.
`
`Page 2
`
`

`

`US 7,921,320 B2
`Page 3
`
`AATI’s Response to Kinetic Technologies, Inc.’s Answer and Coun-
`terclaims to First Amended Complaint, filed by Advanced Analogic
`Technologies, Inc. on Aug. 26, 2009.
`Advanced Analogic Technologies, Inc.’s Notice of Initial Disclosure
`Pursuant To Fed.R.CiV.P. 26(a)(l), served Jun. 5, 2009.
`Defendant Kinetic Technologies, Inc.’s Rule 26(A) Initial Disclo-
`sures, served Jul. 21, 2009.
`AATI’s Disclosure Of Asserted Claims And Preliminary Infringe-
`ment Contentions (Patent L.R. 3-1) And Accompanying Document
`Production (L.R. 3-2) (including infringement contention charts
`attached as Exhibits 1-10), served Aug. 18, 2009. Certain portions of
`this document were designated confidential pursuant to protective
`order.
`Defendant Kinetic Technologies, Inc.’s Invalidity Contentions Pur-
`suant To Patent L.R. 3-3, served Oct. 5, 2009.
`Advanced Analogic Technologies, Inc.’s Preliminary Claim Con-
`structions and Extrinsic Evidence Pursuant to L.R. 4-2, served Nov.
`2, 2009.
`
`Defendant Kinetic Technologies, Inc.’s Exchange of Preliminary
`Claim Construction Pursuant to Patent L.R. 4-2, served Nov. 2, 2009.
`Joint Claim Construction and Prehearing Statement Pursuant to
`Patent L.R. 4-3 (including attached Exhibits A-C), filed Nov. 30,
`2009.
`
`Complaint for Misappropriation of Trade Secrets, filed Sep. 5, 2008.
`Advanced Analogic Technologies, Inc.’s Statement of Claims, dated
`Feb. 20, 2009.
`Claim of Kin Shum and Kinetic Technologies, Inc., dated Feb. 20,
`2009.
`
`Order Granting Petition to Compel Arbitration, dated Feb. 10, 2009.
`Arbitrator’s Order on Disputed Discovery Issues, dated Mar. 25,
`2009.
`
`Notice of Entry of Order and Judgment, dated Feb. 2, 2010.
`
`* cited by examiner
`
`Page 3
`
`

`

`US. Patent
`
`Apr. 5, 2011
`
`Sheet 1 014
`
`US 7,921,320 132
`
`I
`
`1
`
`I
`
`I
`
`I
`
`I
`
`2
`
`I
`
`3
`
`I
`
`I
`
`4
`
`I
`
`I
`
`n-1
`
`I
`
`n
`
`Fig. 1
`
`I
`
`EN/SE—T
`
`o
`
`Opififgm'
`
`206
`
`ENISET
`
`Page 4
`
`

`

`US. Patent
`
`Apr. 5, 2011
`
`Sheet 2 014
`
`US 7,921,320 132
`
`Fig. 3
`
`'ljmeoqt
`:
`
`J— —_——fl——L_ Enable
`
`1
`
`2
`
`3
`
`4
`
`n-1
`
`n
`
`0
`
`Counter
`
`Clock
`
`_ Enable
`
`Page 5
`
`

`

`US. Patent
`
`Apr. 5, 2011
`
`Sheet 3 014
`
`US 7,921,320 B2
`
`206
`
`EN/SET
`
`Latch
`Timeout
`Tlmeoul
`'H'
`i<—+‘:
`S
`i
`x
`g
`m m :I
`3
`——-—3—¥
`i
`
`Fig. 6
`
`———1
`
`z
`:
`I
`
`EN/SET
`
`Enable
`
`Clock
`
`W T I 1““;
`
`1
`
`2
`
`3
`
`4
`
`n-1
`
`n
`
`0
`
`Counter
`
`__________————r——L-— Latch
`Control
`————————-——S—— Word
`0
`n
`0
`
`Page 6
`
`

`

`US. Patent
`
`Apr. 5, 2011
`
`Sheet 4 014
`
`US 7,921,320 132
`
`Fig. 7
`
` ENIS ET
`
`mm '
`
`Page 7
`
`

`

`1
`SINGLE WIRE SERIAL INTERFACE
`
`RELATED APPLICATIONS
`
`US 7,921,320 B2
`
`2
`
`This application is a continuation of Application Ser. No.
`10/144,333 filed May 13, 2002, now US. Pat. No. 7,127,631,
`which claims the benefit of a US. Provisional Patent Appli-
`cation Ser. No. 60/368,474 entitled “Single Wire Serial Inter-
`face: filed Mar. 28, 2002, which are incorporated in this 1 0
`document by reference.
`
`5
`
`TECHNICAL FIELD OF THE INVENTION
`
`The present invention relates generally to control inter-
`faces for integrated circuits and other devices. More particu-
`larly, the present invention includes a single wire serial inter-
`face that may be used to control power ICs and other devices.
`
`BACKGROUND OF THE INVENTION
`
`15
`
`20
`
`35
`
`In power IC applications, an interface generally serves to
`manage functions such as power level, or on and off switch-
`ing. In the load switch power IC case, the IC either delivers
`power to a subsystem or not depending on the state of the 25
`on/off pin. In a more complex power supply controller, the
`regulated output voltage is set by a more complex interface
`such as an integrated 5-pin digital to analog interface. When
`many sub systems exist within the same system, an even more
`complex interface, such as the SMBUS interface may be 30
`implemented.
`The complex power IC can easily afford a multi-pin control
`interface, since it is already in a large package, and has suf-
`ficient functional density. The stand-alone power manage-
`ment function cannot normally offer a complex control inter-
`face due to die size or package size constraints. Still there are
`cases where this type of control is desirable. For instance, it
`may be desirable to vary a current limit over different load
`scenarios. However, few pins are available for control of the
`simple load switch because most of the pins are used by the
`power function, and there is no board space or budget for a
`larger package. Some functionality can be added by means of
`an analog interface, but since most applications are controlled
`by a microprocessor, a digital interface is easiest to imple- 45
`ment and most cost effective. A serial interface is efficient, but
`common simple serial interfaces such as 3-wire or 2-wire
`require too many pins. Complex serial interfaces such as
`SMBUS are generally too complex and expensive to merit
`implementation for the stand-alone power management func- 50
`tion.
`For these reasons and others, there is a need for an interface
`that may be used to control stand-alone power and other IC
`types. Ideally, this interface would be able to accommodate a
`wide variety of control needs and be scaleable to many levels 55
`of complexity. Minimal pin use is also desirable, with the
`ideal being use of a single pin that may optionally be shared
`with another function.
`
`40
`
`referred to as the EN/SET pin. The sensing circuit determines
`whether or not the voltage at the EN/SET pin is high, low, or
`toggling.
`When the voltage at the EN/SET pin is toggling the counter
`is enabled. This causes the counter to count the rising edge of
`each clock pulse sent to the EN/SET pin. Holding the voltage
`at the EN/SET pin high causes the counter to stop counting
`and maintain its value. Holding the voltage at the EN/SET pin
`low for more than a preset timeout period causes the counter
`to reset to zero.
`The ROM contains a total of 2" words ofm bits. Each m-bit
`
`word corresponds to one control state for the IC. The output of
`the counter is an address within the ROM selecting a particu-
`lar m-bit word and control state. For simple functions, the
`counter can be only a few bits, in which case the counter
`outputs can be directly decoded in logic without the complex-
`ity of a ROM.
`Another aspect of the present invention is an LED current
`source IC incorporating the single wire serial interface. The
`LED current source includes at least one current output and
`one EN/SET input. For a representative implementation, the
`ROM includes a total of thirty-two (32) words. Each word
`corresponds to an output level for the one or more current
`outputs. The output levels -a-re preferably configured as a
`logarithmic scale, yielding two decades of output levels and
`LED luminosity.
`Another aspect of the present invention is a load switch IC
`incorporating the single wire serial interface. The load switch
`includes one EN/SET input and n outputs where n is greater
`than one. For the case ofthe load switch, the bits in the counter
`may be used to directly control the state of the individual
`outputs (i.e., each bit determines the state of a corresponding
`output). This allows the ROM to be omitted from the load
`switch IC, simplifying its design. The bits in the counter yield
`a total of 2" different output configurations (i.e., all possible
`configurations).
`Another aspect of the present invention is a current limited
`load switch IC incorporating the single wire serial interface.
`The current limited load switch includes one or more outputs
`and one EN/SET input. Each word in the ROM corresponds to
`a different current limit for the outputs.
`Other aspects and advantages of the present invention will
`become apparent from the following descriptions and accom-
`panying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`For a more complete understanding of the present inven-
`tion and for further features and advantages, reference is now
`made to the following description taken in conjunction with
`the accompanying drawings, in which:
`FIG. 1 is a timing diagram illustrating the use of the single
`wire protocol according to one aspect of the present inven-
`tion.
`
`FIG. 2 is a block diagram showing an IC using a single wire
`serial interface according to one aspect of the present inven-
`tion.
`
`SUMMARY OF THE INVENTION
`
`FIG. 3 is a timing diagram illustrating the use of the single
`wire serial interface of the IC of FIG. 2.
`
`60
`
`An aspect of the present invention provides a single wire
`serial interface that may be used to control stand-alone power
`ICs and other devices. For this aspect, an IC is configured to
`include a sensing circuit, a counter, and a ROM or similar 65
`decoder. The sensing circuit monitors the voltage present at
`one of the IC pins. Typically, this will be the on/off pin and is
`
`FIG. 4 is a diagram showing a sensing circuit appropriate
`for use in the IC of FIG. 2.
`
`FIG. 5 is a block diagram showing an IC using a latched
`implementation of single wire serial interface according to
`one aspect of the present invention.
`FIG. 6 is a timing diagram illustrating the use of the single
`wire serial interface of the IC of FIG. 5.
`
`Page 8
`
`

`

`US 7,921,320 B2
`
`3
`FIG. 7 is a diagram showing a latch driver circuit appro-
`priate for use in the IC of FIG. 2.
`
`DETAILED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The preferred embodiments of the present invention and
`their advantages are best understood by referring to FIGS. 1
`through 7 ofthe drawings. Like numerals are used for like and
`corresponding parts of the various drawings.
`Single Wire Serial Protocol
`An aspect of the present invention provides a single wire
`serial protocol that may be used to control ICs and other
`compatible devices. To use the single wire serial protocol, a
`device must support a series of different operational states or
`modes. For one example, a stand-alone power IC might be
`configured to support a range of different output levels. Typi-
`cally, these output levels would progress in even increments
`from a no-power or off condition to a full power condition.
`Each different output level would define a particular opera-
`tional state. The single wire serial protocol allows the opera-
`tional states of compatible devices to be dynamically con-
`trolled. Thus, for the stand-alone power IC example, the
`single wire serial protocol would be used to select different
`operational states and associated output power levels.
`Devices that support the single wire serial protocol are
`configured to receive an EN/SET signal. As shown by the
`timing diagram of FIG. 1, the EN/SET signal may be charac-
`terized as having three different waveforms. The first ofthese
`is a toggling waveform where the EN/SET signal is composed
`of a series of clock pulses. The second waveform is where the
`EN/SET signal is asserted to have a constant high value. The
`third waveform is where the EN/SET signal is asserted to
`have a constant low value.
`
`The toggling waveform causes compatible devices to
`select particular operational states. The total number of clock
`pulses (or rising edges) determines the particular operational
`state that will be selected (i.e., four clock pulses selects the
`fourth operational state and so on. Additional clock pulses
`that exceed the number of operational states supported by a
`compatible device will generally cause the count to rollover
`and start again with the first operational state.
`The constant high waveform causes compatible devices to
`maintain their previously selected operational states. As
`shown in FIG. 1, the current operational state may be contin-
`ued for an arbitrary duration in this way.
`The constant low waveform causes compatible devices to
`power off (or otherwise adopt a predefined configuration)
`after a pre-defined timeout period has elapsed. The timeout
`period allows compatible devices to distinguish between the
`constant low waveform and the shorter low portions of the
`toggling waveform. For a typical implementation, the timeout
`value is 400 us with the EN/SET signal having a frequency in
`the range of l Mhz to 10 kHz. Higher and lower frequencies
`are also possible.
`Single Wire Serial Interface
`To use the single wire serial protocol, compatible devices
`must provide a single wire serial interface. For the purposes of
`illustration, FIG. 2 shows a block diagram of an IC (generally
`designated 200) configured to provide this interface. IC 200
`includes one or more inputs 202 and one or more outputs 204.
`IC 200 also includes an EN/SET input 206 and a core portion
`208. Core portion 208 is intended to be generally representa-
`tive of the circuits that function to create outputs 204 using
`inputs 202EN/SET input 206 is connected to a sensing circuit
`210. Sensing circuit 210 monitors the EN/SET signal at
`EN/SET input 206 and determines ifthat voltage is constantly
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`high, constantly low, or toggling. Based on this determina-
`tion, sensing circuit 210 produces two signals: a Clock signal
`and an Enable signal. The Clock and Enable signals control
`the operation of a counter 212 having 11 bits. Counter 212
`counts the rising transitions of the Clock signal whenever
`sensing circuit 210 asserts the Enable signal. Counter 212
`resets whenever the Enable signal is not asserted.
`The relationship between the EN/SET signal and the Clock
`and Enable signals is shown in more detail in the timing
`diagram of FIG. 3. As shown in that figure, a rising transition
`of the EN/SET signal causes sensing circuit 210 to assert the
`Enable signal. Sensing circuit 210 holds the Enable signal
`high until the EN/SET signal transitions to a logical low state
`and remains in the low state until the predetermined timeout
`period has elapsed. The Enable signal acts to gate the Clock
`signal. As long as the Enable signal remains high, sensing
`circuit 210 forwards the EN/SET signal as the Clock signal.
`Counter 212 receives both the Clock and Enable signal. The
`first rising transition of the EN/SET signal raises the Enable
`signal and causes the EN/SET signal to be forwarded as the
`Clock signal. Counter 212 responds by increasing its value to
`one. Subsequent rising transitions causes Counter 212 to
`increment its value to two, three and so on. Counter 212 resets
`to zero when sensing circuit 210 transitions the Enable signal
`to a low value.
`
`The 11 output bits of counter 212 control a ROM 214. ROM
`214 has a total of 2" words, each having m bits. Each m-bit
`word corresponds to one control state for IC 200. The n-bit
`output of counter 212 selects a particular m-bit word within
`ROM 214. The selected control state and Enable signal are
`passed to core portion 208. Core portion 208 is configured to
`adjust its operation to match the selected control state.
`Sensing Circuit
`FIG. 4 shows a representative implementation for sensing
`circuit 210. As shown in that figure, sensing circuit 210 pro-
`duces the Enable and Clock signals by timing the logic low
`period of the EN/SET signal. As long as the timeout period is
`not exceeded, the Enable signal will remain high, and the
`EN/SET signal will feed through logic gate AND1 to become
`the Clock signal. In the described implementation, the timer
`consists of capacitor C1 and current source I1. Transistors
`MN2 and MN3 mirror current source I1. This linearly dis-
`charges capacitor C1 when the EN/SET signal is a logical
`low, and transistor MP1 is off. If the EN/SET signal remains
`in a logic low state long enough, capacitor C1 will discharge
`to a voltage that is less than the threshold of transistor MN1
`and turn MN1 off. When MN1 is off, R1 pulls node “2” to the
`threshold of Schmit trigger ST1 and the Enable signal goes to
`a logic low state. As long as the EN/SET signal remains low
`for a period less than the timeout period, the Enable signal
`will remain in a logic high state. The timeout period is domi-
`nated by the power supply voltage, the threshold of transistor
`MN1 (Vmm), the value of capacitor C1, and the magnitude of
`current source I1, given by:
`
`Timeout:C* (Vcc— Vm1)/11
`
`Typical values of C1:10 pF, Vcc:5 v, VtMNl:l v and I1
`:01 uA yield a timeout period of 400 us. Sensing circuit 210
`can respond to a 400 ns signal of the EN/SET signal. As a
`result, it is able to differentiate between the EN/SET signal as
`Clock and EN/SET signal as Enable. A typical application
`can be designed around a range of EN/SET frequencies
`between 1 Mhz to 10 kHz, or slower if desired.
`Latched Single Wire Serial Interface
`Devices that implement thejust described single wire serial
`interface select a new control state each time a rising edge of
`a clock pulse is received. One result is that compatible devices
`
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`US 7,921,320 B2
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`5
`progressively select each control state in sequence until the
`desired control state is reached. So, selecting the eighth con-
`trol state means that compatible devices will progressively
`select control states one through seven before finally selecting
`the eighth (desired) control state. For some devices this
`behavior is acceptable or even desirable. This can be true, for
`example where the device is a current source where progres-
`sively increasing output can be benign or even useful. In other
`cases, selection of intermediate control states may have
`unwanted side effects. This could be true for the case of the
`
`multiple load switch that is described below.
`FIG. 5 shows a block diagram of an IC (generally desig-
`nated 500) that uses an implementation of the single wire
`serial interface that eliminates intermediate control states. IC
`
`the majority of components previously
`500 includes
`described for FIG. 2 and IC 200. In this case, the output of
`counter 212 is passed through a latch 502 before reaching
`ROM 214. Latch 502 is controlled by a Latch signal generated
`by a latch driver circuit 504.
`The relationship between the EN/SET, Clock, Enable and
`Latch signals is shown in FIG. 6. As shown, the Latch signal
`remains low until the EN/SET signal has been maintained in
`a high state for a duration that exceeds a predetermined latch
`timeout period. Holding the EN/SET signal high for longer
`than the latch timeout period causes latch driver 504 to assert
`the Latch signal. This, in turn causes latch 502 to forward the
`accumulated value of counter 212 to ROM 214. The result is
`
`that counter 212 is prevented from forwarding intermediate
`control states until the EN/SET signal has been asserted high
`after the train of clock pulses has been completed.
`Latch Driver Circuit
`
`FIG. 7 shows a representative implementation for latch
`driver 504. As shown in that figure, latch driver 504 produces
`the Latch signal by timing the logic high period of the
`EN/SET signal. As long as the EN/SET signal is high for less
`than the latch timeout period, the Latch signal remains low. In
`the described implementation, the timer consists of capacitor
`C1 and current source 11. Transistors MN2 and MN3 mirror
`
`current source 11. This linearly discharges capacitor C1 when
`the EN/SET signal is a logical high, and transistor MP1 is off
`If the EN/SET signal remains in a logic high state long
`enough, capacitor C1 will discharge to a voltage that is less
`than the threshold oftransistor MN1 and turn MN1 off. When
`
`MN1 is off, R1 pulls node “2” to the threshold of Schmit
`trigger ST1 and the Latch signal goes to a logic high state. As
`long as the EN/SET signal remains high for a period less than
`the latch timeout period, the Latch signal will remain in a
`logic low state. The latch timeout period is dominated by the
`power supply voltage,
`the threshold of transistor MN1
`(VtMM), the value of capacitor C1, and the magnitude of
`current source 11, given by:
`
`Latch Timeout:C* (Vcc— VlMNl)/11
`
`Typical values of C1:10 pF, Vcc:5 v, VtMN1:1 v and 11
`:01 uA yield a latch timeout period of 400 us. Latch driver
`504 can respond to a 400 ns signal ofthe EN/SET signal. As
`a result, it is able to differentiate between the EN/SET signal
`as Clock and EN/SET signal as Latch. A typical application
`can be designed around a range of EN/SET frequencies
`between 1 Mhz to 10 kHz; or slower if desired.
`Decoder
`
`ROM 214 provides a mapping between the EN/SET signal
`and associated control states for IC 200. In some cases, there
`may be relatively few control states. In other cases, the map-
`ping may be defined functionally. In these cases, it is possible
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`to replace ROM 214 with a decoder. This allows the outputs of
`counter 212 to be directly decoded in logic without the com-
`plexity of a ROM.
`LED Driver
`
`The white LED has become the backlight source of choice
`for small displays, used in products such as cell phones that
`typically use a lithium ion battery for power. The white LED
`is an excellent light source. However, it requires from 3.6 to
`4.1 volts of forward bias voltage to conduct current and emit
`light. Since the lithium ion battery runs between 4.1 and 2.9
`volts, a regulated boosted voltage must be generated to power
`the LED. Four LED’s are typically used in a display; either in
`a serial or a parallel arrangement.
`The lowest cost solution is to drive the four LED’s in
`
`parallel with a charge pump. The higher cost solution is to
`drive the four LED’s in series with a DC/DC boost converter
`
`capable ofboosting the lithium ion battery up to four times the
`forward voltage of the LEDs (e.g. 4><4.1:16.4 volts). The
`DC/DC boost converter is higher cost due to the cost and size
`of the required inductor, but since the LED is really a current
`mode device, the performance is better because all of the
`LED’s in series will be biased with the same current and share
`
`the same luminosity.
`The charge pump solution is attractive because small low
`cost capacitors can be used to develop a voltage ofup to 1.5 or
`2 times the battery voltage. The disadvantage to the charge
`pump solution is that the resulting voltage must be sensed as
`a current for brightness control of the LED. A single voltage
`can drive multiple LED’s, however only one LED is used as
`the current reference. This is achieved by adding a current
`setting and sensing resistor in series with it. The additional
`LED’s have a matching resistor in series, but unless their
`forward voltages match that of the reference LED, they will
`have substantially different currents and, as such, brightness
`levels. A better solution would have parallel current outputs
`for driving the LED with a current. In this manner, all LED’ s
`would have the same bias current and luminosity. The parallel
`outputs however, require more pins and a larger package that
`is a significant disadvantage.
`Another issue is brightness control. Brightness control can
`be performed by setting a reference current and leaving it
`constant, or by applying some control means to the DC/DC
`converter to obtain a different output voltage or current. One
`way to control the brightness of an LED is to simply turn it on
`and off at a higher frequency than the human eye can detect,
`and pulse width modulate (PWM) the on-time. An easier
`system solution would be an interface whereby a current
`control is input to the DC/DC converter to control the output
`current. This can be accomplished either by a control voltage
`or a digital interface. A simple solution is a digital interface,
`but to have enough resolution, or a large enough range, many
`bits of control are required. This leads again to higher unde-
`sirable pin count.
`Since the human eye senses brightness logarithmically, a
`useful digital control would result in a logarithmic brightness
`scale. A logarithmic scale that adequately covers two decades
`of luminosity requires at least 5-bits or 32 levels.
`An aspect of the present invention provides an LED driver
`that effectively meets all of these requirements. The LED
`driver is preferably configured as a 12-pin device with four
`LED current source outputs. The LED driver also includes an
`EN/SET input that supports the singl