`
`COMPREHENSIVE
`
`DICTIONARY
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`
`
`EEEcEiiNAE
`» ENEINEEEINE
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`'
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`EDI-TDFl-lN-Cl-IIEF
`
`Phillip A. Laplante
`
`A CRC Handbook Published in Cooperation with IEEE Press
`
`REMBRANDT EXHIBIT 2010
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`REMBRANDT EXHIBIT 2010
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`

`

`Acquiring Editor: Ron Powers
`Production Manager: Suzanne Lassandro
`Project Editor: Susan Fox
`Cover Design: Jonathan Pennell
`
`Library of Congress Cataloging-in-Publication Data
`
`Comprehensive dictionary of electrical engineering I Phillip Laplante, editor-in-chief.
`p. em.
`Includes bibliographical references (p. ).
`ISBN 0-8493-3128-5 (alk. paper)
`ISBN 3-540-64835-6
`l. Electric engineering - Dictionaries. I. Laplante, Phillip A.
`TK9.C575 1999
`621.3'03-dc21
`
`98-44776
`CIP
`
`This book contains information obtained fromaulhentic and highly regarded sources. Reprinted material is quoted
`with permission, and source.~ arc indicated. A wide variety of references are listed. Reasonable efforts have been made
`to publish reliable data and infoi1Illltion, but the author und the publisher cannot assume responsibility for the validity
`of all materials or for the consequences of their use.
`Neither this book nor any purt may be reproduced or transmitted in any form or by auy means, electronic or
`mechanical, including photocopying, microfilming, and recording, or by any information storage or retrieval system,
`without prior permission in writing from the publisher.
`All rights reserved. Authorization to photocopy items for internal or personal use, or the personal or internal use
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`Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923 USA. The fee code for users of the
`Transactional Reporting Service is ISBN 0-8493-3128-5/99/$0.00+$.50. The fee is subject to change without notice.
`For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been
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`CRC Press LLC's consent does not extend to copying for general distribution, for promotion, for creating new
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`Trademark Notice: Product or cororate names may be trademarks or registered trademarks, and are used only for
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`
`© 1999 by CRC Press LLC
`
`No claim to original U.S. Government works
`International Standard Book Number 0-8493-3128-5
`Library of Congress Card Number 98-44776
`Printed in the United States of America 1 2 3 4 5 6 7 8 9 0
`Printed on acid-free paper
`
`REMBRANDT EXHIBIT 2010
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`

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`set, and disallow the others in the set, from being
`active or valid. For example, masking an inter(cid:173)
`rupt.
`(2) for semiconductor manufacturing, a de(cid:173)
`vice used to selectively block photolithographic
`exposure of sensitized coating used for prevent(cid:173)
`ing a subsequent etching process from removing
`materi.al. A mask is analogous to a negative in
`conventional photography.
`(3) a glass or quartz plate containing infor(cid:173)
`mation (encoded as a variation in transmittance
`and/or phase) about the features to be printed.
`Also called a photomask or a reticle.
`
`mask aligner
`a tool that aligns a photomask to
`a resist-coated wafer and then exposes the pattern
`of the photomask into the resist.
`
`mask biasing
`the process of changing the size
`or shape of the mask feature in order for the
`printed feature size to more closely match the
`nominal or desired feature size.
`
`mask blank
`a blank mask substrate (e.g.,
`quartz) coated with an absorber (e.g., chrome),
`and sometimes with resist, and used to make a
`mask.
`
`mask linearity
`the relationship of printed re(cid:173)
`sist feature width to mask feature width for a
`given process.
`
`mask programming
`programming a semi(cid:173)
`conductor read-only-memory (ROM) by modi(cid:173)
`fying one or more of the masks used in the semi(cid:173)
`conductor manufacturing process.
`
`mask set
`consists of the dozen or so (varies
`with process and company) individual masks that
`are required to complete a MMIC wafer fabrica(cid:173)
`tion from start to finish. Examples of masks or
`mask levels are "first level metal" (defines all the
`primary metal structure on the circuit), "capacitor
`top plate" (defines the pattern for the metal used
`to form the top plate of MIM capacitors), and
`
`master copy
`
`"dielectric etch" (defines areas where dielectric
`(insulator) material will be removed after coating
`the entire wafer with it).
`
`maskable interrupt
`interrupt that can be post(cid:173)
`poned to permit a higher-priority interrupt by set(cid:173)
`ting mask bits in a control register. See also non(cid:173)
`maskable interrupt.
`
`mass storage
`data.
`
`a storage for large amounts of
`
`massively parallel architecture
`a computer
`system architecture characterized by the pres(cid:173)
`ence of large numbers of CPUs that can execute
`instructions in parallel. The largest examples can
`process thousands of instructions in parallel, and
`provide efficient pathways· to pass data from one
`CPU to another.
`
`massively parallel processor
`a system that
`employs a large number, typically 1000 or more,
`of processors operating in parallel.
`
`master
`the system component responsible for
`controlling a number of others (called slaves).
`
`master boot record
`a record of the disk con(cid:173)
`taining the first code and table that are loaded
`at the bootstrap of the computer. It is read even
`before the partition table sector.
`
`master control relay (MCR)
`in
`used
`programmable logic controllers to secure entire
`programs, or just certain rungs of a program. An
`MCR will override any timer condition, whether
`it be time-on or time-off, and place all contacts
`in the program to a safe position whenever con(cid:173)
`ditions warrant.
`
`master copy
`in coherence protocols, the copy
`of the object that is guaranteed to hold the "cor(cid:173)
`rect'' contents for the object. Coherence proto(cid:173)
`cols can be designed around the tagging of master
`copies. The master copy can be read (rather then
`
`397
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`REMBRANDT EXHIBIT 2010
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