(12) United States Patent
`Yoon et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,740,585 B2
`May 25, 2004
`
`US006740585B2
`
`m)mmmmmmMnmNmmGMwm
`SPUTTER DEPOSITION METHOD WITH
`PVD, CVD, OR ALD
`
`(75)
`
`Inventors: Ki Hwan Yoon, Sunnyvale, CA (US);
`Yonghwa Chris Cha, San Jose, CA
`(US); Sang Ho Yu, Sunnyvale, CA
`(US); Hafiz Farooq Ahmad, Newark,
`CA (US); Ho Sun Wee, Santa Clara,
`CA (US)
`
`(73) Assignee: Applied Materials, Inc., Santa Clara,
`CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`
`(22)
`
`(65)
`
`(63)
`
`(51)
`(52)
`(58)
`
`(56)
`
`Appl. No.:
`Filed:
`
`10/044,412
`
`Jan. 9, 2002
`Prior Publication Data
`
`US 2003/0022487 A1 Jan. 30, 2003
`
`Related U.S. Application Data
`
`Continuation—in—part of application No. 09/916,234, filed on
`Jul. 25, 2001.
`
`Int. Cl.7 .............................................. .. H01L 21/41
`U.S. Cl.
`...................... .. 438/680; 438/682; 438/685
`Field of Search ....................... .. 438/680, 682-685;
`361/234, 233
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,122,923 A
`5,252,807 A
`5,286,296 A
`
`....... .. 361/321
`6/1992 Matsubara et al.
`10/1993 Chizinsky ................. .. 219/390
`2/1994 Sato et al.
`................ .. 118/719
`
`5mmmA &m4mmma ............ ummm
`5,650,052 A
`7/1997 Edelstein et al.
`.... .. 204/192.12
`
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`200195821
`
`*
`
`7/2000
`
`OTHER PUBLICATIONS
`
`Kotaki et al., Novel Oxygen Free Titanium Silicidation-
`(OFS) Processing For Low Resistance and Termally Stable
`Salicide (self—sligned silicide) In Deep SubmicronDual Gate
`CMOS, JAPNDE, ISSN 0021-4922, 1995.*
`
`(List continued on next page.)
`
`Primary Examiner—Carl Whitehead, Jr.
`Assistant Examiner—Yennhu B. Huynh
`(74) Attorney, Agent,
`or Firm—Moser, Patterson &
`Sheridan, LLP
`
`(57)
`
`ABSTRACT
`
`Methods and apparatus are provided for forming a metal or
`metal silicide barrier layer. In one aspect, a method is
`provided for processing a substrate including positioning a
`substrate having a silicon material disposed thereon in a
`substrate processing system, depositing a first metal layer on
`the substrate surface in a first processing chamber, forming
`a metal silicide layer by reacting the silicon material and the
`first metal layer, and depositing a second metal layer in situ
`on the substrate in a second processing chamber. In another
`aspect, the method is performed in an apparatus including a
`load lock chamber, the intermediate substrate transfer region
`including a first substrate transfer chamber and a second
`substrate transfer chamber, a physical vapor deposition
`processing chamber coupled to the first substrate transfer
`chamber, and a chemical vapor deposition chamber coupled
`to the second substrate transfer chamber.
`
`39 Claims, 8 Drawing Sheets
`
` 54
`
`MICRO-
`PROCESSOR
`CONTROLLER
`
`422
`
`129
`
`/ /I
`402
`
`401/?
`
`4_00
`
`412
`
`414
`
`406
`
`§”
`
`\
`
`GILLETTE 1 012
`
`GILLETTE 1012
`
`

`
`US 6,740,585 B2
`Page 2
`
`6,225,176 B1
`6 238 533 B1
`’
`’
`6,251,759 B1
`
`5/2001 Yu ........................... .. 438/305
`5 2001 Satit unwa cha
`/
`et ,1? .....
`..........H 204/298.25
`6/2001 Guo et al.
`................ .. 438/584
`
`OTHER PUBLICATIONS
`
`Byun, et al. “Effect of Deposition Temperature and Sputter-
`ing Ambient on In Situ Cobalt Silicide Formation”, J.
`Electrochem. Sod’ 144(9) (Sep. 1997)’ pp. 3175_3179.
`f
`I
`1
`“A N
`C b It S 1.
`.d T h
`1
`0r
`“°“‘°’> et a ">
`‘?W ,, 0 a
`“C1 C . 6° “° Ogy
`0.15.—/tm CMOS Devices , IEEE Transactzons on Electron
`DEVICES 45(11) (NW 1998), PP- 2312-2318
`USSN 09/748,072 (Narwankan, et a1.), filed Dec. 21, 2000.
`
`* cited by examiner
`
`U.S. PATENT DOCUMENTS
`5,780,361 A
`7/1998 Inoue ....................... .. 438/683
`
`5,814,852 A
`9/1998 Sandhu et a1
`257/310
`5,838,035 A
`11/1998 Ramesh .................... .. 257/295
`5,851,896 A
`12/1998 Summerfelt
`.............. .. 438/396
`5,886,864 A *
`3/1999 Dvorsky
`361/234
`
`..................... .. 438/303
`5,899,720 A
`5/1999 Mikagi
`5,902,129 A
`5/1999 Yoshikawa etal.
`....... .. 438/592
`5,936,831 A
`8/1999 Kola et al.
`. . . . . . . .
`. . . . . .. 361/303
`6,033,537 A
`3/2000 Suguro
`. 204/192.2
`6,071,055 A
`6/2000 Tepman ..
`414/217
`6,165,807 A
`12/2000 Lee et al.
`.... N 438/18
`6,171,922 B1
`1/2001 Maghsoudnia .
`438/385
`6,179,983 B1
`1/2001 Reid et al.
`.................. .. 205/96
`6,218,716 B1
`4/2001 Wang et al.
`.............. .. 257/413
`6,221,766 B1
`4/2001 Wasserman ............... .. 438/656
`
`
`
`

`
`U.S. Patent
`
`May 25, 2004
`
`Sheet 1 of 8
`
`US 6,740,585 B2
`
`MICRO-
`
`PROCESSOR
`
`CONTROLLER
`
`

`
`U.S. Patent
`
`May 25, 2004
`
`Sheet 2 of 8
`
`US 6,740,585 B2
`
`46
`
`46
`
`54
`
`MICRO-
`PROCESSOR
`CONTROLLER
`
`

`
`U.S. Patent
`
`May 25, 2004
`
`Sheet 3 of 8
`
`US 6,740,585 B2
`
`176
`
`174
`
`172
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`U.S. Patent
`
`May 25, 2004
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`Sheet 4 of 8
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`US 6,740,585 B2
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`U.S. Patent
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`May 25, 2004
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`Sheet 7 of 8
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`US 6,740,585 B2
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`

`
`U.S. Patent
`
`May 25, 2004
`
`Sheet 8 of 8
`
`US 6,740,585 B2
`
`

`
`US 6,740,585 B2
`
`1
`BARRIER FORMATION USING NOVEL
`SPUTTER DEPOSITION METHOD WITH
`PVD, CVD, OR ALD
`
`RELATED APPLICATIONS
`
`This application is a continuation-in-part of co-pending
`U.S. patent application Ser. No. 09/916,234 [AMAT/5547],
`which was filed on Jul. 25, 2001, and is incorporated by
`reference herein.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to the fabrication of semi-
`conductor devices and to the apparatus and methods for
`deposition and annealing of materials on a semiconductor
`substrate.
`
`2. Description of the Related Art
`Recent
`improvements in circuitry of ultra-large scale
`integration (ULSI) on semiconductor substrates indicate that
`future generations of semiconductor devices will require
`sub-quarter micron multi-level metallization. The multilevel
`interconnects that lie at the heart of this technology require
`planarization of interconnect features formed in high aspect
`ratio apertures,
`including contacts, vias,
`lines and other
`features. Reliable formation of these interconnect features is
`
`very important to the success of ULSI and to the continued
`effort to increase circuit density and quality on individual
`substrates and die as features decrease below 0.13 pm in
`size.
`
`ULSI circuits include metal oxide semiconductor (MOS)
`devices, such as complementary metal oxide semiconductor
`(CMOS) field effect transistors (FETs). The transistors can
`include semiconductor gates disposed between source and
`drain regions.
`In the formation of integrated circuit
`structures, and particularly in the formation of MOS devices
`using polysilicon gate electrodes, it has become the practice
`to provide a metal silicide layer over the polysilicon gate
`electrode, and over the source and drain regions of the
`silicon substrate, to facilitate lower resistance and improve
`device performance by electrically connecting the source
`and drain regions to metal interconnects.
`One important processing technique currently used in
`CMOS processing technology is the Self-Aligned Silicida-
`tion (salicide) of refractory metals such as titanium and
`cobalt. In a salicide process using cobalt (Co), for example,
`the source and drain and polysilicon gate resistances are
`reduced by forming a high conductivity overlayer and the
`contact resistance is reduced by increasing the effective
`contact area of the source and drain with subsequently
`formed metal interconnects. Salicide processing technology
`seeks to exploit the principle that a refractory metal such as
`cobalt deposited on a patterned silicon substrate will selec-
`tively react with exposed silicon under specific processing
`conditions, and will not react with adjacent materials, such
`as silicon oxide material.
`
`For example, a layer of cobalt is sputtered onto silicon,
`typically patterned on a substrate surface, and then subjected
`to a thermal annealing process to form cobalt silicide (CoSi).
`Unreacted cobalt, such as cobalt deposited outside the
`patterned silicon or on a protective layer of silicon oxide,
`can thereafter be selectively etched away. The selective
`reaction of cobalt silicide will result
`in maskless, self-
`aligned formation of a low-resistivity refractory metal sili-
`cide in source, drain, and polysilicon gate regions formed on
`the substrate surface and in interconnecting conductors of
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`the semiconductor device. After the etch process, further
`processing of the substrate may occur, such as additional
`thermal annealing, which may be used to further reduce the
`sheet resistance of the silicide material and complete for-
`mation of cobalt silicide (CoSi2).
`However, it has been difficult to integrate cobalt silicide
`processes into conventional manufacturing equipment. Cur-
`rent processing systems performing cobalt silicide processes
`require transfer of the substrate between separate chambers
`for the deposition and annealing process steps. Transfer
`between chambers may expose the substrate to contamina-
`tion and potential oxidation of silicon or cobalt deposited on
`the substrate surface.
`Oxide formation on the surface of the substrate can result
`
`in increasing the resistance of silicide layers as well reduc-
`ing the reliability of the overall circuit. For example, oxi-
`dation of the deposited cobalt material may result in cobalt
`agglomeration and irregular growth of the silicide layer. The
`agglomeration and irregular growth of the cobalt layer may
`result in device malformation, such as source and drain
`electrodes having different thicknesses and surface areas.
`Additionally, excess cobalt silicide growth on substrate
`surface may form conductive paths between devices, which
`may result in short circuits and device failure.
`One solution to limiting cobalt and silicon contamination
`has been to sputter a capping film of titanium and/or titanium
`nitride on the cobalt and silicon film prior to transferring the
`substrate between processing systems. The capping film is
`then removed after annealing the substrate and prior to
`further processing of the substrate. However, the addition of
`titanium and titanium nitride deposition and removal pro-
`cesses increases the number of processing steps required for
`silicide formation,
`thereby reducing process efficiency,
`increasing processing complexity, and reducing substrate
`through-put.
`ULSI circuits also include the formation of interconnects
`
`or contacts between conductive layers, such as the cobalt
`silicide layer described above and a copper feature. Inter-
`connects or contacts generally comprise a feature definition
`formed in a dielectric material, such as silicon oxide, a
`barrier layer deposited on the feature definition, and a metal
`layer fill or “plug” of the feature definition. Titanium and
`titanium nitride films have been used as barrier layer mate-
`rial for the metal layer, such as tungsten, and the films are
`generally deposited by a physical vapor deposition tech-
`nique. However, deposition of titanium over silicon surfaces
`presents the problem of titanium silicide formation.
`Titanium silicide has been observed to agglomerate,
`which detrimentally affects subsequently deposited materi-
`als. Also, titanium silicide exhibits a radical increase in sheet
`resistance as feature sizes decrease below 0.17 gm, which
`detrimentally affects the conductance of the feature being
`formed. Further, titanium silicide has an insufficient thermal
`stability during processing of the substrate at temperatures
`of about 400° C. or higher, which can result in interlayer
`diffusion and detrimentally affect device performance.
`Additionally, titanium and titanium nitride PVD deposi-
`tion often occur at extremely low processing pressures, i.e.,
`less than 5><10‘3 Torr, compared with CVD deposition of
`materials such as tungsten, which may be deposited as high
`as about 300 Torr. This results in difficult integration of PVD
`and CVD processes in the same system. This has resulted in
`many manufactures using separate systems for the PVD
`titanium and titanium nitride deposition and the CVD tung-
`sten deposition. The increase in the number of systems
`results in increased production costs, increased production
`
`

`
`US 6,740,585 B2
`
`3
`times, and exposes the processed substrate to contamination
`when transferred between systems.
`Therefore, there is a need for a method and apparatus for
`forming barrier layers and silicide materials on a substrate
`while reducing processing complexity and improving pro-
`cessing efficiency and throughput.
`
`SUMMARY OF THE INVENTION
`
`Embodiments of the invention described herein generally
`provide methods and apparatus for forming a metal barrier
`or a metal silicide layer using a deposition and/or annealing
`process. In one aspect, a system is provided for processing
`a substrate including a load lock chamber, an intermediate
`substrate transfer region comprising a first substrate transfer
`chamber and a second substrate transfer chamber, wherein
`the first substrate transfer chamber is operated at a first
`pressure and the second transfer chamber is operated at a
`second pressure less than the first pressure and the first
`transfer chamber is coupled to the load lock chamber and the
`second substrate transfer chamber is coupled to the first
`substrate transfer chamber, at
`least one physical vapor
`deposition (PVD) processing chamber coupled to the first
`substrate transfer chamber, at
`least one chemical vapor
`deposition (CVD) processing chamber coupled to the second
`substrate transfer chamber, and at least one annealing cham-
`ber coupled to the second substrate transfer chamber.
`In another aspect, a method is provided for processing a
`substrate including positioning a substrate having a silicon
`material disposed thereon with patterned feature definitions
`formed therein in a substrate processing system, depositing
`a first metal layer on the substrate surface in a first process-
`ing chamber disposed on the processing system by a physi-
`cal vapor deposition technique, a chemical vapor deposition
`technique or an atomic layer deposition technique, forming
`a metal silicide layer by reacting the silicon material and the
`first metal layer, and depositing a second metal layer in situ
`on the substrate in a second processing chamber disposed on
`the processing system by a chemical vapor deposition tech-
`nique.
`In another aspect, a method is provided for processing a
`substrate including positioning a substrate having feature
`definitions formed in a silicon-containing material
`in a
`substrate processing system, depositing a metal layer on the
`silicon-containing material
`in the feature definitions,
`wherein the metal layer comprises cobalt, nickel, or com-
`binations thereof, and depositing a tungsten layer on the
`metal layer by a chemical vapor deposition technique at a
`temperature sufficient to form a metal silicide layer at an
`interface of the silicon-containing material and the metal
`layer.
`In another aspect, a method is provided for processing a
`substrate including positioning a substrate having feature
`definitions formed in a silicon-containing material
`in a
`substrate processing system, depositing a metal layer on the
`silicon-containing material in the feature definitions in a
`physical vapor deposition chamber, annealing the substrate
`in the physical vapor deposition chamber to form a metal
`silicide layer at an interface of the silicon-containing mate-
`rial and the metal layer, annealing the substrate to substan-
`tially convert the metal layer to metal silicide, and depos-
`iting a tungsten layer on the metal layer in a chemical vapor
`deposition chamber.
`In another aspect, a method is provided for processing a
`substrate including positioning a substrate having a silicon
`material disposed thereon with patterned feature definitions
`formed therein in a first processing chamber, exposing the
`
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`substrate to a plasma cleaning process in a first processing
`chamber, depositing a cobalt layer on the substrate surface
`and in the feature definitions by a physical vapor deposition
`technique in a second processing chamber, annealing the
`substrate at a first temperature in the second processing
`chamber to partially form a cobalt silicide layer, annealing
`the substrate at a second temperature greater than the first
`temperature in a third processing chamber to substantially
`form the cobalt silicide layer, and depositing a tungsten layer
`on the cobalt silicide layer by a chemical vapor deposition
`technique in a fourth processing chamber, wherein the first,
`second, third, and fourth processing chamber are disposed
`on one vacuum processing system.
`In another aspect, a method is provided for processing a
`substrate including positioning a substrate having feature
`definitions formed in a silicon-containing material
`in a
`substrate processing system, depositing a metal layer on the
`silicon-containing material
`in the feature definitions,
`wherein the metal layer comprises cobalt, nickel, or com-
`binations thereof, annealing the substrate at a first tempera-
`ture to form a metal suicide layer, depositing a tungsten layer
`on the metal layer by a chemical vapor deposition technique,
`and annealing the substrate at a second temperature greater
`than the first temperature.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`So that the manner in which the above recited aspects of
`the invention are attained and can be understood in detail, a
`more particular description of the invention, briefly summa-
`rized above, may be had by reference to the embodiments
`thereof which are illustrated in the appended drawings.
`It is to be noted, however, that the appended drawings
`illustrate only typical embodiments of this invention and are
`therefore not to be considered limiting of its scope, for the
`invention may admit
`to other equally effective embodi-
`ments.
`
`FIG. 1 is schematic top view of one embodiment of an
`integrated multi-chamber apparatus;
`FIG. 2 is schematic top view of another embodiment of an
`integrated multi-chamber apparatus;
`FIG. 3 is a cross-sectional view of one embodiment of a
`
`sputtering chamber included within the invention;
`FIG. 4 is an expanded view of FIG. 3 including upper area
`of the shields near the target;
`FIG. 5 is a plan view of one embodiment of a ring
`collimator;
`FIG. 6 is a partial plan view of one embodiment of a
`honeycomb collimator;
`FIG. 7A is a cross-sectional view of one embodiment of
`
`a pedestal for annealing a substrate;
`FIG. 7B is a cross-sectional view of another embodiment
`
`of a pedestal for annealing a substrate;
`FIGS. 8A—8C are schematic sectional views of one depo-
`sition process described herein; and
`FIG. 9 is a simplified sectional view of a silicide material
`used as a contact with a transistor.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`Embodiments of the invention described herein provide
`methods and apparatus for forming a metal silicide layer in
`a deposition chamber or substrate processing system. One
`embodiment described below in reference to a physical
`vapor deposition (PVD) process is provided to illustrate the
`
`

`
`US 6,740,585 B2
`
`5
`invention, and should not be construed or interpreted as
`limiting the scope of the invention. Aspects of the invention
`may be used to advantage in other processes, such as
`chemical vapor deposition, in which an anneal is desired for
`forming metal silicide layers.
`FIG. 1 is shows an integrated multi-chamber substrate
`processing system suitable for performing at
`least one
`embodiment of the physical vapor deposition, the chemical
`vapor deposition, and annealing processes described herein.
`The deposition and annealing processes may be performed
`in a multi-chamber processing system or cluster tool having
`a PVD chamber and a CVD chamber disposed thereon. One
`processing platform that may be used to advantage is an
`EnduraTM processing platform commercially available from
`Applied Materials, Inc., located in Santa Clara, Calif.
`FIG. 1 is a schematic top view of one embodiment a
`processing platform 35 including two transfer chambers 48,
`50, transfer robots 49, 51, disposed in transfer chambers 48,
`50 respectfully, and a plurality of processing chambers 36,
`38, 40, 41, and 42, disposed on the two transfer chambers 48,
`50. The first transfer chamber 48 and the second transfer
`
`chamber 50 are separated by pass-through chambers 52,
`which may comprise cooldown or pre-heating chambers.
`Pass-through chambers 52 also may be pumped down or
`ventilated during substrate handling when the first transfer
`chamber 48 and the second transfer chamber 50 operate at
`different pressures. For example, the first transfer chamber
`48 may operate between about 100 milliTorr and about 5
`Torr, such as about 400 milliTorr, and the second transfer
`chamber 50 may operate between about 1><10‘5 Torr and
`about 1><10‘8 Torr, such as about 1><10‘7. The processing
`platform 35 is automated by programming a microprocessor
`controller 54.
`
`The first transfer chamber 48 is coupled with two degas
`chambers 44, two load lock chambers 46, a reactive pre-
`clean chamber 42, at least one physical vapor deposition
`chamber, preferably a long throw physical vapor deposition
`(PVD) chamber 36, and the pass-through chambers 52. The
`pre-clean chamber may be a PreClean II chamber, commer-
`cially available from Applied Materials, of Santa Clara,
`Calif. Substrates (not shown) are loaded into the wafer
`processing system 35 through load-lock chambers 46.
`Thereafter,
`the substrates are sequentially degassed and
`cleaned in degas chambers 44 and the pre-clean chamber 42,
`respectively. The transfer robot 49 moves the substrate
`between the degas chambers 44 and the pre-clean chamber
`42. The substrate may then be transferred to the long throw
`PVD chamber 36 for deposition of a material thereon.
`The second transfer chamber 50 is coupled to a cluster of
`process chambers 38, 40, 41, and 43. Chambers 38 and 40
`may be chemical vapor deposition (CVD) chambers for
`depositing materials, such as tungsten, as desired by the
`operator. An example of a suitable CVD chamber includes
`W><ZTM chambers, commercially available from Applied
`Materials, Inc.,
`located in Santa Clara, Calif. The CVD
`chambers are preferably adapted to deposit materials by
`atomic layer deposition (ALD) techniques as well as by
`conventional chemical vapor deposition techniques. Cham-
`bers 41 and 43 may be Rapid Thermal Annealing (RTA)
`chambers, or Rapid Thermal Process (RTP) chambers, that
`can anneal substrates at vacuum or near vacuum pressures.
`An example of a RTA chamber 41 is a RADIANCETM
`chamber, commercially available from Applied Materials,
`Inc., Santa Clara, Calif. Alternatively, the chambers 41 and
`43 may be W><ZTM deposition chambers capable of perform-
`ing high temperature CVD deposition, annealing processes,
`or in situ deposition and annealing processes. The PVD
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`processed substrates are moved from transfer chamber 48
`into transfer chamber 50 via pass-through chambers 52.
`Thereafter, transfer robot 51 moves the substrates between
`one or more of the process chambers 38, 40, 41, and 43 for
`material deposition and annealing as required for process-
`ing.
`RTA chambers (not shown) may also be disposed on the
`first transfer chamber 48 of the processing platform 35 to
`provide post deposition annealing processes prior to sub-
`strate removal from the platform 35 or transfer to the second
`transfer chamber 50.
`
`While not shown, a plurality of vacuum pumps is dis-
`posed in fluid communication with each transfer chamber
`and each of the processing chambers to independently
`regulate pressures in the respective chambers. The pumps
`may establish a vacuum gradient of increasing pressure
`across the apparatus from the load lock chamber to the
`processing chambers.
`Alternatively, a plasma etch chamber, such as a
`Decoupled Plasma Source chamber (DPSTM chamber)
`manufactured by Applied Materials, Inc., of Santa Clara,
`Calif., may be coupled to the processing platform 35 or in a
`separate processing system for etching the substrate surface
`to remove unreacted metal after PVD metal deposition
`and/or annealing of the deposited metal. For example in
`forming cobalt silicide from cobalt and silicon material by
`an annealing process,
`the etch chamber may be used to
`remove unreacted cobalt material from the substrate surface.
`
`The invention also contemplates the use of other etch
`processes and apparatus, such as a wet etch chamber, used
`in conjunction with the process and apparatus described
`herein.
`
`FIG. 2 is a schematic top view of another embodiment of
`an integrated multi-chamber substrate processing system
`suitable for performing at least one embodiment the physical
`vapor deposition, chemical vapor deposition, and annealing
`processes described herein. In this embodiment,
`the first
`transfer chamber 48 is coupled to a cluster of process
`chambers 38, 40, 41, and 43, two load lock chambers 46, and
`pass-through chambers 52. Chambers 41 and 43 may be a
`RTA chambers that can anneal substrates at vacuum or near
`
`vacuum pressures, such as the RADIANCETM chamber, and
`chambers 38 and 40 are CVD chambers, such as W><ZTM
`chambers. The first
`transfer chamber 48 may operate
`between about 1><10‘5 Torr and about 1><10‘8 Torr, such as
`about 1><10’7, and the second transfer chamber 50 may
`operate between about 100 milliTorr and about 5 Torr, such
`as about 400 milliTorr.
`
`Alternatively, chambers 41 and 43 may be W><ZTM cham-
`bers capable of performing high temperature CVD
`deposition, annealing processes, or in situ deposition and
`annealing processes. The pass-through chambers 52 may
`additionally perform as degas chambers in addition to
`heating, cooling, and transporting functions.
`The second transfer chamber 50 is coupled to reactive
`pre-clean chambers 42, one or more long throw physical
`vapor deposition (PVD) chambers 36, and pass-through
`chambers 52. The second transfer chamber 50 configuration
`allows for substrate pre-cleaning, such as by a plasma clean
`method, and PVD deposition at a vacuum pressure of
`1><10‘8 prior to transfer to a higher pressure transfer cham-
`ber 48. The first transfer configuration allows higher pres-
`sure processing, such as annealing, compared to PVD
`processing, to be performed in the transfer chamber adjacent
`the loadlocks 46 and prior to substrate removal. The higher
`pressure first transfer chamber in this embodiment allows for
`
`

`
`US 6,740,585 B2
`
`7
`reduced pump down times and reduced equipment costs
`compared to configuration of system 35 using a near vacuum
`pressure, such as between about 1><10‘5 Torr and about
`1><10‘8 Torr, at the first transfer chamber 48.
`FIG. 3 illustrates one embodiment of a long throw physi-
`cal vapor deposition chamber. Example of suitable long
`throw PVD chambers are ALPS plus” and SIPTM PVD
`processing chambers, both commercially available from
`Applied Materials, Inc., Santa Clara, Calif.
`Generally, the long throw PVD chamber 36 contains a
`sputtering source, such as a target 142, and a substrate
`support pedestal 152 for receiving a semiconductor substrate
`154 thereon and located within a grounded enclosure wall
`150, which may be a chamber wall as shown or a grounded
`shield.
`
`The chamber 36 includes a target 142 supported on and
`sealed, as by O-rings (not shown), to a grounded conductive
`aluminum adapter 144 through a dielectric isolator 146. The
`target 142 comprises the material to be deposited on the
`substrate surface during sputtering, and may include cobalt,
`titanium, tantalum, tungsten, molybdenum, platinum, nickel,
`iron, niobium, palladium, and combinations thereof, which
`are used in forming metal silicide layers. For example,
`elemental cobalt, nickel cobalt alloys, cobalt tungsten alloys,
`cobalt nickel tungsten alloys, doped cobalt and nickel alloys,
`or nickel iron alloys may be deposited by using alloy targets
`or multiple targets in the chamber. The target may also
`include a bonded composite of a metallic surface layer and
`a backing plate of a more workable metal.
`A pedestal 152 supports a substrate 154 to be sputter
`coated in planar opposition to the principal face of the target
`142. The substrate support pedestal 152 has a planar
`substrate-receiving surface disposed generally parallel to the
`sputtering surface of the target 142. The pedestal 152 is
`vertically movable through a bellows 158 connected to a
`lower chamber wall 160 to allow the substrate 154 to be
`
`transferred onto the pedestal 152 through an load lock valve
`(not shown)
`in the lower portion of the chamber and
`thereafter raised to a deposition position. Processing gas is
`supplied from a gas source 162 through a mass flow con-
`troller 164 into the lower part of the chamber.
`A controllable DC power source 148 coupled to the
`chamber 36 may be used to apply a negative voltage or bias
`to the target 142. An RF power supply 156 may be connected
`to the pedestal electrode 152 in order to induce a negative
`DC self-bias on the substrate 154, but in other applications
`the pedestal 152 is grounded or left electrically floating.
`A rotatable magnetron 170 is positioned in back of the
`target 142 and includes a plurality of horseshoe magnets 172
`supported by a base plate 174 connected to a rotation shaft
`176 coincident with the central axis of the chamber 140 and
`
`the substrate 154. The horseshoe magnets 172 are arranged
`in closed pattern typically having a kidney shape. The
`magnets 142 produce a magnetic field within the chamber,
`generally parallel and close to the front face of the target 142
`to trap electrons and thereby increase the local plasma
`density, which in turn increases the sputtering rate. The
`magnets 172 produce an electromagnetic field around the
`top of the chamber, which magnets are rotated to rotate the
`electromagnetic field which influences the plasma density of
`the process to more uniformly sputter the target 142.
`The chamber 36 of the invention includes a grounded
`bottom shield 180 having, as is more clearly illustrated in the
`exploded cross-sectional view of FIG. 4, an upper flange 182
`supported on and electrically connected to a ledge 184 of the
`adapter 144. A dark space shield 186 is supported on the
`
`8
`
`flange 182 of the bottom shield 180, and fasteners (not
`shown), such as screws recessed in the upper surface of the
`dark space shield 186 fix it and the flange 182 to the adapter
`ledge 184 having tapped holes receiving the screws. This
`metallic threaded connection allows the two shields 180,
`186 to be grounded to the adapter 144. The adapter 144 in
`turn is sealed and grounded to an aluminum chamber
`sidewall 150. Both shields 180, 186 are typically formed
`from hard, non-magnetic stainless steel.
`A rotatable magnetron 170 is positioned in back of the
`target 142 and includes a plurality of horseshoe magnets 172
`supported by a base plate 174 connected to a rotation shaft
`176 coincident with the central axis of the chamber 140 and
`
`the substrate 154. The horseshoe magnets 172 are arranged
`in closed pattern typically having a kidney shape. The
`magnets 172 produce a magnetic field within the chamber,
`generally parallel and close to the front face of the target 142
`to trap electrons and thereby increase the local plasma
`density, which in turn increases the sputtering rate. The
`magnets 172 produce an electromagnetic field around the
`top of the chamber, which magnets are rotated to rotate the
`electromagnetic field which influences the plasma density of
`the process to more uniformly sputter the target 142.
`Returning to the overall view of FIG. 3, the bottom shield
`180 extends downwardly in a upper generally tubular por-
`tion 194 of a first diameter and a lower generally tubular
`portion 196 of a smaller second diameter to extend generally
`along the walls of the adapter 144 and the chamber body 150
`to below the top surface of the pedestal 152. It also has a
`bowl-shaped bottom including a radially extending bottom
`portion 198 and an upwardly extending inner portion 100
`just outside of the pedestal 152. Acover ring 102 rests on the
`top of the upwardly extending inner portion 100 of the
`bottom shield 180 when the pedestal 152 is in its lower,
`loading position but rests on the outer periphery of the
`pedestal 152 when it is in its upper, deposition position to
`protect the pedestal 152 from sputter deposition. An addi-
`tional deposition ring (not shown) may be used to shield the
`periphery of the substrate 154 from deposition.
`The chamber 36