IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL 2, NO. I, APRIL 1996
`
`35
`
`Telecommunications Applications of Ferroelectric
`Liquid-Crystal Smart Pixels
`
`Robert J. Mears, Associate Member, IEEE, William A. Crossland, Mark P. Dames, James R. Collington,
`Michael C. Parker, Steve T. Warr, Timothy D. Wilkinson, and Anthony B. Davey
`
`(Invited Paper)
`
`Abstract- Ferroelectric liquid crystal over silicon smart pix(cid:173)
`els offers potential advantages over conventional electronic and
`waveguide approaches to telecommunications switching. The role
`of such smart-pixel architectures in space/wavelength optical
`interconnect and in high-performance ATM switches based on
`interconnection of optically accessed memory is discussed.
`
`I. INTRODUCTION
`
`SMART pixels are the subject of considerable int~rest for
`
`telecommunications switching. 1 The purpose of thrs paper
`is to review applications of smart pixels based on ferroelectric
`liquid crystal (FLC) over silicon technology [2]. The large
`electrooptic effects in liquid crystals and the integratability
`of large numbers of modulators [e.g., 320 x 2402] with
`the functionality of silicon VLSI gives rise to a number of
`useful switching applications. The devices discussed employ
`free-space optics. We review fiber-to-fiber space [6] and wave(cid:173)
`length [7] switches that use FLC as phase modulators. We
`discuss fiber-to-fiber switches3 and ATM switch structures [9]
`with optically accessed silicon memories (opto-RAM) [10]
`that both use FLC shutters in a matrix-matrix [11], [12]
`configuration.
`The ever-increasing bit rate and the economic pressures on
`network operators to reduce the number of nodes in national
`networks leads to increasing node complexity and a potential
`
`Manuscript received June 14, 1996; revised July 12, 1996. This work was
`supported in part by the UK EPSRC under the POETS and OST Research
`Grants, Norte], and the DTL
`R. 1. Mears, 1. R. Collington, M. C. Parker, S. T. Warr, T. D. Wilkinson,
`and A. B. Davey are with the Cambridge University Engineering Department,
`Cambridge CB2 lPZ, U.K.
`W. A. Crossland is with the Cambridge University Engineering Department,
`Cambridge CB2 lPZ, U.K., and he is also a Norte! Research Professor of
`Photonics.
`M. P. Dames is with the Cambridge University Engineering Department,
`Cambridge CB2 lPZ, U.K., on sabbatical leave from BT Laboratories,
`Martlesham Heath, Ipswich, Suffolk IPS 7RE, U.K.
`Publisher Item IdentifierS 1077-260X(96)07968-3.
`1 See, for example, [I] and this issue.
`2 A 320 x 240 array of modulators on a 14-mm silicon chip is currently
`being built under DRA Contract MAL lb/2256. See also [3] (176 x 176
`modulator array) and [4], [5] (256 x 256 array).
`3 The OCPM project (optically connected parallel machines) is a collabo(cid:173)
`ration between British Aerospace (Sowerby Research Centre), BNR Europe
`(Norte!), Herriot Watt University, the University of Bath, and Thorn EMI CRL.
`Work at BNR Europe was subcontracted to the Engineering Department at the
`University of Cambridge. The project was coordinated by British Aerospace
`and was funded in part by the DTI and EPSRC. (DTI Reference No. IED2-
`430-30-004) See also Final Report: OCPM-039013-ADM-BAe-HW 960223
`and [8].
`
`electronic demultiplexing bottleneck. At the same time, the
`introduction of the EDFA [13], [14] to both submarine [15] and
`terrestrial routes4 increases the potential for WDM techniques
`and wavelength routing in such networks. A schematic view
`of a future optoelectronic node is shown in Fig. 1. With the
`possibility of aggregated switch node throughputs of 1 Tbps
`being required beyond the tum of the century, it would seem
`desirable, if not inevitable, that much of the transit node traffic
`will at least be only partially demultiplexed, if at all.
`There is a growing need for fiber matrix switches both
`in association with electronic switches (such as replacements
`to current digital crossconnects) and ultimately as space(cid:173)
`wavelength routing switches. This is represented by the upper
`part of Fig. 1. Optical transparency is essential for bit-rate
`independence, and the switching speeds necessary for network
`restoration and management, route protection, and mainte(cid:173)
`nance are approachable by FLC over silicon technology. Such
`devices might become an important part of wavelength-routed
`networks. The photonics group at Cambridge University is
`actively involved in research into such switches for both
`national and local area networks as part of the UK EPSRC
`POETS (parallel optoelectronic telecommunications systems)5
`and OST (optical switching testbed) projects.6
`The core switch technology represented by the lower part
`of Fig. 1 is seen as essentially a silicon electronic system, but
`optical interconnections will clearly be needed to achieve the
`necessary aggregate capacity. Switch capacities measured in
`Tb/ps are currently being postulated. Future deployment of
`public broadband ATM-based services [16] is likely to place
`severe demands on all-electronic approaches to switch design.
`While there have undoubtedly been impressive efforts in the
`density of gates achievable on silicon, this has never been
`matched by the performance of the metal-based interconnect
`between chips, either for multichip modules or backplanes.
`Since an ATM switching fabric requires a considerably higher
`degree of interconnectivity than that necessary for circuit
`switching, electronic interconnectivity is identified as a severe
`limitation of present approaches to broadband switch design. A
`
`4For example, MCI/Pirelli link between Chicago, IL, and Salt Lake City,
`UT.
`5 Parallel Optoelectronic Telecommunications Systems (POETS), UK EP(cid:173)
`SRC GR/144773. The POETS project involves Cambridge University (coor(cid:173)
`dinator), King's College, London, and University College London.
`6 0ptical Switching Testbed UK EPSRC GR/144728 (Cambridge University
`Engineering Department and Computer Laboratories).
`
`1077-260X/96$05.00 © 1996 IEEE
`
`FINISAR 1013
`
`

`

`36
`
`IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 2, NO. 1, APRIL 1996
`
`WDM
`STM-N
`
`WDMDemux
`
`Transit Switching
`
`Optical Cross
`Connects
`
`WDM
`STM-N
`
`WDMMux
`
`STM-N
`
`STM-N
`
`STM
`and/or
`ATM
`
`Local Switching
`
`Fig. 1. Schematic of a possible future optoelectronic node.
`
`free-space optically assisted approach to an ATM switch fabric
`may help by using its inherent spatial bandwidth to increase the
`connectivity and reduce the limiting effects of buses, low pin(cid:173)
`out integrated circuits, printed circuit boards, and multichip
`modules. Unless overcome, such pin-out limitations can result
`in suboptimal system partitioning and architectures. Previous
`important attempts at harnessing free-space optics have been
`technologically limited to a small switch node functionality
`as well as low fan-out [17]. Such a limitation has the effect
`of increasing the number of stages of switching necessary to
`produce a suitably connected fabric.
`In contrast to the many attempts at alleviating intercon(cid:173)
`nection bottlenecks by the selective replacement of electrical
`connections with on-board optical equivalents [18], we have
`adopted a fresh approach to the problem in an attempt to
`understand how a hybrid optoelectronic approach may fun(cid:173)
`damentally affect the design of an ATM switch fabric from
`a theoretical performance as well as an interconnection per(cid:173)
`spective. Clearly, any successful approach must partition the
`optics and electronics in a befitting manner. Such partitioning
`has already been described within the context of multiple(cid:173)
`quantum-well devices [19]. FLC over silicon opto-RAM [10]
`allows the incorporation of a degree of optical switching to
`assist the electronic switching. Some of the available optical
`parallelism must be used to obtain a high enough chip-to(cid:173)
`chip transfer rate due to the modest switching speed currently
`available from this form of light modulator. However, chip-to(cid:173)
`chip transfer rates are ideally matched to the read/write times
`of silicon VLSI structures, rather than the data rates of the
`incoming links.
`
`(a)
`
`Glass Cover
`
`AI Edge
`Contact
`
`GlueSeal /
`
`Silicon me
`
`(b)
`
`Fig. 2. FLC on silicon technology.
`
`II. FLC OVER SILICON SMART-PIXEL TECHNOLOGY
`
`The addition of a thin layer of ferroelectric liquid crystal to
`standard CMOS silicon yields an optoelectronic technology
`that boasts the versatility of VLSI with massively parallel
`optical input/output [2]. Photodetectors can be implemented
`within CMOS design rules and the very large electrooptic
`effects of the liquid crystal enable the implementation of
`both intensity and 1r-phase modulators (see Section III). A
`
`schematic construction of a smart-pixel device and a photo(cid:173)
`graph of a recently designed 320 x 240 modulator chip are
`shown in Fig. 2.
`The modulator bandwidth is a function of the required
`electrooptic effect and the permissible driving voltage. A
`recent optical interconnect project, optically connected parallel
`machine (OCPM), demonstrated intensity shutters with a re(cid:173)
`configuration time of less than 20 JLS at 45 °C using addressing
`voltages of 10 V [8]. The fastest reconfiguration time for
`
`

`

`MEARS eta/.: TELECOMMUNICATIONS APPLICATIONS OF SMART PIXELS
`
`37
`
`Amplitude Mode rn ........ t:c. a
`' m .... 'W .... E
`
`Transmitted Power
`
`~if =0
`~n =sin2 28
`
`I:!= sin2 e
`T_1 = -sin2 8
`
`Poiariser
`
`FLC·SLM
`with ±V applied
`
`Analyser
`
`Phase Mode
`
`Polariser
`
`FLC-SLM
`with ±V applied
`
`Analyser
`
`-·-- Circuitry
`
`+---- FLC Light
`Modulator
`
`Fig. 3. Opto-RAM cell (single pixel).
`
`intensity modulation suitable for interconnect is extrapolated to
`be about 1 J.iS at 80 °C [20]. To achieve efficient phase modu(cid:173)
`lation, a larger switching angle of up to 1r /2 radians is required
`[21]. For fields of 10 V J..im- 1 or less, this limits the switching
`times for currently available materials to the order of 400 J.iS
`at 45 oc but times below 40 J.iS have been obtained at 80 oc
`[22]. Switching down to 200 ns has been observed for much
`smaller switching angles (:S;2°) in electroclinic liquid crystals
`[23]. While the implied lack of contrast/loss would probably
`make electroclinic LC' s unsuitable for optical interconnect,
`they do have promise for signaling modulators in architectures
`such as the opto-RAM. The driver circuitry can be as simple
`as a single transistor (DRAM), so that given a small-geometry
`CMOS process, the limiting smart pixel packing density will
`be the optical input/output (photodiode/modulator) geometry,
`even for relatively complex pixel logic. The layout for an
`experimental optical read opto-RAM memory pixel is shown
`in Fig. 3.
`The pixel shown in Fig. 3 is on a 70-J..im pitch with a
`modulator size of approximately 30 J.im. The large dimensions
`are due to the 2.0-J.im CMOS used and to allow a large
`read beam to simplify alignment in our experimental system.
`As liquid crystal technology matures and switching voltages
`decrease, it will be possible to reduce the process geometry.
`Also, as the optical beam used to illuminate the modulator
`becomes closer to being diffraction limited, then the modulator
`will be of order 5 IJ.m. Previous work has focused two beams
`into a 6-J..imX 20-J.im area [24], although with ferroelectric
`liquid crystals only one beam is required. This is because
`the transmission of a reference beam is not required due
`to a high contrast ratio alleviating any problems associated
`with variations in receiver threshold over the area of a die.
`Therefore, feasible pixel pitches will be of order 15 J.im with
`the die size approaching 20 mm. (Crosstalk considerations
`suggest a limiting pixel pitch of about 8 J.im [11]). This will
`allow for at least 106 pixels per single chip.
`
`Ill. LIQUID-CRYSTAL MODULATION SCHEMES
`Ferroelectric liquid crystal modulators can be configured
`as either phase or intensity modulators and drive schemes
`
`Fig. 4. Modulation schemes for FLC smart pixels.
`
`can be chosen for continuous or synchronized read-out [25].
`The choice of modulation and drive scheme have important
`consequences for smart-pixel system design. The thin layer of
`(surface stabilized) ferroelectric liquid crystal can be optically
`modeled as a rotatable waveplate with fast and slow axes in
`the plane of the modulator, i.e., perpendicular to the direction
`of light propagation. The alignment layers are usually chosen
`so that the crystal will lie in one of two bistable states such that
`there is an angle of 28 between the fast axes of the two states
`where 8 is known as the tilt angle of the crystal. Application
`of an electric field is required to switch from one state to
`the other and the field must be reversed to switch back. The
`ferroelectricity (spontaneous polarization) of the LC implies
`that charge needs to be transferred to and from the crystal-too
`little charge will result in incomplete switching. To ensure
`long lifetime of the crystal, charge balancing should also be
`maintained. Interconnect applications demand a drive scheme
`which permits continuous viewing. The preferred scheme for
`the smart-pixel architectures uses an alternating front electrode
`(ITO on glass) voltage. Thus, depending on the phase of the
`silicon pad voltage, an FLC field is produced which, in one
`half cycle, switches pixels needing to change from state 1 to
`state 2 and, in the next half cycle, those changing from state
`2 to state 1, otherwise leaving a net zero voltage across the
`crystal so that pixels not needing to change are left unaltered.
`The schemes for intensity and phase modulation are de(cid:173)
`picted in Fig. 4. A fuller description may be obtained from
`Jones' matrix analysis [26], but a more qualitative description
`is adopted here.
`Perhaps the key difference between intensity and phase
`modulation, which has only been fully elucidated relatively
`recently [27] is that, to obtain high contrast, intensity mod(cid:173)
`ulation is polarization sensitive, requiring crossed polarizers
`at the input and output, and therefore, polarization control
`of the source. However, when phase modulators are used
`to form a (binary) phase grating or hologram, the relative
`modulation between pixels in alternate states is always 1r
`radians irrespective of the input polarization. Thus, in the
`output plane, there will be a central (zero-order spot) whose
`intensity will vary as sin2 (28)
`J(zero order) = Io [ 1 - sin2 (28) sin2 ~]
`
`(1)
`
`

`

`38
`
`IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 2, NO. I, APRIL 1996
`
`OCPM Fibre-to-fibre Optical Crossbar
`
`collecting
`lenses
`/
`
`multi mode fibre
`output array
`
`\
`
`fanout hologram
`(multiple imaging)
`
`mono mode
`fibre
`input array
`
`reflective
`SLM
`
`polarising
`beamsplitter
`
`Fig. 5. The matrix-matrix intensity crossbar.
`
`where Ia is the incident intensity and 8 is the optical path
`difference between the fast and slow axes expressed in radians)
`and the intensity of the diffracted spots will be independent
`of the input polarization. It is this unique feature which
`enables the design and implementation of optically transpar(cid:173)
`ent beam-steering switches for telecommunications systems.
`Furthermore, the attainment of binary phase is wavelength
`independent, being essentially a symmetry property. Thus, the
`phase holograms can be expected to be broadband, the only
`limitation being the unavoidable shifts in spot position from
`the wavelength dependence of diffraction.
`
`IV. SPACE-SWITCH ARCHITECTURES
`
`A. Matrix-Matrix Intensity Switches
`
`The majority of implementations of optical switches using
`FLC have been of the full crossbar architecture, since the
`use of free-space optics permits high fan-out and fan-in.
`The OCPM demonstrator, for example, uses an input array
`of 64 single-mode high-birefringence fibers and an output
`array of 64 multimode fibers. The interconnect is based
`on the matrix-matrix principle [11], [12] with holographic
`fan-out and fan-in. The matrix-matrix crossbar makes more
`efficient use of the numerical aperture than, for example, the
`vector-matrix multiplier [28]. As it performs a full crossbar
`function it allows both broadcast and multicast. A schematic
`of the matrix-matrix crossbar is shown in Fig. 5. The critical
`performance parameters are the loss (and scaleability), isola(cid:173)
`tion/crosstalk, and the ease of implementation of the routing
`algorithm.
`
`I) Loss: Fan-out losses of 1/ N are unavoidable through
`the replication of the inputs to achieve the full crossbar
`function. Holographic replication can be achieved with low
`excess loss ( rv 1 dB) [29] at the expense of making the switch
`relatively narrow-band ( rv ± 1 nm). For the matrix-matrix
`crossbar, the fan-in losses are reduced by the use of multimode
`fiber but would scale as 1/ N if single-mode output were
`required. A single-mode fiber-to-multimode fiber loss of 28
`dB was achieved in the first prototype 64 x 64 switch against
`an intrinsic fan-out loss of 18 dB.
`2) Isolation: The isolation that can be achieved is directly
`related to the intensity contrast of the individual FLC pixels.
`There is usually a single pixel acting as each crosspoint. A
`single port isolation of 16.6 dB was measured in the OCPM
`demonstrator, which was dominated by the poor 40: 1 contrast
`ratio of the SLM. With better quality mirrors, it is reasonable
`to expect a contrast of 25-30 dB to be achievable with FLC
`over silicon devices.
`3) Control and Arbitration: The use of a single-stage
`crossbar architecture with intensity pixels acting as single
`crosspoints permits the trivial routing algorithm: open the
`requisite pixel to make the connection. Likewise, arbitration
`requires that only one pixel in a block associated with each
`output is open at one time.
`For applications where polarization control of the source
`fibers is permitted and where multimode fibers can be used,
`the single-stage matrix-matrix crossbar remains attractive for
`moderate switch sizes. The OCPM 64 x 64 demonstrator was
`tested at 270 Mb/ps at I0- 12 BER using 3 mW in fiber laser
`power at 800 nm. An existing optical design suggests a 33-dB
`power budget at 2.5 Gb/ps with a +3 dBm source and -33-
`
`

`

`MEARS et al.: TELECOMMUNICATIONS APPLICATIONS OF SMART PIXELS
`
`39
`
`reflection hologram
`
`Fig. 6. Schematic of one possible implementation of a holographic crossbar.
`
`array
`
`dBm receiver with an excess loss of 7.5 dB over the intrinsic
`fan-out losses. Subject to the acceptable contrast, these figures
`would support a 144 x 144 crossbar at 10- 12 BER.
`
`B. Holographic Beam-Steering Switches
`
`Since the first proposal for FLC on silicon modulators to
`be used as (binary) phase holograms for optical intercon(cid:173)
`nect [30], [31], there has been much debate over their best
`configuration for switching. The architectures and implemen(cid:173)
`tation differ from the polarization-dependent, intensity-based
`matrix-matrix crossbar in a number of important respects.
`First, the use of groups of phase pixels associated with each
`input permits beam-steering architectures. Although a single(cid:173)
`stage crossbar can be implemented, it is more power- and
`crosstalk-efficient to use a two-stage architecture such as
`the deflector-selector [32]. The fan-out of a single stage is
`determined by the space-bandwidth product (number of pixels)
`and the physical dimensions of the output fiber array. Clearly,
`if the fan-out does prove a limitation for very large switches,
`then banyan, Clos, or other architectures might be employed,
`with a concomitant increase in the complexity of control and
`arbitration. However, single-stage dynamic fan-out of 1:64 or
`1:128 appears technologically feasible-routing on array sizes
`of this dimension has been demonstrated in the laboratory, but
`not yet to single-mode fiber arrays. A schematic of one mode
`of interconnection for a 1 : N switch using a FLC silicon
`backplane is shown in Fig. 6.
`: 1 stage is
`1) Loss: The loss of a single 1 : N or N
`predominantly a function of the efficiency of the beam-steering
`FLC phase hologram. Binary phase holograms, because of the
`output plane symmetry, incur a loss to a single spot of about
`4 dB. This may not be so severe if it is remembered that
`the symmetric spot might be usefully employed to provide
`redundancy.
`Free-space single-mode to single-mode fiber losses of 2-3
`dB have been observed in simple laboratory switch rigs.
`The other potential source of loss is the use of nonoptimal
`FLC switching angle and thickness. While this has hampered
`experimental demonstrations to date (typically incurring a 6 dB
`
`penalty), new FLC materials such as low molar mass siloxanes
`[22] have been shown in the laboratory to obviate this penalty.
`2) Isolation: Unlike the matrix-matrix crossbar, the isola(cid:173)
`tion of the holographic beam-steering switch is not so critically
`dependent on the liquid crystal alignment, since binary-phase
`operation is assured. Rather, it is dependent on the number of
`pixels associated with the beam-steering hologram and residual
`scattering losses. A crude estimate for the single-port isolation
`is [33] is
`
`Isolation,..._, 10 log 10 [2(;'~ rJ)] dB
`
`(2)
`
`where m is the number of pixels in the routing hologram and
`17 is the hologram efficiency. Equation (2) assumes that power
`is distributed evenly over the output plane away from the
`desired spot. Various solutions can be theoretically determined
`which dramatically reduce the power at other fiber positions
`than the desired output [34], [35]. However, experimentally
`determined isolation to date has yielded figures more closely
`in agreement with (2) (typically 25-35 dB). For example, the
`fiber switch reported in [27] has a fiber-to-fiber loss of 13 dB
`and an isolation of 35 dB for a 64 x 64 routing hologram.
`Of course, in the deflector-selector architecture, the single(cid:173)
`stage isolation will be squared (per input port), i.e., 50-70 dB.
`Such figures are compatible with the stringent requirements
`on crosstalk for optically transparent [36] and particularly for
`wavelength-routed systems [35].
`3) Control and Arbitration: For a N x N switch (or each
`: 1 switch), N different routing holograms
`1 : N or N
`will be required. These are of course determined during the
`switch fabrication. Irregularities in the fiber array can be built
`into the hologram design, and the precise holograms can be
`optimized in situ [37]. As an example, the 1:16 experimental
`fiber switch shown in Fig. 7 used a series of search holograms
`to determine the core positions of the fibers in the array and
`hence the optimum hologram set. It is envisaged that further
`monitoring and optimization should be possible during the
`lifetime of the switch. It should be possible to extend the FLC
`over silicon smart-pixel technology to incorporate the (digital)
`hologram patterns in on-chip memory (a 1:64 module would
`
`

`

`40
`
`IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL 2, NO. I, APRIL 1996
`
`(-48,96)
`
`(-1,93)
`
`(48,94)
`
`(94,95)
`
`(-46,50)
`
`(0,48}
`
`(48,47)
`
`(90,49)
`
`0~--------~--~--~~_J
`1.5424!.1-m
`1.5624!.1-m
`2nm/div
`
`5nW
`/div
`
`(a)
`
`(b)
`
`1.5624!.1-m
`2nm/div
`
`Fig. 8. Wavelength filter tuning characteristic.
`
`the experimental fixed (binary) phase grating. With the full
`switching angle and a commercial low-loss phase grating, the
`filter should have losses of less than 10 dB. Although the
`current losses associated with FLC phase holograms prohibit
`a competitive filter, the tunability and reproducibility of the
`wavelength filter makes it an attractive prospect for the future.
`It is also possible to design multiple wavelength multiplexers
`and demultiplexers based on the passive designs described in
`[39]. By combining active or passive WDM splitters with
`holographic space switches, it is possible to create flexible
`optical routers with crosstalk performance which outstrips
`acoustooptic tunable filters (AOTF) [40].
`The digitally tunable filter can be put inside a laser cavity to
`yield a precisely controllable WDM source [41]. Fig. 9 shows
`the discrete tuning of such a laser in 1.3 nm steps across the
`erbium window at 1.55 J..im. A long-term stability of 0.1 nm
`(monitored over four hours) was limited by the mechanical
`instability of the laboratory rig and would be considerably
`improved by a solid glass (e.g., GRIN) interconnect. The short(cid:173)
`term linewidth (measured by a self-heterodyne technique for
`a ring laser configuration) is of the order of 1 kHz.
`
`VI. 0PTO-RAM TECHNOLOGY
`
`Many of the proposed optical information processing and
`interconnection systems involve interaction and exchange of
`data between spatial light modulators and silicon electronic
`
`0000
`0000
`oooo
`80 00
`
`(-45,1}
`
`(0,0) ~~s
`
`(49•4)
`
`(43,1}
`
`(-44,-46)
`
`(0,-46)
`
`(52,-45)
`
`(97,-44)
`
`Fig. 7. Fiber array alignment for holographic 1:16 interconnect.
`
`require about 500 kB). Like the crossbar, the fully connected
`deflector-selector has a straightforward routing algorithm.
`
`V. WAVELENGTH ROUTING
`
`The diffracted spot positions in the beam-steering switch
`are of course wavelength-dependent. The relatively large FLC
`pixel dimensions compared to the wavelength lead to small
`diffraction angles and the need to pack output fibers closely
`together if larger dimension switches are to be achieved.
`The wavelength sensitivity depends on the tolerance of the
`output fiber launch efficiency to lateral displacements. To a
`first approximation, the ratio of this tolerance to the actual
`deflection (i.e., displacement of the fiber core from the zero(cid:173)
`order optical axis) is equal to the ratio of the bandwidth
`to the wavelength. Thus, at a telecoms wavelength of 1.55
`J.Lm, a tolerance of ±5 J..im yields a bandwidth of 30 nm for
`a 500-J.Lm displacement. The need for compact fiber arrays
`is thus important for large dimension switches if a broad
`bandwidth is to be maintained. On the other hand, the small
`wavelength dependence can be turned to advantage to form
`a wavelength filter if a larger deflection angle is used. This
`can be achieved by concatenating a fixed phase grating of
`higher spatial frequency with the FLC device. The resultant
`filter is tuned by changing the digitally generated FLC binary
`phase hologram-hence, a digitally tunable wavelength filter
`[7], [38]. Fig. 8 shows the layout of an experimental filter
`using a transmissive FLC SLM at a wavelength of 1.5 J.Lm.
`The filter is tunable in steps of 1.3 nm over more than 80
`nm at 1.5 J..im with a FWHM bandwidth of 2 nm. The step
`and bandwidth are both functions of the physical layout and
`can be optimized for other applications. They were chosen
`here to reflect a view of the likely future channel spacing
`in commercial WDM systems. An overall fiber-to-fiber loss
`of 22 dB was due to the small switching angle of the FLC
`in the SLM and the large diffraction losses associated with
`
`

`

`MEARS eta!.: TELECOMMUNICATIONS APPLICATIONS OF SMART PIXELS
`
`41
`
`'2
`0
`
`·13dBm
`
`Trunk line inputs Support chips
`~ ~ High-speed
`~ multiple)(ed
`~serial/ink
`
`Memory sector
`\~
`I
`4--1--- Psrallelised
`data block
`
`1:
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`-33dBm
`
`i = lOdB
`= "' Ill
`Q "' ~
`~
`~ ;:
`0
`D.
`
`-53dBm
`
`Fig. 9. Digitally tunable laser characteristic.
`
`Wavelength
`
`Fig. II. Use of peripheral chips to support a sectorized opto-RAM.
`
`Modulator
`Array
`
`Interconnection optlcs
`(farroutlfan-inlshuffle)
`
`Opta-RAM
`plane 2
`
`Columnl/0
`
`Column~
`
`Column
`i\ddrcss
`t.ines
`
`Switchabfe
`sector
`
`Fig. 10. Block diagram of an optically accessed memory (optical-read).
`
`Fig. 12. Free-space optical interconnection of two planes of opto-RAM
`smart pixels.
`
`memory. A generic component in these applications might
`be an "opto-RAM," i.e., an optically accessed electronic
`memory which: 1) optically presents/receives parallelized data
`images to/from a high fan-out free-space optical network and
`2) performs electronic rearrangement within memory sectors
`[10]. The internal circuitry of opto-RAM is almost identical
`to a standard VLSI CMOS RAM, with the exception of
`the addition of opto-electronic transducers to modulate/detect
`light when optically reading/writing the memory. Fast memory
`access times are ,..,_, 1-10 ns per word. The modulator/detector
`rate can be matched to the number of words on the opto(cid:173)
`RAM multiplied by the access time, i.e., a switching rate of
`the order of 10 JLS, which is well suited to FLC technology.
`This could enable very fast block data transfer to be made
`between areas of memory and even spatial processing (such
`as block switching or optical transformation of data L42J)
`to be carried out within the optical interconnect. A classic
`connection intensive application of this type is in (core)
`telecommunications switching.
`Fig. 10 shows a block diagram of a complete optical read
`opto-RAM, where no sectorization has been shown for clarity.
`The electronic circuitry of the memory is identical to a
`VLSI CMOS electronic memory (with address and data buses
`
`being the main inputs) however a modulator array has been
`added to allow for optical read. Each bit of storage has
`its own modulator. The equivalent optical write opto-RAM
`incorporates an integrated silicon photodetector [43], rather
`than a modulator, for each bit of storage. Such photodetectors
`have been successfully operated at 224 Mb/ps [43].
`Fig. 11 shows the operational configuration of an optilcal
`read opto-RAM, showing 16 parallelized data images optically
`presented to the free-space optical center stage. The opto-RAM
`has been partitioned into four sectors due to addressing con(cid:173)
`straints. Such constraints arise due to the aggregate data rate
`to/from a device exceeding the rate at which a single memory
`may be addressed. Sectorization therefore allows the opto(cid:173)
`RAM to be scaleable with future requirements. Each sec:tor
`has its own data and address buses which are independent
`of other sectors. Data coming in on a particular trunk link,
`which could be a high-speed fiber serial multiplex (e.g., STM-
`16), may only be written into an area in the memory sector
`addressed by the associated support chip. The support chip
`writes data into the opto-RAM at a suitable location as defined
`by the address of that location. Suitable locations are defined
`as locations which can be optically switched, by the free-space
`optical switch, to free locations on the output links. This results
`
`

`

`42
`
`IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 2, NO. I, APRIL I996
`
`switchable F-fold tan-out/
`sector
`tan-in
`
`/,./
`
`Fig. 13. Model for interconnected opto-RAM planes using F-fold fan-ouUfan-in and shuffle.
`
`1
`
`N
`
`Theoretical
`lower bound
`from (3)
`
`g1o·•
`:.0
`\Q
`D
`0
`0.10 6
`
`Ul
`Ul
`
`:§:
`J 10 8
`
`in the support chips being responsible for part of the switch
`arbitration. Output links are also accessed by a similar opto(cid:173)
`RAM structure. Each support chip must therefore be able to
`determine the output locations which have already been used.
`The support chip accesses the address bus of the opto-RAM
`sector it is writing to in order to specify the correct spatial
`position and then writes the data to that location. Data may be
`in the form of a multiplicity of bits presented in parallel as an
`image to the optical switch, where in the limit this parallelism
`could be an entire ATM cell (approximately 400 bit).
`
`VII. GENERALIZED ATM SWITCH ARCHITECTURE
`We have explored the tradeoffs which exist between the
`degree of interchip optical fan-out/fan-in versus on-chip opto(cid:173)
`RAM sector functionality for interconnecting two planes of
`opto-RAM in a manner suitable to meet ATM switching
`connectivity requirements. A suitable interconnect for ATM
`switching must meet certain criteria.
`1) It must (in principle) be technologically and practically
`realizable.
`2) It must provide acceptable connectivity and hence cell(cid:173)
`loss probability.
`3) A path-hunting mechanism for routing ATM cells from
`input opto-RAM plane to output opto-RAM plane must
`be able to be carried out within the time limits imposed
`by ATM (for STM-1 input lines at 155 Mb/ps, this
`imposes a minimum cell period time restriction of 2.7
`J.I,S to find all the paths through the fabric if only one
`cell per channel is switched per distribution period, up
`to a maximum of 256 J.I,S set by the permissible latency
`per node).
`As an example, Fig. 12 schematically shows an opto-RAM
`plane partitioned into a number (1