BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`TOSHIBA CORPORATION; TOSHIBA AMERICA, INC.;
`TOSHIBA AMERICA ELECTRONICS COMPONENTS, INC.; and
`TOSHIBA AMERICA INFORMATION SYSTEMS, INC.
`Petitioner
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`v.
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`INTELLECTUAL VENTURES II LLC
`Patent Owner
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`Case IPR2014-00418
`U.S. Patent No. 5,500,819
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`DECLARATION OF WILLIAM R. HUBER, D.Sc., P.E. IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`IV 2001
`IPR2014-00418
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`TOSHIBA CORPORATION; TOSHIBA AMERICA, INC.;
`TOSHIBA AMERICA ELECTRONICS COMPONENTS, INC.; and
`TOSHIBA AMERICA INFORMATION SYSTEMS, INC.
`Petitioner
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`v.
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`INTELLECTUAL VENTURES II LLC
`Patent Owner
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`
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`Case IPR2014-00418
`U.S. Patent No. 5,500,819
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`DECLARATION OF WILLIAM R. HUBER, D.Sc., P.E. IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`IV 2001
`IPR2014-00418
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`Case IPR2014-00418
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`U.S. Patent 5,500,819
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`I, William R. Huber, D.Sc., P.E., a resident of West End, North Carolina,
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`declare as follows:
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`1.
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`I have been retained on behalf of Intellectual Ventures II LLC, to
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`provide declaratory evidence in inter partes review of U.S. Patent 5,500,819
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`(“’819 patent”).
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`2.
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`I am being compensated for my work related to this inter partes
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`review proceeding. My compensation is not dependent on and in no way affects
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`the substance of my statements in this Declaration.
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`3.
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`I have reviewed and am familiar with the specification and the
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`claims of the ’819 patent. I will cite to the specification using the following format:
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`(Ex. 1001, ’819 patent, 1:1-10). This example citation points to the ’819 patent
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`specification at column 1, lines 1-10.
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`4.
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`Along with the petition for inter partes review of the ’819 patent
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`(Paper 1; “Petition”), I have reviewed and am familiar with following references:
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`• U.S. Patent 5,500,819 to Runas (Ex. 1001; “’819 patent” or “Runas”);
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`• Prosecution File History for U.S. Patent 5,500,819 (Ex. 1002);
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`• U.S. Patent 4,745,577 to Ogawa et al. (Ex. 1003; “Ogawa ’577”);
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`• Declaration of Robert J. Murphy (Ex. 1004; “Murphy Dec.”).
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`• U.S. Patent 4,773,045 to Ogawa (Ex. 1005; “Ogawa ’045”);
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`U.S. Patent 5,500,819
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`• Japanese Patent Appl. No. H3-46832 to Ogawa (Ex. 1006; “JP ’832”);
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`and
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`• Ex Parte Reexamination File History for U.S. Patent 5,500,819 (Ex.
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`1007).
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`5.
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`I have also reviewed and refer to the Board’s Decision to Institute
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`Inter Partes Review in this proceeding (Paper 7; “Decision”), and the transcript
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`from the deposition of Robert J. Murphy, Toshiba’s declarant (Ex. 2002).
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`6.
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`I am familiar with the technology at issue and the state of the art at
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`the time the application leading to the ’819 patent was filed.
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`7.
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`I have been asked to provide my technical review, analysis,
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`insights, and opinions regarding the above-noted references, as well as various
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`semiconductor industry practices.
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`Qualifications
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`8. My academic and professional pursuits are closely related to the
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`subject matter of the ’819 patent.
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`9.
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`I have more than 50 years of experience in the semiconductor field.
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`I have over 30 years of experience in the hands-on product development, research,
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`and management of complex semiconductor integrated circuit products. This
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`experience includes the design of memory devices. I also have over 20 years of
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`technical consulting experience in the field of semiconductor memory devices.
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`10.
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`I earned a Bachelor of Science degree in Electrical Engineering in
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`1962 from the University of Pittsburgh in Pittsburgh, Pennsylvania. One year later,
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`I earned a Master of Science degree in Electrical Engineering from The Ohio State
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`University in Columbus Ohio. In 1969, I earned a Doctor of Science degree in
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`Electrical Engineering from the University of Pittsburgh.
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`11.
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`I am currently the President of Electronics Consulting Engineers
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`(ECE). I founded ECE in 1993. ECE has locations in Melbourne, Florida and West
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`End, North Carolina and provides patent-related services such as licensing
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`evaluation, validity and infringement assessment, and litigation support. I have
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`provided litigation support to various integrated circuit companies in a wide array
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`of semiconductor memory technologies such as DRAM, SDRAM, and Flash
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`memory. In providing this support, I rely on my technical experiences in the field
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`of semiconductor memory: (1) over 30 years of hands-on and management
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`experience in the semiconductor field, including the design of semiconductor
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`memory devices; (2) my involvement with semiconductor standards committees,
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`including the Joint Electron Device Engineering Council (JEDEC) Committee on
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`semiconductor memory devices; and, (3) authoring continuing education courses
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`on semiconductor memory technologies.
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`12. My hands-on and management experience in the semiconductor
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`field started at Bell Telephone Laboratories in 1962, where I was a Supervisor and
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`Member of Technical Staff. While at Bell, along with my group, I developed and
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`applied the concept of redundancy to semiconductor memory chips. This
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`development had a significant impact on the semiconductor memory field since it
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`reduced the impact of manufacturing defects on production yield and overall
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`product cost. I co-authored and presented a paper on this memory redundancy
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`concept. The paper won the Best Paper Award at the International Solid-State
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`Circuits Conference in 1979. I also authored/co-authored three other papers
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`focusing on semiconductor memory devices during my time at Bell. I left Bell in
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`1982.
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`13. From 1982 to 1989, I was Manager of Integrated Circuit
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`Development and Manager of Reliability and Quality Assurance at General
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`Electric Company Microelectronics Center in Research Triangle Park, North
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`Carolina. I planned and directed new product and technology development and
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`characterization. One of the products we developed during this time was a 64K
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`radiation-hardened SRAM.
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`14. From 1989 to 1994, I worked at Harris Corporation in Melbourne,
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`Florida as Senior Scientist and Director of Engineering—Military and Aerospace
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`Division. I planned and directed new product development and characterization.
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`This effort included the development of radiation-hardened field-programmable
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`gate array devices and also involved the design of a 256K radiation-hardened
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`SRAM.
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`15.
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`In addition to my engineering experiences described above, I
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`played an active role in various Joint Electron Device Engineering Council
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`(JEDEC) committees. I was an active member of the JEDEC JC-42 Committee on
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`Semiconductor Memory Devices from its early days in 1972 until 1984. As a
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`member, I met regularly with memory specialists from companies that designed or
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`bought memories to develop physical, electrical and performance standards for a
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`wide variety of semiconductor memories. For the last two years of my tenure at
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`JEDEC JC-42, I chaired the Task Group on IC Operating Voltage Standards. We
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`developed standards for low-voltage (3.3V) operation and interface requirements
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`for memory and logic devices.
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`16.
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`In addition to my semiconductor industry experience, I am an
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`inventor on three U.S. patents that relate to semiconductor devices. Two of the
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`patents directly relate to semiconductor memory devices—in particular, DRAM
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`devices. I am also a Senior Member of the Institute of Electrical and Electronics
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`Engineers (IEEE) and have been a member for over 50 years. I am currently
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`registered as a Professional Engineer in Florida and North Carolina.
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`17. Additional information on my education, technical experience and
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`professional associations can be found in my curriculum vitae (attached as
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`Appendix A).
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`Obviousness Law
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`18.
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`I understand that a patent claim is invalid if the claimed invention
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`would have been obvious to a person of ordinary skill in the field at the time the
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`application was filed. This means that even if all of the requirements of the claim
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`cannot be found in a single prior art reference that would anticipate the claim, the
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`claim can still be invalid.
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`19.
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`As part of this inquiry, I have been asked to consider the level of
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`ordinary skill in the field that someone would have had at the time the claimed
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`invention was made. In deciding the level of ordinary skill, I considered the
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`following:
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`• the levels of education and experience of persons working in the field;
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`• the types of problems encountered in the field; and
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`• the sophistication of the technology.
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`20.
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`To obtain a patent, the claimed invention must have, as of the
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`priority date, been nonobvious in view of the prior art in the field. I understand that
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`an invention is obvious when the differences between the subject matter sought to
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`be patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time the invention was made to a person having ordinary skill
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`in the art.
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`21.
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`I understand that to prove that prior art or a combination of prior
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`art renders a patent obvious, it is necessary to: (1) identify the particular references
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`that, singly or in combination, make the patent obvious; (2) specifically identify
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`which elements of the patent claim appear in each of the asserted references; and
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`(3) explain how the prior art references could have been combined in order to
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`create the inventions claimed in the asserted claim.
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`22.
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`I understand that certain objective indicia can be important
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`evidence regarding whether a patent is obvious or nonobvious. Such indicia
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`include: commercial success of products covered by the patent claims; a long-felt
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`need for the invention; failed attempts by others to make the invention; copying of
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`the invention by others in the field; unexpected results achieved by the invention as
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`compared to the closest prior art; praise of the invention by the infringer or others
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`in the field; the taking of licenses under the patent by others; expressions of
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`surprise by experts and those skilled in the art at the making of the invention; and
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`the patentee proceeded contrary to the accepted wisdom of the prior art.
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`23.
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`Based on the technologies disclosed in the ’819 patent, a person
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`of ordinary skill in the art would have a Master of Science degree in Electrical
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`Engineering or an equivalent field, as well as at least 2 years of industry experience
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`designing semiconductor memories. Less education could be compensated by more
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`direct experience.
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`The ’819 Patent and Independent Claims 1, 7 and 17
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`24.
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`Before analyzing the differences between the Ogawa ’577, JP
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`’832 and Ogawa ’045 references and the ’819 patent, I would like to provide
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`insight on the technical challenges addressed by the ’819 patent and how these
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`challenges are addressed by the ’819 patent claims. This will help define certain
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`terms in the ’819 patent claims in view of its specification as well as what a person
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`of ordinary skill in the art would have understood during the 1994 timeframe (also
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`referred to herein as “the relevant timeframe”).
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`25.
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`The ’819 patent describes efficiently transferring data from and
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`to a memory array using the same bank of slave circuitry. This data transfer
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`operation contributes to the ongoing goal of improving speed and efficiency in
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`memory systems. During the 1994 timeframe, memory systems suffered from
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`inefficient accesses (read and write) to memory. For example, the ’819 patent
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`specification states that:
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` (Ex. 1001,’819 patent, 1:40-58.) As a result of the development of enhanced
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`operations such as BitBLT operations, “the need has arisen for improved circuits,
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`systems and methods for implementing bit block transfers. In particular, such
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`methods, systems and circuits should be applicable to the movement and/or
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`copying of pixel data within the frame buffer of a display system.” (Id., 2:43-48.)
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`The claimed invention of the ’819 patent addresses this need for
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`26.
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`efficient movement of data during the enhanced operations by providing a memory
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`system and method for data transfer using the same bank of slave circuitry. (See
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`Ex. 1001, ’819 patent, 4:21-36.) The memory system illustrated in FIG. 2 of the
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`’819 patent “advantageously provide[s] for efficient block moves/copies of data
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`within memory” by using the same bank of slave circuitry—e.g., slave sense
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`amplifiers bank 210. (Id., 7:41-42.)
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`27.
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`Throughout my declaration, I annotate various figures from the
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`’819 patent, Ogawa ’577 reference, JP ’832 reference and Ogawa ’045 reference.
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`These annotated figures are drafted based on the ’819 patent claims and visually
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`highlight the distinctions between the challenged claims and the applied references.
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`28.
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`For example, FIG. 1 below shows the memory system disclosed
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`in FIG. 2 of the ’819 patent with my annotations. In a row move operation, after a
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`master sense amplifier bank 208 senses data from a source row, “the data from the
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`source row is moved into a selected one of the slave sense amp banks 210 or 211.”
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`(Id., 7:55-57.) Next, after a row decoder 205 selects a destination row, “the data
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`stored in the selected slave sense amp 210 or 211 is driven onto local sense
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`amplifier bus 209, through master sense amplifiers 208 and into the memory cells
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`202 along the destination row.” (Id., 7:61-64.)
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`FIG. 1 (FIG. 2 of the ’819 Patent with Annotations)
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`The illustration above shows movement of data from memory
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`29.
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`array 203 to slave sense amplifier bank 210 (read operation) and copying of the
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`data from the same slave sense amplifier bank 210 to memory array 203 (write
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`operation). This operation of reading data from memory and writing data back to
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`memory is also referred to a “move/copy” operation. The above-described
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`move/copy operation can also be performed between memory array 203 and slave
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`sense amplifier bank 211. FIG. 2 below shows this operation. In FIGs. 1 and 2,
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`data moves from a memory array to a bank of slave circuitry—e.g., slave sense
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`amplifiers bank 210 or 211—and the data from the same bank of slave circuitry is
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`copied to the memory array.
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`FIG. 2 (FIG. 2 of the ’819 Patent with Annotations)
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`30.
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`The above distinguishing characteristics of the ’819 patent—
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`reading to and writing from the same bank of slave circuitry—are recited in
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`independent claims 1, 7 and 17. For example, claim 1 recites (emphasis added):
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`In claim 1, the “data” in the recited “control circuitry for controlling exchange of
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`data between said master read/write circuitry and said first and second slave
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`circuitry” is sensed, transferred to either the first or second slave circuitry and then
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`written to memory. The “control transfer of said data from said master read/write
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`circuitry to a selected one of said first and second slave circuitry” and “control
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`writing of said data through said master read/write circuitry” elements of claim 1
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`mean that data is read from the memory array to selected slave circuitry and the
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`data is written from the same slave circuitry to the memory array.
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`31.
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`Similarly, claim 7 recites (emphasis added):
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`In claim 7, the “data” is sensed, transferred to a selected bank of slave sense
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`amplifiers and then written to memory. The “control transfer of said data from said
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`master sense amplifiers to a selected one of said banks of slave sense amplifiers”
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`and “control writing of said data through said master sense amplifiers” elements of
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`claim 7 mean that data is read from the memory array to a selected bank slave
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`sense amplifiers and the data is written from the same bank of slave sense
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`amplifiers to the memory array.
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`32.
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`Further, claim 17 recites (emphasis added):
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`In claim 17, the “data” is sensed, transferred to (or latched into) a bank of slave
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`sense amplifiers and then written to memory. The latching and writing steps of
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`claim 17 require that data is read from the memory array to a bank of slave sense
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`amplifiers and the data is written from the same bank of slave sense amplifiers to
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`the memory array.
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`The Ogawa ’577 Reference
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`33.
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`The Ogawa ’577 reference discloses a data transfer operation that
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`uses multiple different alleged slave circuits. Unlike independent claims 1, 7 and
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`17 of the ’819 patent, the Ogawa ’577 reference discloses an additional write
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`operation from a slave circuit to a different alleged slave circuit prior to writing
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`data to the memory array.
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` (Ex. 1003, Ogawa ’577, 4:6-18, emphasis added.) FIG. 3 below pictorially depicts
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`Ogawa ’577’s data transfer operation. In the first step, data moves from a random
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`access memory 1 (RAM 1) to a shift register 3. Next, in the second step, the data in
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`shift register 3 moves (or is copied) to shift register 4. Lastly, in the third step, the
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`data in shift register 4 moves (or is copied) to RAM 1. Thus, Ogawa ’577 uses
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`different alleged slave circuits—i.e., shift registers 3 and 4—to read data from and
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`to write data to memory.
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`FIG. 3 (FIG. 2 of Ogawa ’577 with Annotations)
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`The JP ’832 Reference
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`34.
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`The JP ’832 reference discloses a nearly identical memory
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`system and data transfer operation as the Ogawa ’577 reference. Similar to the
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`Ogawa ’577 reference, the JP ’832 reference discloses a data transfer operation
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`using different alleged slave circuitry. The JP ’832 reference discloses an
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`additional write operation from a slave circuit to a different alleged slave circuit
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`prior to writing data to the memory array. The data transfer operation disclosed in
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`the JP ’832 reference uses different shift registers when reading data from and
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`writing data to memory.
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`(Ex. 1006, JP ’832, pp. 3-4, emphasis added.) FIG. 4 below pictorially depicts JP
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`’832’s data transfer operation. In the first step, data moves from a dynamic random
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`access memory 10 (DRAM 10) to a shift register SRA. Next, in the second step,
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`the data in shift register SRA moves (or is copied) to shift register SRB. Lastly, in
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`the third step, the data in shift register SRB moves (or is copied) to DRAM 10.
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`Thus, JP ’832 uses different alleged slave circuits—i.e., shift registers SRA and
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`SRB—to read data from and to write data to memory.
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`FIG. 4 (FIG. 1 of JP ’832 with Annotations)
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`The Ogawa ’045 Reference
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`35.
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`The Ogawa ’045 reference does not disclose a move/copy
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`operation. I note that Toshiba applies Ogawa ’045 to address a different aspect of
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`independent claims 1, 7 and 17 of the ’819 patent: “The Ogawa ’045 (TOSH-1005)
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`reference is cited for the proposition that in an earlier patent filed by the same
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`inventor, the inventor disclosed a similar invention in which a sense amplifier is
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`used to drive a pair of bitlines during a memory write operation.” (Paper 1,
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`Petition, pp. 10-11; see also id., pp. 24, 25, 32, 33, 50 and 51.) Toshiba does not
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`apply the Ogawa ’045 reference to address the move/copy operation recited in the
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`challenged claims.
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`36.
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`The Ogawa ’045 reference discloses an individual write
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`operation and an individual read operation. FIG. 5 below illustrates the write
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`operation of Ogawa ’045. During the write operation, shift register 1 receives data
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`serially bit-by-bit from a source external to random access memory (RAM). After
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`receiving eight bits, shift register 1 transfers its stored data to RAM.
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`FIG. 5 (Combined FIGs. 1A and 1B of Ogawa ’045 with Annotations)
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`FIG. 6 below illustrates the read operation of Ogawa ’045.
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`37.
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`During the read operation, shift register 1 receives data from the RAM. Shift
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`register 1 then transfers its stored data, in a serial manner, to a video display
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`external to the RAM.
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`FIG. 6 (Combined FIGs. 1A and 1B of Ogawa ’045 with Annotations)
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`38.
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`The Ogawa ’045 reference does not disclose transferring the data
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`from and to memory using the same slave circuit. It merely discloses individual
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`read and write operations, and does not disclose a move/copy operation at all much
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`less the move/copy operation recited in independent claims 1, 7 and 17 of the ’819
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`patent.
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`The Claimed Invention of the ’819 Patent Is Advantageous Over the Memory
`Systems and Data Transfer Methods Disclosed in the Ogawa ’577 and JP ’832
`References
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`39.
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`The advantages of the memory system and data transfer method
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`of the claimed invention over the memory systems and methods of Ogawa ’577
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`and JP ’832 include speed and efficiency. The move/copy operation of the claimed
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`invention is a streamlined process where data moves between a memory array and
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`the same slave circuit. In contrast, the data transfer operations disclosed in the
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`Ogawa ’577 and JP ’832 references move data to multiple alleged slave circuits
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`prior to writing data back to the memory array.
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`40.
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`As described above, the move/copy operation of the claimed
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`invention is a two-step process using the same slave circuitry: (1) move (or read)
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`data from a memory array to slave circuitry; and (2) copy (or write) the data stored
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`in the same slave circuitry to the memory array. On the other hand, each of the
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`Ogawa ’577 and JP ’832 references discloses a three-step data transfer operation
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`using different alleged slave circuitry: (1) move (or read) data from a memory
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`array to slave circuitry; (2) move the data from the slave circuitry to different
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`alleged slave circuitry; and (3) write the data in the different alleged slave circuitry
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`U.S. Patent 5,500,819
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`to the memory array. FIG. 7 below illustrates the differences between the
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`move/copy of the claimed invention and the data transfer operations of the Ogawa
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`’577 and JP ’832 references—i.e., the claimed invention is a two-step process,
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`whereas Ogawa ’577 and JP ’832 disclose a three-step process.
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`FIG. 7 (Comparison of Data Transfer Operations Between the ’819 Patent,
`Ogawa ’577 and JP ’832)
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`41.
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`Unlike the memory systems and data transfer methods disclosed
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`in the Ogawa ’577 and JP ’832 references, the memory system and data transfer
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`method of the claimed invention provide a faster and more efficient data transfer
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`operation since it does not require data transfers to multiple slave circuits. In turn,
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`this memory system and data transfer method support the ongoing goal of
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`improving access to memory.
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`Claim Construction
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`42.
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`I understand that, for expired patents such as the ’819 patent,
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`claims terms are given their ordinary and customary meaning as understood by a
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`person of ordinary skill in the art at the time of the invention. I also understand that
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`the intrinsic record of the ’819 patent—e.g., claims, specification and prosecution
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`history—is the primary source for determining claim meaning.
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`Technical Comparison Between the ’819 Patent Claims and the Applied
`References
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`43. My analysis focuses on the distinctions between independent
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`claims 1, 7 and 17 of the ’819 patent and the Ogawa ’577, JP ’832 and Ogawa ’045
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`references. A key distinction between the claimed invention and the applied
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`references is that the claimed invention discloses a move/copy operation that
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`moves (or reads) data to slave circuitry and then copies (or writes) the data to
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`memory using the same slave circuitry. The applied references do not disclose this.
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`Rather, as discussed above, the memory systems and methods disclosed in Ogawa
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`’577 and JP ’832 transfer data from and to memory using different alleged slave
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`circuitry. Further, the memory system disclosed in Ogawa ’045 does not cure the
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`deficiencies of the Ogawa ’577 and JP ’832 references since it does not disclose
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`the move/copy operation recited in the challenged claims.
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`Independent Claims 1, 7 and 11 Require Transferring Data from and to
`Memory Using the Same Slave Circuit.
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`44.
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`As discussed above, independent claims 1, 7 and 17 require the
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`transfer of the data from and to memory using the same slave circuit. On the other
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`hand, Toshiba interprets these claims to require the transfer of data from and to
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`memory using different slave circuits, as disclosed in the Ogawa ’577 and JP ’832
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`references. This is counter to the plain and ordinary meaning of the claims.
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`45.
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`For example, based on their plain and ordinary meaning, the
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`latching and writing steps of claim 17 require that the data stored in the bank of
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`slave sense amplifiers—the same bank of slave sense amplifiers receiving the data
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`from the memory array—be written to the memory array. This interpretation is
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`supported by the ’819 patent specification.
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`(Ex. 1001, ’819 patent, 7:51-66, emphasis added.)
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`46.
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` Claims 1 and 7 recite similar distinguishing elements. For
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`example, claim 1 recites: “control transfer of said data from said master read/write
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`circuitry to a selected one of said first and second slave circuitry”; and “control
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`writing of said data through said master read/write circuitry to a second said row in
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`said array selected by said addressing circuitry.” Claim 7 recites: “control transfer
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`of said data from said master sense amplifiers to a selected one of said banks of
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`slave sense amplifiers”; and “control writing of said data through said master sense
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`amplifiers to a second said row in said array selected [by] said row decoder.”
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`47.
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`The Ogawa ’577, JP ’832 and Ogawa ’045 references do not
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`disclose these elements of claims 1, 7 and 17.
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`The Ogawa ’577 Reference
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`U.S. Patent 5,500,819
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`48.
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`As discussed above, the data transfer operation disclosed in
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`Ogawa ’577 transfers data using different alleged slave circuits. FIG. 3 below
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`pictorially depicts Ogawa ’577’s data transfer operation. In the first step, data
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`moves from a random access memory 1 (RAM 1) to a shift register 3. Next, in the
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`second step, the data in shift register 3 moves (or is copied) to shift register 4.
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`Lastly, in the third step, the data in shift register 4 moves (or is copied) to RAM 1.
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`Thus, Ogawa ’577 uses different alleged slave circuits—i.e., shift registers 3 and
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`4—to read data from and to write data to memory.
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`FIG. 3 (FIG. 2 of Ogawa ’577 with Annotations)
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`In its petition, Toshiba describes Ogawa ’577’s data transfer
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`49.
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`operation in a similar manner. In referring to FIG. 2 of Ogawa ‘577, Toshiba
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`states:
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`(Paper 1, Petition, p. 19.) Toshiba characterizes shift registers 3 and 4 of Ogawa
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`’577 as different alleged slave circuits:
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` (Id., p. 30, emphasis added.) Further, Toshiba states:
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`(Paper 1, Petition, pp. 30-31, emphasis added.) Toshiba thus recognizes that shift
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`registers 3 and 4 are separate and independent banks of slave circuitry—e.g., “first
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`and second slave circuitry”—used in the data transfer operation of Ogawa ’577.
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`50.
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`In view of the above, Toshiba characterizes Ogawa ’577’s data
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`transfer operation as using two different alleged slave circuits— i.e., shift registers
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`3 and 4—to read data from and write data to memory. The Ogawa ’577 reference
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`thus does not disclose the data transfer operation of independent claims 1, 7 and 17
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`of the ’819 patent.
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`The JP ’832 Reference
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`Case IPR2014-00418
`U.S. Patent 5,500,819
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`51.
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`As discussed above, the data transfer operation disclosed in JP
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`’832 is nearly identical to the data transfer operation disclosed in Ogawa ’577.
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`Like Ogawa ’577, the JP ’832 reference describes a data transfer operation using
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`different shift registers when reading data from and writing data to memory. FIG.
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`4 below pictorially depicts JP ’832’s data transfer operation. In the first step, data
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`moves from a dynamic random access memory 10 (DRAM 10) to a shift register
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`SRA. Next, in the second step, the data in shift register SRA moves (or is copied)
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`to shift register SRB. Lastly, in the third step, the data in shift register SRB moves
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`(or is copied) to DRAM 10. Thus, JP ’832 uses different alleged slave circuits—
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`i.e., shift registers SRA and SRB—to read data from and to write data to memory.
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`FIG. 4 (FIG. 1 of JP ’832 with Annotations)
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`52.
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`In its petition, Toshiba describes JP ’832’s data transfer operation
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`in a similar manner. In referring to FIG. 1 of JP ’832, Toshiba states:
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`(Paper 1, Petition, p. 44.) Toshiba characterizes shift registers SRA and SRB as
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`different alleged slave circuits:
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` (Id., p. 40, emphasis added.) Toshiba thus recognizes that shift registers SRA and
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`SRB are separate and independent banks of slave circuitry—e.g., “banks of ‘slave
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`sense amplifiers’”—used in the data transfer operation of JP ’832.
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`53.
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`In view of the above, Toshiba characterizes JP ’832’s data
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`transfer operation as using two different alleged slave circuits— i.e., shift registers
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`SRA and SRB—to read data from and write data to memory. The JP ’832
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`reference thus does not disclose the move/copy operation of independent claims 1,
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`7 and 17 of the ’819 patent.
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`The Ogawa ’045 Reference
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`54.
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`As discussed above, the Ogawa ’045 reference does not disclose
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`the move/copy operation of independent claims 1, 7 and 17 of the ’819 patent, and
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`indeed does not disclose a move/copy operation at all. Toshiba applies Ogawa ’045
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`to address a different aspect of claims 1, 7 and 17: “The Ogawa ’045 (TOSH-1005)
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`reference is cited for the proposition that in an earlier patent filed by the same
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`inventor, the inventor disclosed a similar invention in which a sense amplifier is
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`used to drive a pair of bitlines during a memory write operation.” (Paper 1,
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`Petition, pp. 10-11; see also id., pp. 24, 25, 32, 33, 50 and 51.) Toshiba does not
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`apply the Ogawa ’045 reference to address the move/copy operation recited in the
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`challenged claims. Nor does it disclose this feature.
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`55.
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`Instead, as described above, Ogawa ’045 merely discloses
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`individual write operations and individual read operations. FIG. 5 below illustrates
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`the write operation of Ogawa ’045. During the write operation, shift register 1
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`receives data serially bit-by-bit from a source external to random access memory
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`(RAM). After receiving eight bits, shift register 1 transfers its stored data to RAM.
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`FIG. 5 (Combined FIGs. 1A and 1B of Ogawa ’045 with Annotations)
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`FIG. 6 below illustrates the read operation of Ogawa ’045.
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`56.
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`During the read operation, shift register 1 receives data from the RAM. Shift
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`register 1 then transfers its stored data, in a serial manner, to a video display
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`external to the RAM.
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`FIG. 6 (Combined FIGs. 1A and 1B of Ogawa ’045 with Annotations)
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`57.
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`The Ogawa ’045 reference only discloses individual reads and
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`writes, and does not disclose a move/copy operation. Thus, the Ogawa ’045
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`reference does not disclose the move/copy ope
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