`
`National
`Semiconductor
`
`PRELIMINARY
`December 1988
`
`COP620C/COP621C/COP622C/COP640C/COP641C/
`
`COP642C/COP820C/COP821C/COP822C/COP840C/
`COP841C/COP842C Single-Chip microCMOS
`
`General Description
`The COPSZOC and COP84OC are members of the COPSTM
`microcontroiler family. They are fully static parts. fabricated
`using double-metal silicon gate microCMOS technology.
`This low cost microcontroiler is a complete microcomputer
`containing all system timing, interrupt logic. ROM, RAM, and
`l/O necessary to implement dedicated control functions in a
`variety of applications. Features include an 8-bit memory
`mapped architecture, MICROWIFlE/PLUSTM serial
`l/O, a
`16-bit
`timer/counter with capture register and a multi-
`sourced interrupt. Each l/O pin has software selectable op-
`tions to adapt the COPBZOC and COPBAOC to the specific
`application. The part operates over a voltage range of 2.5 to
`6.0V. High throughput is achieved with an efficient. regular
`instruction set operating at a 1 microsecond per instruction
`rate. The part may be operated in the ROMIess mode to
`provide for accurate emulation and for applications requiring
`external program memory.
`
`Features
`I Low Cost 8-bit microcontroiler
`
`16-bit read/write timer operates in a variety of modes
`—Timer with 16-bit auto reload register
`——16—bit external event counter
`—Timer with 16—bit capture register (selectable edge)
`Multi-source interrupt
`—— Reset master clear
`—- External interrupt with selectable edge
`— Timer interrupt or capture interrupt
`— Software interrupt
`8-bit stack pointer (stack in RAM)
`Powerful instruction set, most instructions single byte
`BCD arithmetic instructions
`MICROWIRE PLUSTM serial I/O
`28 pin package (optionally 24 or 20 pin package)
`24 input/output pins (28-pin package)
`Software selectable l/O options (TRl-STATE®, push-
`pull, weak pull-up)
`Schmitt trigger inputs on Port G
`Temperature ranges: 440°C to +85°C.
`+125°C
`ROMIess mode for accurate emulation and external
`program capability—expandable to 32k bytes in ROM-
`I FUIIY static CMOS
`less mode
`I 1 its instruction time (20 MHz clock)
`I Form.
`fit and function EEPFtOM emulation device
`I Low current drain (2.2 mA at 3 its instruction rate)
`(COP87200)
`Low current static HALT mode (Typically < 1 HA)
`I Piggyback emulation devices (COPBZOCP/COPBAOCP)
`l Single supply operation: 2.5 to 6.0V
`Fuily supported by National‘s MOLETM development
`1024 bytes ROM/64 Bytes RAM—COPBZOC
`system
`l 2048 bytes ROM/128 Bytes RAM—COP84OC
`
`— 55°C to
`
`Block Diagram
`
`CKI W VCC
`
`GND
`
`
`
`SJaIIOJIU030-IOIWSOINOOJOIWd!l-IC)'3|5U!SOZVBdOO/OIVBdOO/OOVBdOO/OZZBdOO
`
`
`
`
`
`
`
`l3LZBdOO/OOZBdOO/OZI’QdOO/OWQdOO/OOVQdOO/OZZQdOO/OLZQdOO/OOZQdOO
`
`
`
` Microcontrollers
`
`
`
`PROS. COUNTER
`
`
`
`
`
`CLOCK
`
`HALT
`
`ADDRESS
`
`1
`
`
` INSTRUCTiON
`
`DECODER
`
`Iw
`
`e
`
`1 J
`
`3
`PfVTL
`
`ill
`
`I E-BIT
`
`INTERRUPT
`TiMER/COUNTER
`WiTH AUTOLOAD
`(TIMER a
`
`EXTERNAL)
`
`& CAP'URE REG
`
`
`INPUTS
`
`uicrwwmr
`PLUS
`
`1PORT G
`
`POW D
`
`UPORTi
`
`Ti /DD/9103—i
`
`FIGURE 1
`COPS'M‘ HPCTM. MICROWIREW MiCROWIFE/PLUSW arid MOLE'“ are Irade 'iarks oi Natioriai Semiconductor Corporation
`TFtl STATEi
`is a registered trademark at National Semiconductor Corporation
`
`RRUBZOMIER Frinlediri t; S A
`
`9' HIGH Nalloriai Semiconductor Corporation
`
`TL/DD/QIWTJ
`
`#3
`
`Pet'r Exhibit 1020
`
`Continental V. Wasica
`
`5
`IPR2014-00295
`Page 000001
`
`

`

`
`
`COP8206/COP821C/COP822C/COP84OC/COP841C/COP8420
`Absolute Maximum Ratings
`If Military/Aerospace specified devices are required,
`please contact
`the National Semiconductor Sales
`Office/Distributors for availability and specifications.
`Suppiy Voltage (VCC)
`7V
`Voltage at any pin
`—O.3Vto Vcc t 0.3V
`ESD Susceptibility (Note 4)
`2000V
`Total Current into VCC Pin (Source)
`50 mA
`DC Electrical Characteristics 740°C 3 TA g +85°C unless otherwise specified
`
`Parameter
`Condition
`Min
`#—
`
`60 mA
`Total Current out of GND Pin (Sink)
`— 65°C to +140°C
`Storage Temperature Range
`Note: Absolute maximum ratings indicate limits beyond
`which damage to the device may occur. 00 and AC electri-
`.
`.
`.
`.
`cal spectfications are not ensured when operating the de-
`vice at absolute maximum ratings.
`
`Operating Voltage
`2.5
`
`Power Supply Ripple (Note 1)
`Peak to Peai;
`Supply Current
`High Speed Mode, CKI : 20 MHz
`Normal Mode, CKI = 5 MHz
`Normal Mode. CKI = 2 MHz
`(Note 2)
`HALT Current
`V00 : 6V, C Kl : 0 MHz
`
`(Note 3)
`input Levels
`RESET, CKI
`Logic High
`Logic Low
`All Other inputs
`Logic High
`Logic Low
`Hi-Z input Leakage
`VCC = 6.0V VIN = 0V
`—2
`pA
`
`Input Puilup Current
`Vcc : 6.0V. VIN 7 0V
`40
`250
`HA
`
`G Port Input Hysteresis
`0.05 VCC
`V
`Output Current Levels
`D Outputs
`Source
`
`VCC = 6V, to = 1 its
`Vcc = 6V, to = 2 its
`Vcc = 2.5V tc = 5 MS
`
`09 V00
`
`0.7 Vcc
`
`0.4
`0.2
`10
`2
`
`VCC 2 4.5V VOH : 3.8V
`Vcc : 2.5V VOH : 1.8V
`Vcc = 4.5V VOL = 1.0V
`VCC = 2,5V VOL : 0.4V
`
`10
`VCC = 4.5V VOH : 3.2V
`2.5
`Vcc = 2.5V VOH = 1.3V
`0.4
`Vcc 2 4.5V VOH : 3.8V
`0.2
`Vcc = 2.5V VOH = 1.8V
`Sink(Push-Puii Mode)
`VCC = 405V. VOL = 0.4V
`1.6
`mA
`VCC : 2.5V. VOL : 0.4V
`0.7
`
`TRi-STATE Leakage
`72.0
`+ 20
`uA
`Allowable Sink/Source
`Current Per Pin
`D Outputs (Sink)
`15
`mA
`
`AiiOthers
`L
`3
`mA
`Maximum Input Current (Note 5)
`
`Without Latchup (Room Temp)
`Room Temp
`: 100
`mA
`RAM Retention Voltage, Vt
`500 ns Rise and
`
`Fall Time (Min)
`20
`V
`pF
`7
`Input Capacitance
`
`Load Capacitance on D2
`1000
`pF
`Note 1: Rate ol voltage change must be less than 0.5V/ms
`Note 2: Supply current is measured after running 2000 cycles With a square wave CKI input. CKO open. inpms at rails and outputs open.
`Note 3: The HALT mode wtll stop CKi lrom oscillating in the RC and tre Crystal configurations. Test conditions: All inputs tied to Vcc, L and G ports TRi-STATED
`and tied to ground. all outputs low and tied to ground.
`Note 4: Human body mode. 100 pF through 15001).
`Note 5: Except pins 3. 4, 24
`pins 3, 24
`+60 mA, 7100 mA
`pin4
`+100 mA, -25mA
`Sampled but not 100% tested.
`
`
`Sink
`All Others
`Source (Weak Pull-Up)
`
`Source (Push-Pull Mode)
`
`
`
`
`
`
`
`
`
`
`
`
`
`mA
`mA
`mA
`mA
`
`110
`33
`
`uA
`uA
`mA
`
`Page 000002
`
`

`

`
`
`
`
`COP820C/COP821C/COP822C/COP84OC/COP841C/COP842C
`AC Electrical Characteristics 7 40“C < TA < +85°C unless otherwise specified
`
` Parameter Condition
`Instruction Cycle Time (to)
`VCC x 4.5V
`High Speed Mode
`2.5V 3 Vcc < 4.5V
`(Div-by 20)
`VCC ;: 4.5V
`Normal Mode
`2.5V ; VCC < 4.5V
`(Div-by 10)
`VCC _. 4.5V
`R/C Oscillator Mode
`
`(Div-by 10) 2.5V ; vcc < 4.5V
`
`fr : Max ( :- 20 Mode)
`CKI Clock Duty Cycle (Note 6)
`tr = 20 MHz Ext CIock
`Rise Time (Note 6)
`tr 2 20 MHz Ext Clock
`Fall Time (Note 6)
`Inputs
`tSETUP
`
`
`
`VCC ;» 4.5V
`2.5V ; VCC < 4.5V
`tHOLD
`VCC t: 4.5V
`25V 3 VCC < 4.5V
`CL : 100 pF, RL = 2,2 kn
`Output Propagation Delay
`tPm. tPoo
`80, SK
`
`VCC .: 4.5V
`2.5V 3 VCC < 4.5V
`VCC L: 4.5V
`
`2.5V S VCC < 4.5V
`
`
`
`All Others
`
`CKI Clock Duty Clock
`Rise Time
`Fall Time
`Inputs
`tSETUP
`
`tHOLD
`
`Output Propagation Delay
`IP01, tPDo
`30, SK
`
`
`
`
`
`
`
`
`
`
`
`MICROWlRETM Setup Time (iuws)
`MICROWIRE Hold Time (iUWH)
`MICROWIRE Output
`
`Propagation Delay (tUpD)
`Input Pulse Width
`Interrupt Input High Time
`Interrupt Input Low Time
`Timer Input High Time
`Timer Input Low Time
`
`Reset Pulse Width
`Note 6: Parameter sampled but not 100% tested.
`AC Electrical Characteristics in ROMless Mode —40°C < TA < 85°C unless otherwise specified
`
`Parameter
`Condition
`Min
`Units
`Instruction Cycle Time (to)
`High Speed Mode
`(Div-by 20)
`Normal Mode
`(Div-by 10)
`R/C Oscillator Mode
`
`V00 2 4.5V
`2.5V 3 VCC < 4.5V
`VCC 2 4.5V
`2.5V 5 VCC < 4.5V
`V00 2 4.5V
`2.5V 3 vCC < 4.5V
`fr 2 Max (+ 20 Mode)
`fr : 10 MHz Ext Clock
`fr : 10 MHz Ext Clock
`
`40
`
`#3
`ps
`HS
`its
`[1.8
`MS
`%
`ns
`ns
`
`VCC 2 4.5V
`2.5V 3 Vcc < 4.5V
`Vcc 2 4.5V
`2.5V 3 VCC < 4.5V
`CL = 100 pF, FIL : 2.2 kn
`
`400
`800
`120
`300
`
`ns
`ns
`ns
`ns
`
`[.LS
`1.4
`VCC 2 4.5V
`2.5V 3 vcc < 4.5V
`3.5
`tLS
`All Others
`VCC 2 4.5V
`2
`us
`
`2.5V g vCC < 4.5V
`5
`”5
`Minimum Pulse Width
`Interrupt Input
`to
`
`Timer Input
`tc
`“S
`Reset Pulse Width
`1.0
`
`
`Page 000003
`
`

`

`
`
`COP620C/COP621C/COP622C/COP64OC/COP641C/COP642C
`
`Absolute Maximum Ratings
`If Military/Aerospace specltled devices are required,
`please contact
`the National Semiconductor Sales
`Office/Distributors for availability and specifications.
`SUDP'Y Voltage (VCC)
`5V
`Voltage at any Pin
`—0.3V to VCC + 0.3V
`ESD Susceptibility (Note 4)
`zoom]
`Total Current into VCC Pin (Source)
`40 mA
`
`48 mA
`Total Current out of GND Pin (Sink)
`—65°C to + 140°C
`Storage Temperature Range
`Note: Absolute maximum ratings indicate limits beyond
`which damage to the device may occur. DC and AC electri-
`cal specifications are not ensured when operating the de-
`Vice at absolute maximum ratings.
`
`DC Electrical Characteristics essoc g TA g + 125°C unless otherwise speciiied
`
`Ilmlllllllllnfll mm
`5.5
`V
`0.1 VCC
`V
`
`VCC = 5.5V, to = 1.1 us
`V00 : 5.5V, to = 2.2 [—1.5
`
`15
`5
`
`Vcc = 5.5V, CKI : 0 MHz
`<10
`30
`pA
`
`
`
`
`
`
`
`
`
`nwmm
`cme
`
`Operating Voltage
`
`Power Supply Ripple (Note 1)
`Peak to Peak
`
`Supply Current
`
`
`High Speed Mode, CKI = 18 MHz
`Normal Mode. CKI = 4.5 MHz
`
`(Note 2)
`HALT Current
`
`(Note 3)
`
`Input Levels
`
`RESET, CKI
`Logic High
`
`Logic Low
`
`All Other Inputs
`
`Logic High
`Logic Low
`
`Hin Input Leakage
`Vcc = 5.5V, VlN = 0V
`
`Input Pullup Current
`VCC = 4.5V, VIN : CV
`
`
`G Port Input Hysteresis
`
`
`Output Current Levels
`D Outputs
`Source
`Sink
`All Others
`VCC = 4.5V, VOH : 3.2V
`Source (Weak Pull-Up)
`Source (Push-Pull Mode)
`VCC = 4.5V, VOH = 3.8V
`Sink (Push-Pull Mode)
`Vcc = 4.5V, VOL = 0.4V
`
`TRI-STATE Leakage
`Allowable Sink/Source
`Current Per Pin
`D Outputs (Sink)
`All Others
`Maximum Input Current (Room Temp)
`Without Latchup (Note 5)
`RAM Retention Voltage, Vr
`
`VCC = 4.5V, VOH = 3.8V
`Vcc = 4.5V, VOL : 1.0V
`
`
`
`
`
`Room Temp
`500 ns Rise and
`Fall Time (Min)
`
`
`
`
`
`
`
`mA
`mA
`
`V
`V
`
`V
`V
`pA
`pA
`V
`
`mA
`mA
`
`pA
`mA
`mA
`pA
`
`mA
`mA
`
`mA
`
`V
`
`0.9 Vcc
`
`0.7 Vcc
`
`—5
`35
`
`0.35
`9
`
`9
`0.35
`1.4
`75.0
`
`2.5
`
`0.05 Vcc
`
`0.1 VCC
`
`0.2 Vcc
`+5
`300
`
`120
`
`+ 5.0
`
`12
`2.5
`
`i 100
`
`InputCapacnance
`
`__— pF
`
`Note 1: Rate of voltage change must be less than 0.5V/ms.
`Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
`Note 3: The HALT mode w1l| stop CKI lrom oscillating In the RC and the CrystaI configurations. Test conditions All inputs tied to Vccr L and G ports TRl-STATE
`and tied to ground, all outputs low and tied to ground.
`Note 4: Human body mode, 100 pF through 1500c,
`Note 5: Except pins 3. 4, 24
`pins 3, 24:
`+60 mA. — 100 mA
`pin 4:
`+100. —25 mA
`Sampled but not 100% tested.
`
`
`
`Page 000004
`
`

`

`
`
`COP620C/COP621C/COP622C/COP640C/COP641C/COP642C
`
`AC Electrical Characteristics — 55°C < TA < + 125°C unless otherwuse specified
`
`Parameter
`Condition
`Min
`Typ
`J_Max
`Units
`Instruction Cycle Time (to)
`High Speed Mode
`V00 2 4.5V
`1.1
`DC
`ps
`(Div-by 20)
`Normal Mode
`VCC 2 45V
`2.2
`DC
`MS
`
`(Div-by 10)
`CKI Clock Duty Cycle
`(Note 6)
`Rise Time (Note 6)
`fr = 18 MHz Ext Clock
`12
`ns
`
`Fall Time (Note 6)
`fr = 18 MHz Ext Clock
`8
`ns
`Inputs
`ISETUF’
`[HOLD
`Output Propagation Delay
`tPDl- IPDo
`30, SK
`All Others
`MICROWIRE Setup Time (tUWS)
`MICROWIRE Hold Time (lUWH)
`MICROWIRE Output Valid
`Time (tUV)
`Input Pulse Width
`to
`Interrupt Input High Time
`Interrupt Input Low Time
`tC
`Timer Input High Time
`to
`
`Timer Input Low Time
`to
`_
`1
`Reset Pulse Width
`1
`ps
`Note 6: Parameter sampled but not 100% tested.
`
`fr : Max (+ 20 Mode)
`
`33
`
`Vcc 2 4.5V
`220
`
`VCC 2 4.5V
`66
`RL : .Zrzk, CL = 100 pF
`
`V00 2 4.5V
`VCC 2 4.5V
`
`20
`56
`
`
`
`
`
`
`
`
`
`
`
`66
`
`0.8
`1.1
`
`220
`
`%
`
`ns
`ns
`
`us
`ps
`ns
`ns
`n
`
`5
`
`
`
`
`AC Electrical Characteristics in ROMIess Mode —55“C < TA < + 125°C unless otherwise specified
`Parameter
`Condition
`
`
`Instruction Cycle Time (tc)
`High Speed Mode
`VCC 2 45V
`
`(Div-by 20)
`Normal Mode
`V00 2 4.5V
`
`(Div-by 10)
`CKI Clock Duty Clock
`lr : Max( ~ 20 Mode)
`Rise Time
`Ir = 9 MHz Ext Clock
`
`Fall Time
`Ir = 9 MHZ Ext Clock
`Inputs
`tSETUP
`Vcc 2 4-5\"
`
`Mom)
`VCC 2 4.5V
`Output Propagation Delay
`RL : 2.2K, CL = 100 pF
`tPDlr tPDo
`SO, SK
`All Others
`Minimum Pulse Width
`Interrupt Input
`Timer Input
`Reset Pulse Width
`
`Vcc 2 45V
`VCC 2 4.5V
`
`
`
`Page 000005
`
`

`

`
`
`Timing Diagrams
`
`(+2ouooc)
`
`CKI
`(+10 MODE)
`
`I
`
`I1 (XLD)
`
`I2 (PHi)
`
`D0. 01, 03
`
`I
`
`I
`”I tPm
`
`I
`4 tPoo
`
`it
`
`I
`
`I
`
`I
`
`I
`
`I
`
`/Ifi*I {FD I”
`
`1
`
`/
`‘Pm r
`/
`
`—>I
`
`‘Ii
`
`P00 ‘-
`
`\
`
`/
`<—
`
`\
`
`—>1‘PDO
`'snup
`
`
`
`\
`
`1
`
`How
`
`TL/DD/9103—2
`
`FIGURE 2a. AC Timing Diagrams in ROMless Mode
`
`SI
`
`FIGURE 2b. MlCROWIRE/PLUS Timing
`
`TL/DD/9103—19
`
`
`
`
`
`
`
`Page 000006
`
`

`

`
`
`Connection Diagrams
`DUAL-lN-LINE PACKAGE
`
`20 DIP
`
`28 DIP
`
`
`
`cs/no
`62
`c1
`00/1141
`
`W6
`
`ND
`03
`02
`n1
`
`8L
`
`7
`L6
`L5
`L4
`
`123456789
`
`umN#
`
`64/50
`cs/sx
`GE/SI
`c7/cxo
`CKI
`VCC
`| 0
`| 1
`| Z
`| 3
`L0
`L1
`L2
`L3
`
`TL/DD/9103—5
`Order Number COPBZOC-XXX/D,
`copazoc-xxxm, COP84OC-XXX/ D
`or COP840C-XXX/N
`See NS Package Number
`028C or N288
`
`Gs/no
`27 23
`
`04/50
`1
`
`GS/SK
`2
`
`GG/Sl
`3
`
`c7/cxo
`4
`
`GO/INT
`fir
`sun
`D3
`
`DO
`
`10
`11
`
`15141312
`
`oz D1
`
`33233::
`TL/DD/QiOfl—IB
`Order Number COPGZOC-XXX/V or
`COPB4OC-XXX/V
`See NS Package Number V28A
`
`04/50
`cs/sx
`GG/Si
`o7/cxo
`cm
`vcc
`L0
`L1
`L2
`
`L3
`
`cs/no
`62
`GI
`GO/iNT
`W
`6ND
`L7
`L6
`L5
`L4
`
`TL/DD/mos—a
`
`Top View
`Order Number COPBZZC-XXX/D,
`COP822C-XXX/N, COP8420-XXX/D
`or COP842C-XXX/ N
`See NS Package Number
`D20A or N20A
`
`Gt/so
`GS/SK
`GS/SI
`G7/CKO
`CKi
`VCC
`10
`I 3
`L0
`L1
`L2
`L3
`
`L4
`
`63/110
`62
`GI
`(so/mt
`RESET
`GND
`03
`
`L7
`L6
`L5
`
`TL/DD/91DGJ
`Order Number COP821C-XXX/D,
`COP821c-XXX/N, COP841c-XXX/D
`or COP841C-XXXIN
`See Ns Package Number
`D240 or N24A
`
`SURFACE MOUNT
`
`20 50 Wide
`
`24 50 Wide
`
`04/50
`GS/SK
`GG/SI
`c7/cxo
`cm
`vcc
`L0
`L1
`L2
`
`L5
`
`63/110
`GI
`c1
`GO/iNT
`aw
`em:
`L7
`L6
`L5
`L4
`
`TL/DD/QI 03—3
`
`Top View
`Order Number COP822C-XXX/WM
`or COP84zc-xxX/WM
`See NS Package Number M203
`
`04/30
`GS/SK
`36/51
`G7/CKO
`CKi
`VCC
`I 0
`I 3
`L0
`L1
`L2
`L3
`
`os/‘no
`62
`GI
`GO/INY
`WT
`GND
`03
`
`L7
`L6
`L5
`
`L4
`
`TL/DD/91OG—4
`Order Number COP821C-XXX/WM
`or COP841C-XXXIWM
`See NS Package Number M248
`
`
`
`
`COP822C
`COP842C
`
`COP821C
`COP841C
`
`COP820C
`COP840C
`
`V“ PORT L MGND
`
`CKI
`
`REE?
`
`W“ G N INYR
`CKO
`MICROWIRE/PLUS
`TL/DD/9103—6
`
`
`
`INYR
`0K0
`MICROWIRE/PLUS
`TL/DD/9103—7
`
`FIGURE 3
`
`
`
`iNTR
`CKO
`MICROWIRE/PLUS
`TL/DD/QlOS—a
`
`
`
`Page 000007
`
`

`

`
`
`PhtDescfipfions
`Vcc and GND are the power supply pins.
`CKI
`is the clock input. This can come from an external
`source, a R/C generated oscillator or a crystal (in conjunc-
`tion with CKO). See Oscillator description.
`RESET is the master reset input. See Reset descriptior.
`PORT | is a four bit Hi»Z input port.
`PORT L is an 8—bit l/O port.
`There are two registers associated with each L l/O port: a
`data register and a configuration register. Therefore, each L
`l/O bit can be individually configured under software control
`as shown below:
`Port L
`
`
`Setup
`
`Hi-Z input (TRl-STATE)
`
`input With Weak Pull-Up
`Push-Pull ”0” Output
`
`Push-Pull “1 ” Output
`
`Three data memory address locations are allocated for
`these ports, one for data register, one for configuration reg-
`ister and one for the input pins.
`PORT G is an 8-bit port with 6 HO pins (GO—G5) and 2 input
`pins (G6, G7). All eight G-pins have Schmitt Triggers on the
`inputs. The G7 pin functions as an input pin under normal
`operation and as the continue pin to exit the HALT mode.
`There are two registers with each l/O port: a data register
`and a configuration register. Therefore, each I/O bit can be
`indiVidually configured under software control as shown be-
`ow.
`
`Port 6
`Port G
`Port G
`
`Config.
`Data
`Setup
`0
`o
`Hi-Z Input (TRI»STATE)
`1
`input With Weak Pull-Up
`0
`Push-Pull “0” Output
`1
`Push-Pull “1 ” Output
`
`
`
`1
`1
`
`Three data memory address locations are allocated for
`these ports, one for data register, one for configuration reg-
`ister and one for the input pins. Since G6 and G7 are input
`only pins, any attempt by the user to set them up as outputs
`by writing a one to the configuration register will be disre-
`garded. Reading the GG and G7 configuration bits will return
`zeros. Note that the chip will be placed in the HALT mode
`by setting the G7 data bit.
`Six bits of Port G have alternate features:
`G0 lNTR (an external interrupt)
`G3 TIO (timer/counter input/output)
`G4 80 (MiCROWIRE serial data output)
`G5 SK (MiCROWlRE clock l/O)
`GS Si (MICROWIRE serial data input)
`G7 CKO crystal oscillator output (selected by mask option)
`or HALT restart input (general purpose input)
`Pins G1 and G2 currently do not have any alternate lunc-
`tions.
`
`logical or
`
`FuncfionalDescflpfion
`Figure I shows the block diagram of the internal architec-
`ture. Data paths are illustrated in simplified form to depict
`how the various logic elements communicate with each oth-
`er in implementing the instruction set of the device.
`ALU AND CPU REGISTERS
`The ALU can do an 8-bit addition, subtraction,
`shift operation in one cycle time.
`There are five CPU registers:
`A is the 15-bit Program Counter register
`PU is the upper 7 bits of the program counter (PC)
`PL is the lower 8 bits of the program counter (PC)
`B is the 8-bit address register, can be auto incremented or
`decremented.
`X is the 8-bit alternate address register, can be incremented
`or decremented.
`SP is the 8—bit stack pointer, points to subroutine stack (in
`RAM).
`B, X and SP registers are mapped into the on chip RAM.
`The B and X registers are used to address the on chip RAM.
`The SP register is used to address the stack in RAM during
`subroutine calls and returns.
`PROGRAM MEMORY
`Program memory for the COPBZOC consists of 1024 bytes
`of ROM (2048 bytes of ROM for the COP840C). These
`bytes may hold program instructions or constant data. The
`program memory is addressed by the 15-bit program coun-
`ter (PC). ROM can be indirectly read by the LAID instruction
`for table lookup.
`DATA MEMORY
`The data memory address space includes on chip RAM, HO
`and registers. Data memory is addressed directly by the in-
`struction or indirectly by the B, X and SP registers.
`The COP82OC has 84 bytes of RAM and the COP84OC has
`128 bytes of RAM. Sixteen bytes of RAM are mapped as
`“registers" that can be loaded immediately, decremented or
`tested. Three specific registers: B, X and SP are mapped
`into this space, the other bytes are available for general
`usage.
`in memory to be set.
`The instruction set permits any bit
`reset or tested. All HO and registers (except the A & PC) are
`memory mapped; therefore, i/O bits and register bits can be
`directly and individually set, reset and tested.
`RESET
`The RESET input when pulled low initializes the microcon-
`troller. Initialization will occur whenever the RESET input is
`pulled low. Upon initialization, the ports L and G are placed
`in the TRl-STATE mode and the Port D is set high. The PC,
`PSW and CNTRL registers are cleared. The data and con-
`figuration registers for Ports L & G are cleared.
`The external RC network shown in Figure 4 should be used
`to ensure that the RESET pin is held low until the power
`supply to the chip stabilizes.
`
`
`
`
`
`Page 000008
`
`PORT D is a four bit output port that is set high wren
`RESET goes low.
`The D2 pin is sampled at reset. If it is held low at reset the
`COPBZOC/COP84OC enters the ROMiess mode of opera-
`tion.
`
`
`

`

`
`
`Functional Description (Continued
`P
`+
`’o
`W
`
`Van
`
`E R
`
`5
`
`l
`
`i
`,
`
`_._
`RESET
`
`5"”
`
`TL DD/BlOEeB
`
`Up f
`
`V
`
`
`
`
`
`J'LF
`EXTERNAL
`ELDCK
`
`HESTART
`
` V
`
`
`
`RC 3 5X Power Supply Rise Time
`FIGURE 4. Recommended Reset Circuit
`OSCILLATOR CIRCUITS
`F/gure 5 shows the three clock oscillator cont gurations
`available for the COPSZOC and COP84OC.
`A. CRYSTAL OSCILLATOR
`The COPSZOC/COP84OC can be driven by a crystal clock.
`The crystal network is connected between the pins CKI and
`CKO.
`Table | shows the component values required for various
`standard crystal values.
`B. EXTERNAL OSCILLATOR
`CKI can be driven by an external clock signal. CKO is avail-
`able as a general purpose Input and/or HALT restart con-
`"0"
`C. R/C OSCILLATOR
`CKI is configured as a single pin FtC controlled Schmitt trlg-
`ger oscillator. CKO is available as a general purpose input
`and/or HALT restart control.
`Table II shows the variation in the oscillator frequencies as
`functions of the component (R and C) values.
`
`CC RESTART
`
`c
`
`I
`_
`
`TL/DD/B‘Ollr l 0
`
`FIGURE 5. Crystal and R-C Connection Diagrams
`OSCILLATOR MASK OPTIONS
`The COP82OC and COPBAOC can be driven by clock inputs
`between DC and 20 MHz. For low input clock frequencies
`(3 5 MHz) the instruction cycle frequency can be selected
`to be the input clock frequency divided by 10. This mode IS
`known as the Normal Mode.
`For oscillator frequencies that are greater than 5 MHz the
`chip must run with a divide by 20. This IS known as the High
`Speed mode.
`
`TABLE I. Crystal Oscillator Configuration, TA : 25°C
`
`R1
`R2
`C1
`C2
`CKI Freq
`Conditions
`
`(k0)
`(Min
`(9F)
`(PF)
`(MHz)
`vcc : 5v
`0
`1
`30
`30-36
`20
`VCC = 5V
`0
`1
`30
`30—36
`10
`0
`1
`30
`30—36
`4 (+ 20)
`VCC : 2.5V
`
`0
`1
`200
`100—150
`0.455
`Vcc = 2.5V
`
`
`TABLE II. RC Oscillator Configuration, TA = 25°C
`
`R
`(Kn)
`3.3
`56
`6.8
`
`C
`(PF)
`82
`100
`100
`
`7
`
`CKI Freq.
`(MHZ)
`2.8 to 2.2
`151011
`1.1 to 0.8
`
`l
`
`Instr. Cycle
`(#5)
`3.6 to 4.5
`s7i09
`9to12.5
`
`.
`.
`Conditions
`
`Vcc = SV
`VCC::5V
`VCC = 2.5V
`
`
`9
`
`Page 000009
`
`

`

`
`
`Functional Description (Continued)
`The COP820C and COP84OC microcontrollers have five
`mask options for configuring the clock input. The CKI and
`CKO pins are automatically configured upon selecting a par-
`ticular option.
`High Speed Crystal (CKI/20) CKO for crystal configura-
`tion
`Normal Mode Crystal (CKI/10) CKO for crystal conf gue
`ration
`High Speed External (CKI/20) CKO available as G7 in-
`put
`Normal Mode External (CKI/10) CKO available as G7
`input
`R/C (CKI/10) CKO available as G7 input
`G7 can be used either as a general purpose input or as a
`control input to continue from the HALT mode.
`CURRENT DRAIN
`The total current drain of the chip depends on:
`1) Oscillator operating mode—l1
`2) Internal switching current—l2
`3) Internal leakage current—l3
`4) Output source current—l4
`5) DC current caused by external input not at VCC or GND—
`l5
`Thus the total current drain, It is given as
`It:l1+l2+l3+l4+|5
`To reduce the total current drain, each of the above compo-
`nents must be minimum.
`The chip will draw the least current when in the nor'nal
`mode. The high speed mode will draw additional current.
`The Fi/C mode will draw the most. Operating with a crystal
`network will draw more current than an external square-
`wave. Switching current, governed by the equation below,
`can be reduced by lowering voltage and frequency. Leak-
`age current can be reduced by lowering voltage and tom
`perature. The other two items can be reduced by carefully
`designing the end-user’s system.
`l2 : C x V x f
`Where
`C = equivalent capacitance of the chip
`V : operating voltage
`f = CKI frequency
`Some sample current drain values at VCC = 6V are:
`
`CKI (MHz)
`Inst. Cycle (its)
`It (mA)
`
`20
`9
`3.58
`2.2
`
`2
`1.2
`0.3
`0.2
`0 (HALT)
`<0.0001
`
`HALT MODE
`The COP820C and COP84OC support a power saving mode
`of operation: HALT. The controller is placed in the HALT
`mode by setting the G7 data bit, alternatively the user can
`stop the clock input. In the HALT mode all internal proces-
`sor activities including the clock oscillator are stopped. The
`fully static architecture freezes the state of the control-
`
`
`
`
`
`
`
`ler and retains all information until continuing. In the HALT
`mode, power requirements are minimal as it draws only
`leakage currents and output current. The applied voltage
`(VCC) may be decreased down to Vr (minimum RAM reten-
`tion voltage) without altering the state of the machine.
`There are two ways to exit the HALT mode: via the RESET
`or by the CKO pin. A low on the FIESET line reinitializes the
`microcontroller and starts executing from the address
`OOOOH. A low to high transition on the CKO pin causes the
`microcontroller to continue with no reinitialization from the
`address following the HALT instruction. This also resets the
`G7 data bit.
`INTERRUPTS
`The COPBZOC and COP84OC have a sophisticated interrupt
`structure to allow easy interface to the real word. There are
`three possible interrupt sources, as shown below.
`A maskable interrupt on external G0 input (positive or nega-
`tive edge sensitive under software control)
`A maskable interrupt on timer carry or timer capture
`A non»maskable software/error interrupt on opcode zero
`INTERRUPT CONTROL
`The GIE (global interrupt enable) bit enables the interrupt
`function. This is used in conjunction with ENI and ENTI to
`select one or both of the interrupt sources. This bit is reset
`when interrupt is acknowledged.
`ENI and ENTI bits select external and timer interrupt re»
`spectively. Thus the user can select either or both sources
`to interrupt the microcontroller when GIE is enabled.
`IEDG selects the external interrupt edge (0 = rising edge,
`1 = falling edge). The user can get an interrupt on both
`rising and falling edges by toggling the state of IEDG bit
`after each interrupt.
`lPND and TPND bits signal which interrupt is pending. After
`interrupt is acknowledged, the user can check these two
`bits to determine which interrupt is pending. This permits the
`interrupts to be prioritized under software. The pending flags
`have to be cleared by the user. Setting the GIE bit high
`inside the interrupt subroutine allows nested interrupts.
`The software interrupt does not reset the GIE bit. This
`means that the controller can be interrupted by other inter-
`rupt sources while servicing the software interrupt.
`INTERRUPT PROCESSING
`The interrupt, once acknowledged, pushes the program
`counter (PC) onto the stack and the stack pointer (SP) is
`decremented twice. The Global Interrupt Enable (GIE) bit is
`reset to disable further interrupts. The microcontroller then
`vectors to the address OOFFH and resumes execution from
`that address. This process takes 7 cycles to complete. At
`the end of the interrupt subroutine, any of the following
`three instructions return the processor back to the main pro-
`gram: RET, HETSK or RETI. Either one of the three instruc-
`tions will pop the stack into the program counter (PC). The
`stack pointer is then incremented twice. The FlETl instruc-
`tion additionally sets the GIE bit to re-enable further inter-
`rupts.
`Any of the three instructions can be used to return from a
`hardware interrupt
`subroutine. The FtETSK instruction
`should be used when returning from a software interrupt
`subroutine to avoid entering an infinite loop.
`
`
`
`
`10
`
`Page 000010
`
`

`

`
`
`Functional Description (Continued)
`
`INTERRUPT TO
`BtC
`
`FIGURE 6. Interrupt Block Diagram
`TABLE III
`
`
`0O1 w
`
`here,
`to is the instruction cycle clock.
`MlCROWIRE/PLUS OPERATION
`Setting the BUSY bit in the PSW register causes the MI-
`CROWIRE/PLUS arrangement to start shifting the data.
`It
`gets reset when eight data bits have been shifted. The user
`may reset the BUSY bit by software to allow less than 8 bits
`to shift. The COPSZOC and COP84OC may enter the MI-
`CROWIRE/PLUS mode either as a Master or as a Slave.
`Figure 8 shows how two COPBZOC microcontrollers and
`several peripherals may be interconnected using the MI-
`CROWIRE/PLUS arrangement.
`Master MlCROWIRE/PLUS Operation
`In the MICROWIRE/PLUS Master mode of operation the
`shift clock (SK) is generated internally by the COPBZOC.
`The MlCROWIRE/PLUS Master always initiates all data ex-
`changes. (See Figure 6). The MSEL bit in the CNTRL regis-
`ter must be set to enable the SO and SK functions onto the
`G Port. The 80 and SK pins must also be selected as out-
`puts by setting appropriate bits in the Port G configuration
`register. Table IV summarizes the bit settings required for
`Master mode of operation.
`SLAVE MICROWIHE/PLUS OPERATION
`In the MlCROWIRE/PLUS Slave mode of operation the SK
`clock is generated by an external source. Setting the MSEL
`bit in the CNTRL register enables the SO and SK functions
`onto the G Port. The SK pin must be selected as an input
`and the 80 pin is selected as an output pin by appropriately
`setting up the Port G configuration register. Table IV sum-
`marizes the settings required to enter the Slave mode of
`operation.
`The user must set the BUSY flag immediately upon entering
`the Slave mode. This will ensure that all data bits sent by
`the Master will be shifted properly. After eight clock pulses
`the BUSY flag will be cleared and the sequence may be
`repeated. (See Figure B.)
`
`
`
`
`INTERRUPT
`LOGIC
`
`TL/DD/9103—11
`
`SK Cycle Time
`ZIC
`4tC
`
`
`
`
`EXTERNAL
`INT. PIN
`
`TIM ER
`UNDERFLOW
`
`SOFTWARE
`
`DETECTION OF ILLEGAL CONDITIONS
`The COPBZOC and COP84OC incorporate a hardware
`mechanism that allows it to detect illegal conditions which
`may occur from coding errors, noise and ‘brown out‘ voltage
`drop situations. Specifically it detects cases of executing out
`of undefined ROM area and unbalanced stack situations.
`Reading an undefined ROM location returns 00 (hexadeci-
`mal) as its contents. The opcode for a software interrupt is
`also ‘00’. Thus a program accessing undefined ROM will
`cause a software interrupt.
`Reading an undefined RAM location returns an FF (hexadee
`cimal). The subroutine stack on the COP82OC and
`COP84OC grows down for each subroutine call. By initializ-
`ing the stack pointer to the top of RAM, the first unbalanced
`return instruction will cause the stack pointer to address
`undefined RAM, As a result the program will attempt to exe-
`cute from FFFF (hexadecimal), which is an undefined ROM
`location and will trigger a software interrupt
`MlCFiOWIRE/PLUS'I’M
`MICROWIRE/PLUS is a serial synchronous bidirectional
`communications interface. The MICROWIRE/PLUS capabil-
`ity enables the COPB20C and COP84OC to interface with
`any of National Semiconductor’s MlCROWIRE peripherals
`(i.e. A/D converters, display drivers, EEPFIOMS, etc.) and
`with other microcontrollers which support the MlCROWIRE/
`PLUS interface.
`It consists of an 8-bit serial shift register
`(SIO) with serial data input (SI), serial data output (SO) and
`serial shift clock (SK). Figure 7 shows the block diagram of
`the MICROWIRE/PLUS interface.
`The shift clock can be selected from either an internal
`source or an external source. Operating the MlCROWIRE/
`PLUS interface with the internal clock source is called the
`Master mode of operation. Similarly, operating the MICRO-
`WIRE/PLUS interface with an external shift clocl. is called
`the Slave mode of operation.
`The CNTRL register is used to configure and control the
`MICROWIRE/PLUS mode. To use the MlCROWIRE/PLUS,
`the MSEL bit in the CNTRL register is set to one. The SK
`clock rate is selected by the two bits, SO and $1,
`in the
`CNTRL register. Table III details the different clock rates
`that may be selected.
`
`
`
`
`11
`
`Page 000011
`
`

`

`
`
`Functional Description (Continued)
`TABLE IV
`
`GS
`64
`Conflg. Conflg.
`Blt
`Blt
`
`64
`
`
`
`
`Operation
`Fun.
`
`
`
`MICROWIRE Master
`
`
`-- so
`
`TRl-STATE Int. SK MICROWIRE Master
`
`MICROWIRE Slave
`TRl-STATE Ext. SK
`
`MICROWIRE Slmd
`TIMER/COUNTER
`The COP82OC and COPMOC have a powerful 16-bit timer
`with an associated 16-bit register enabling them to perform
`extensive timer functions. The timer T1 and its register R1
`are each organized as two 8-bit read/write registers. Control
`bits in the register CNTRL allow the timer to be started and
`stopped under software control. The timer-register pair can
`be operated in one of three possible modes. Table V details
`various timer operating modes and their requisrte control
`settings.
`
`MODE 1. TIMER WITH AUTO-LOAD REGISTER
`in this mode of operation, the timer T1 counts down at the
`instruction cycle rate. Upon underflow the value in the regis-
`ter R1 gets automatically reloaded into the timer which con-
`tinues to count down. The timer undertlow can be pro-
`grammed to interrupt the microcontrolier. A bit in the control
`register CNTFiL enables the TIO (G3) pin to toggle upon
`timer underfiows. This allow the generation of square—wave
`outputs or pulse width modulated outputs under software
`control. (See Figure 9')
`MODE 2. EXTERNAL COUNTER
`In this mode. the timer T1 becomes a 16-bit external event
`counter. The counter counts down upon an edge on the TIO
`pin. Control bits in the register CNTRL program the counter
`to decrement either on a positive edge or on a negative
`edge. Upon undertlow the contents of the register R1 are
`automatically copied into the counter. The undertlow can
`also be programmed to generate an interrupt. (See Figure 9)
`MODE 3. TIMER WITH CAPTURE REGISTER
`Timer T1 can be used to precisely measure external fre-
`quencies or events in this mode of operation. The timer T1
`counts down at the instruction cycle rate. Upon the occur-
`rence of a specified edge on the TIO pin the contents of the
`timer T1 are copied into the register Fit. Bits in the control
`register CNTFiL allow the trigger edge to be specified either
`as a positive edge or as a negative edge. In this mode the
`user can elect to be interrupted on the specified trigger
`edge. (See Figure 10.)
`
`
`Dl CLK
`
`
`
`Tune/910542
`FIGURE 7. MlCROWIRE/PLUS Block Diagram
`
`CHIP SELECT LINES
`
`CS
`
`a-sn
`A/D CON -
`VERTER
`cop43x
`
`cop
`azoc
`(MASTER)
`
`1024 - BlT
`EEPROM
`COP495
`
`CS
`
`LOW
`POWER
`CMOS
`RAM
`& TIMER
`COP498
`
`CS
`
`FREQ.
`GEN. &
`COUNTER
`COP452L
`
`CS
`
`VF
`DISPLAY
`DRIVER
`COP470
`
`DO
`
`DI CLK
`
`D0
`
`DI CLK
`
`DO
`
`DI 0th
`
`D0
`
`Dl CLK
`
`FIGURE 8. MlCROWIRE/PLUS Application
`
`TL/DD/9103—13
`
`
`12
`
`
`
`Page 000012
`
`

`

`
`
` I