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`1991.
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`
`Wang, G.
`
`; Dept. of Electr. Eng , Edinburgh Univ.. UK ; Renshaw, D.
`
`; Denyer, P.B. ; Lu. M.
`
`Abstract
`
`Authors
`
`References
`
`Cited By
`
`Keywords
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`A single chip CMOS video camera is presented, along with design technique and characterization
`results. The chip comprises a 312*287 pixel photodiode array together with all the necessary sensing,
`addressing and amplifying circuitry, as well as a 1000 gate logic processor, which implements
`synchronization timing to deliver a fully-fonnatted composite video signal and a further 1000 gate logic
`processor, which implements automatic exposure control over a wide range. There are also simple
`solutions for gamma correction and test.<>
`
`Published in:
`Euro ASIC '91
`
`Date of Conference:
`
`27-31 May 1991
`
`Page(s):
`100 -103
`
`Meeting Date :
`27 May 1991-31 May 1991
`
`Print ISBN:
`0-8186-2185-0
`
`INSPEC Accession Number:
`4367802
`
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`Conference Location :
`Paris. France
`
`Digital Object Identifier :
`10.1109/EUAS|C.1991.212885
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`

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`CMOS Video Cameras
`
`G. Wang, D. Renshaw, P. B. Denyer and M. Lu
`
`University of Edinburgh
`Department of Electrical Engineering
`Mayfield Road
`Edinburgh, EH9 3JL, UK-.
`
`Abstract
`
`A single chip CMOS video camera is presented,
`along with design technique and characterization
`tm'ttlI.\'. The chip comprises a 312x287 pixel
`photodiode array together with all the necessary
`sensing, addressing and amplifying circuitry, as
`well as a 1,000 gate logic processor, which
`implements synchronization timing to deliver a
`fully-formatted composite video signal and a
`further 1,000 gate logic processor, which imple-
`ments automatic exposure control over a wide
`range. Tltere are also simple solutions for ‘y
`correctt'on and test.
`
`1.
`
`Introduction
`
`We introduce a new capability that extends the
`CMOS ASIC marketplace in a sector of high
`growth rates. This market sector is that of image
`sensing and processing, covering applications
`from electronic cameras to ‘smart’ vision sys-
`tcms.
`
`Camera and vision systems addressed by today’s
`CCD technology appear cumbersome, power-
`hungry and expensive. The experimental work
`reported here demonstrates
`that high-quality
`image sensors can be implemented entirely in
`commodity ASIC CMOS technology, operating
`from single Sv supplies.
`
`The reported chip is a highly-integrated CMOS
`VLSI camera, shown in Figure 1. Most of the
`core area is a 312X 287 pixel image sensor array,
`together with the necessary sensing, addressing
`and amplifying circuitry. The output signal can
`be either linear or -y corrected. 7 correction is
`achieved by a simple solution which uses the
`nonlinear
`ID-VGS characteristic of an MOS
`
`TH0367-3/91/0000/O100$01.00 0 1991 IEEE
`
`I00
`
`transistor. The layout of the sensor is custom
`designed to make it as compact as possible.
`
`At the top (Figure 1) is the 2,000 gate logic pro-
`cessor,
`laid out using -a semi-custom -standard-
`cell compiler. Half of these gates generate syn-
`chronization timing,
`including line-sync and
`frame-sync signals
`to format a 625line/50Hz
`standard composite video output. The other
`half of the gates are included to electronically
`control exposure over a wide range (40,000:1),
`enabling the use of a single fixed-aperture lens.
`The chip measures 7.58mm X7.56mm , using 1.5
`pun, 2 level metal CMOS technology.
`
`
`
`Figure 1. Photo-micrograph of single chip
`video camera
`
`VALEO EX. 1019-004
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`

`
`A video camera has been built using this chip
`along with a 6 MHz clock source, a 5 volt
`power supply, plus one bipolar transistor and a
`small
`number
`of
`resistors
`and
`capacitors
`required to match the line impedance to the
`monitor and decouple the power supply. The
`picture quality is
`subjectively excellent, and
`compares well with commercially available cam-
`eras.
`
`2.
`
`Image Sensor Block
`
`The architecture of the image sensor is shown in
`Figure 2. The light sensing area consists of a
`312x287 diode array matrix, schematically indi-
`cated by the columns and rows of individual
`photodiodes. The pixel size is 19.6p.m X16p.m ,
`giving a light sensing area of 6.12mm ><4.59mm .
`This corresponds to the standard 1/2" format.
`
`+CVO
`
`‘ supplies
`
`clock
`
`D l'l
`
`gain
`setting
`
`cal shift register. At the top of each column is a
`sense amplifier. The sensed information is read
`out sequentially along the x—direction under con-
`trol of a horizontal shift register. At the end of
`the path there is an output amplifier [1,2].
`
`The sense amplifier is a single-ended differential
`charge integrator. Its performance demands an
`accurate capacitor,
`formed by metall/metal2
`and metall/poly. However, commodity ASIC
`CMOS technology sometimes can not guarantee
`the resulting capacitance values. We designed a
`gain-controllable integrator, shown in Figure. 3,
`which allows wide range of programmable varia-
`tion of the capacitance value.
`
`gal;
`
`4-gain control transistors
`
`
`
`Vref _L_
`
`
`
`
`
`self
`
`
`compensation
`
`"
`
`Figure 3.
`
`Integrator with programmable gain
`and self compensation
`
`The main concern in the output stage design is
`the read—out speed required to achieve high
`resolution. A 6 MHZ clock was chosen for this
`
`design; this gives a horizontal resolution of 312
`pixels. The resultant picture quality is assured
`by a two stage output buffer with sample and
`hold function.
`
`3. Automatic Exposure Control
`
`The device automatically controls its exposure
`over a range of 40,000:1. Control
`is achieved
`by varying the integration time prior to reading
`each row of pixels. The integration time can be
`as long as one field, or as short as three cycles
`of the pixel clock(about 500ns).
`
`VALEO EX. 1019-005
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`‘
`
`auto-exposure
`
`control
`
`I995‘?
`
`video format
`
`timing & control
`
`circuits
`
`:_3
`
`8’
`-5
`0)
`in
`13
`'0
`3
`8
`*5
`9
`
`
`
`horizontal addressing
`
`column sense amps
`
`_,_ .......................
`
`8
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`.
`
`.. ._
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`_ Jisht _
`sensing
`area
`
`auto test pattern generation
`
`' CVO -- composite video output
`
`Figure 2. Architecture of the image sensor
`
`The photodiodes are accessed on the basis of
`sequential selection of each row through a verti-
`
`VALEO EX. 1019-005
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`

`
`The exposure is set by monitoring the video
`stream and estimating the fractions of each pic-
`ture which are very white and very black. On
`the basis of this information, the device decides
`whether the picture contrast is acceptable, or too
`white, or too dark. If necessary,
`the exposure
`time is then changed, in the appropriate direc-
`tion.
`
`4. Generation of the Video Format Signal
`
`Figure 4 shows a block diagram for the genera-
`tion of
`the video formatted signal. The -y
`corrected image data is multiplexed with the
`sync-level and blanking-level, controlled by tim-
`ing control signals, which are provided from the
`video
`timing
`block.
`A bipolar
`transistor
`(emitter follower) is needed to provide a low
`impedance output.
`
`in Figure 5.
`
`Vdd
`
`Corrected
`
`output
`
`Linear
`input
`
`I-l
`
`Figure 5. Gamma corrector
`
`SPICE simulation was carried out and a simula-
`tion result is shown in Figure 6. A theoretical
`curve of ideal 7 Correction ( 7 =0.45) is also
`shown in Figure 6.
`
`Vdd
` Image signal
`
`Video
`output
`
`
`
`
`Image
`
`SCH SOT
`
`
`
`
`.I9X9[dll[Il]/q
`
`Blanking Sync
`level
`level
`
` ideal curve
`0.6 0.4
`
`
`.
`_
`simulation result
`
`\ ‘
`
`UK
`
`0.8
`
`0.2
`
`0.2
`
`0.4
`
`0.6
`
`0.8
`
`1.{
`
`
`Figure 4. Generation of the video output
`
`—5—. Simple -Solution for ‘y Correction
`
`to be y
`image data needs
`analogue
`The
`corrected, to compensate for the nonlinearity of
`monitor tubes [3]. This is usually implemented
`using discrete components e.g. a ladder-network
`of diodes,
`resistors
`and reference voltages.
`Unfortunately,
`this is not suitable for integra-
`tion.
`In this design 'y correction is achieved by
`a simple solution which uses the nonlinear I
`—
`VGS characteristic of an MOS FET, as shown
`
`Figure 6. Gamma correction curves
`
`6. Simple Solution for Test
`
`Special consideration has been given to make it
`possible to carry out digital wafer test which is
`as complete as possible. The analogue parts are
`also tested by making them produce digital out-
`puts, so avoiding a requirement for full analo-
`gue test. The test
`includes bit—line tests and
`word-line tests. Only a 0.78% increase in chip
`area was required to implement
`the on chip
`
`I02
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`VALEO EX. 1019-006
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`
`llardwilfe necessary ff)? this 'fE)l'ffl Of testing (Fig-
`ure 2). The individual photo pixels may be
`tested if a sufficiently long vector set is allow-
`able.
`
`The chip can also self-generate a checkerboard
`pattern which may be displayed on a monitor
`screen, or captured by a frame grabber. This
`pattern can be used not only to find defective
`pixels, but also to check analogue performance
`parameters, such as read out speed and unifor-
`mity.
`
`7. Eliminating Noise
`
`Complete guard rings are put around all analo-
`gue parts to minimize interference from the digi-
`tal parts. Routing is arranged with priority to
`analogue output and analogue power supplies.
`Analogue power supplies and digital supplies are
`'separated, and supplies to different analogue
`parts are divided where necessary.
`
`There are two sources of fixed pattern noise:
`threshold variation in the MOS pixel access
`transistors causing speckles, and mismatches
`between the column sense amplifiers causing
`vertical stripes. The s’o1’utien to the pixel thres-
`hold variation is to reduce the pixel reset voltage
`below (Vdd-Vt)
`so that
`the reset voltage is
`insensitive to the variation of the threshold Vt.
`
`Column fixed pattern noise arises mostly from
`offset mismatches in the column sense amplif-
`iers. We l1ave successfully eliminated this prob-
`lem by automatically compensating each amplif-
`ier to give zero offset during each line synchron-
`ization interval.
`
`8. Characterization
`
`An optical test measurement set-up was used to
`characterize the camera. The following table
`summarize the measured results of the perfor-
`mance characterization experiments. The param-
`eters of typical monochrome CCD cameras are
`also given for comparison.
`
`I 31'ameter
`
`operating voltage
`for camera
`
`for chi .
`
`antibloomin factor
`
`for camera
`
`2‘’°'““”
`J 51:18
`4o.ooo:1
`
`saturation level
`
`s2dB
`soon
`
`* as fraction of saturation at room temperature,
`20msec integration time
`
`9. Conclusions
`
`We have developed several design techniques to
`achieve a single chip camera,
`in unmodified
`CMOS
`technology.
`which
`matches
`the
`performance of CCD cameras. The (lesign has
`proven that three technical barriers which most
`greatly influence new product development;
`cost, power
`consumption and size,
`are all
`dramatically reduced over
`today’s
`solid-state
`camera technologies.
`
`10. Acknowledgements
`
`received from the
`We acknowledge support
`Science
`and Engineering Research Council
`(Grant GR/F 36538 IED2/1/1159).
`
`11. References
`
`[1] D. Renshaw, et. al., "ASIC Vision", Proc.
`IEEE
`Custom
`Integrated
`Circuits
`Conference, 1990, pp 3038-3041.
`
`[2]
`
`et.
`
`"ASIC Image
`al.,
`D. Renshaw,
`International
`IEEE
`Sensors",
`Proc.
`Symposium on Circuits and Systems, 1990,
`pp 7.3.l—7.3.4.
`
`[-3]
`
`'l‘clevision and Video
`Eugene Trundle,
`Engineers Pocket Book, Heinemann, 1987.
`
`I03
`
`VALEO EX. 1019-007
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`VALEO EX. 1019-007