UNITED STATES PATENT AND TRADEMARK OFFICE
`
`___________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________________________
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`___________________________________
`
`Case No. IPR2014-00108
`Patent Number 7,151,027
`
`Before the Honorable DEBRA K. STEPHENS, JUSTIN T. ARBES, and
`RICHARD E. RICE, Administrative Patent Judges.
`
`CORRECTED DECLARATION OF SHUKRI SOURI, Ph.D.
`
`
`
`
`
`
`
`
`
`Spansion Exhibit 2002
`Macronix et al v. Spansion
`IPR2014-00108
`Page 00001
`
`
`
`___________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________________________
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD. and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`___________________________________
`
`Case No. IPR2014-00108
`Patent Number 7,151,027
`
`Before the Honorable DEBRA K. STEPHENS, JUSTIN T. ARBES, and
`RICHARD E. RICE, Administrative Patent Judges.
`
`CORRECTED DECLARATION OF SHUKRI SOURI, Ph.D.
`
`
`
`
`
`
`
`
`
`Spansion Exhibit 2002
`Macronix et al v. Spansion
`IPR2014-00108
`Page 00001
`
`
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`
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`I, Shukuri Souri, hereby declare under penalty of perjury under the laws of the United
`
`States of America:
`
`I.
`
`Qualifications
`
`1.
`
`I am currently a Corporate Vice President at Exponent, Inc.
`
`(“Exponent”), an engineering and scientific consulting firm, headquartered at 149
`
`Commonwealth Drive, Menlo Park, California 94025. I am based in, and the Director
`
`of, Exponent’s New York office. I am also the Director of Exponent’s Electrical
`
`Engineering and Computer Science practice.
`
`2.
`
`I received a Master’s Degree in Electrical Engineering from Stanford
`
`University in 1994, and a Ph.D. in Electrical Engineering, also from Stanford
`
`University, in 2003. I have extensive experience with semiconductor devices,
`
`including the design, fabrication, modeling, measurement, and testing of integrated
`
`circuits. While at Stanford University, I taught several courses on integrated circuit
`
`fabrication, optical fiber communications, and networking. Before joining Stanford, I
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`was a member of the staff at Raychem Corporate Research and Development
`
`Laboratories, where I worked on semiconductor materials and electrical circuit
`
`protection devices. I am a named inventor on four U.S. patents related to
`
`semiconductor processes, devices, and integrated circuits.
`
`3. My education, experience, and qualifications, including a list of my
`
`publications and a list of matters in which I have testified as an expert, are set forth in
`
`my curriculum vitae, attached hereto as EX2003. My opinions, as expressed in this
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`1
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`Page 00002
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`
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`report, are based on my education, career, and relevant experience, as well as the
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`materials reviewed.
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`4.
`
`I have been retained on behalf of Patent Owner Spansion LLC to offer
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`statements and opinions regarding the understanding of a person of ordinary skill in
`
`the art (discussed below) as it relates to U.S. Patent No. 7,151,027 (the ’027 Patent)
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`assigned to Patent Owner, as well as other references presented to me by counsel for
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`Patent Owner.
`
`5.
`
`I am a salaried employee of Exponent. Exponent charges an hourly rate
`
`of $495 plus expenses for my work performed in connection with this Inter Partes
`
`Review. I have received no additional compensation for my work in this Inter Partes
`
`Review, and my compensation does not depend on the contents of this report, any
`
`testimony I provide, or the ultimate outcome of this Inter Partes Review.
`
`II. Materials Considered
`
`6.
`
`In developing my opinions below relating to the ’027 Patent, I have
`
`considered the following materials:
`
` U.S. Patent No. 7,151,027 (Exhibit MX027-1001);
`
` Petition for Inter Partes Review of U.S. Patent No. 7,151,027
`(“Petition” or “Pet.”) (Paper No. 1);
`
` Patent Owner’s Preliminary Response (Paper No. 14);
`
` Decision – Institution of Inter Partes Review (Paper No. 16) (“ID”);
`
` Corrected Declaration of Dhaval J. Brahmbhatt (Exhibit MX027-
`1002);
`
`
`
`2
`
`Page 00003
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`
`
`
`
` U.S. Patent No. 6,458,655 to Yuzuriha, et al. (“Yuzuriha”) (Exhibit
`MX027-1003);
`
` U.S. Patent No. 6,258,648 to Lee (Exhibit MX027-1004);
`
` U.S. Patent No. 6,559,012 to Shukuri, et al. (Shukuri) (Exhibit
`MX027-1005);
`
` U.S. Patent No. 6,359,304 to Nakagawa (“Nakagawa”) (Exhibit
`MX027-1006);
`
` U.S. Patent No. 6,461,916 to Adachi (Exhibit MX027-1007);
`
` Exhibit to Brahmbhatt Declaration – Purported Excerpt from
`Streetman, Ben, SOLID STATE ELECTRONIC DEVICES, 4th Ed
`(Prentice Hall 1995) (Exhibit MX027-1008);
`
` Exhibit to Brahmbhatt Declaration - Kim, J.H., et al., An Empirical
`Model for Charge Leakage Through Oxide-Nitride-Oxide Interpoly Dielectric in
`Stacked-Gate Flash Memory Devices, 18 SEMICONDUCTOR SCI. &
`TECH. 158 (16 Jan. 2003) (Exhibit MX027-1009);
`
` Transcript of Videotaped Deposition of Dr. Dhaval Brahmbhatt (July
`2, 2014);
`
` Transcript of Videotaped Deposition of Dr. Dhaval Brahmbhatt (July
`3, 2014); and
`
` All other materials referenced herein.
`III. Level of Ordinary Skill for the ’027 Patent
`
`7.
`
`I understand that the factors that may be considered in determining the
`
`ordinary level of skill in the art include: (1) the levels of education and experience of
`
`persons working in the field; (2) the types of problems encountered in the field; and (3)
`
`the sophistication of the technology. I understand that a person of ordinary skill in the
`
`art is not a specific real individual, but rather a hypothetical individual having the
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`qualities reflected by the factors above.
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`
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`3
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`Page 00004
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`8.
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`It is my opinion that at least as of June 1, 2004, the filing date of the ’027
`
`Patent, a person of ordinary skill in the art would have had a Bachelor’s of Science
`
`degree in materials science, electrical engineering, physics or the equivalent and about
`
`two years of processing experience related to memory device fabrication.
`
`9.
`
`I note that Mr. Brahmbhatt has opined that “a person of ordinary skill in
`
`the art would have a bachelor’s degree in Electrical Engineering and 2-3 years of
`
`experience in design or fabrication of semiconductor memories. An individual with
`
`additional education or industry experience could also be one of ordinary skill in the
`
`art if that additional experience compensated for a deficit in the other aspect stated
`
`above.” MX027-1002 at ¶ 29.
`
`10. Unless otherwise stated, when I state that something would be known or
`
`understood by a person of ordinary skill in the art, I am referring to a person with the
`
`level of education and experience expressed in ¶¶ 8-9 above, as of June 1, 2004. As
`
`described above and in my CV (EX2003), I have decades of experience with
`
`semiconductor devices, including the design and fabrication of memory devices. As
`
`of June 1, 2004, I would have qualified as one of ordinary skill in the art according to
`
`either of the above definitions. Therefore, I am qualified to testify about what a
`
`person of ordinary skill in the art would have known and understood at that time.
`
`IV. Relevant Legal Standards
`
`11.
`
`I have been informed that if an independent claim is found to be valid,
`
`every claim that depends from it is also valid. I have also been informed that if an
`4
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`Page 00005
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`
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`independent claim is found to be invalid, the claims which depend from it may be
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`found to be valid.
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`12.
`
`I understand that to be valid, a patent claim must be non-obvious and
`
`novel. I also understand that a patent claim is not novel if is anticipated by a single
`
`prior art reference – that is, a single prior art reference discloses each and every
`
`element of the claim either expressly or inherently. I also understand that a single
`
`reference cannot merely disclose each element. Rather, it must disclose all of the
`
`elements as arranged in the claim. I further understand that for a reference to
`
`“inherently” disclose something, the missing descriptive matter must necessarily be
`
`present in the reference, not merely probably or possibly present, and that it would be
`
`so recognized by a person of ordinary skill. I understand that if an element of the
`
`claim is not disclosed by one prior art reference, then the claim is not anticipated.
`
`13.
`
`I understand that a patent claim is deemed obvious if the differences
`
`between it and the prior art are such that the subject matter as a whole would have
`
`been obvious at the time the invention was made to a person having ordinary skill in
`
`the art. That is, a person of ordinary skill must have had a reasonable expectation of
`
`success in making or practicing the claimed invention, based on the prior art. I also
`
`understand that the obviousness analysis does not permit the use of hindsight. One
`
`way of avoiding a hindsight analysis is to point to a suggestion or a motivation in the
`
`prior art to make or practice the claimed invention.
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`
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`5
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`Page 00006
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`14.
`
`I have been informed that to render a claim obvious, a combination of
`
`prior art references must disclose each and every claim element of that claim, and that
`
`obviousness is a question of law (i.e. for the Board to determine) based on the
`
`underlying facts. I understand that the underlying factual inquiries are: (1) the scope
`
`and content of the prior art, (2) the differences between the prior art and the claims at
`
`issue, (3) the level of ordinary skill in the pertinent art, and (4) secondary
`
`considerations of nonobviousness. I also understand that a patent composed of
`
`several elements is not proven to be obvious by simply demonstrating that each of its
`
`elements was, independently, known in the prior art. Instead, I understand that there
`
`must be some rationale given to support the conclusion.
`
`15.
`
`I further understand that, in making a determination as to whether or
`
`not the claimed invention would have been obvious to a person of ordinary skill, the
`
`Board must consider certain objective factors, such as commercial success, long-felt,
`
`but unsolved need, unexpected results, copying, and praise by others in the field. The
`
`presence of such factors is evidence of non-obviousness. I also understand that a
`
`connection, or nexus, must exist between the objective category and the claimed
`
`invention.
`
`16.
`
`I understand that the Board has instituted an inter partes review of claims
`
`1-6 and 8-13 of the ’027 Patent. I understand that trial is limited to the following
`
`grounds: (1) whether claims 1-4 and 8-10 are anticipated by Yuzuriha; (2) whether
`
`claims 5, 11, and 12 are rendered obvious by Yuzuriha and Shukuri; and (3) whether
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`Page 00007
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`claims 6 and 13 are rendered obvious by Yuzuriha and Nakagawa. (ID at 33). I
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`further understand that the Petition was denied as to all other grounds and trial is
`
`accordingly limited to these three grounds. I understand that the Board “has not
`
`made a final determination under 35 U.S.C. § 318(a) with respect to the patentability
`
`of the challenged claims.” Id.
`
`V.
`
`Background of the ’027 Patent
`17. U.S. Patent 7,151,027 (the “’027 Patent”), entitled “Method and Device
`
`for Reducing Interface Area of a Memory Device” was filed on June 1, 2004, and
`
`issued on December 19, 2006. The patent names inventors Hiroyuki Ogawa, Yider
`
`Wu, Kuo-Tung Chang, and Yu Sun.
`
`18. As discussed in the ’027 Patent, “[o]ne important goal of the
`
`semiconductor industry is to reduce the size of memory devices. In reducing the size
`
`of operational components (e.g., a memory array) and periphery components, an
`
`important consideration is the interface between the operational components and
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`periphery components.” MX027-1001 at 1:18-23. This arrangement is illustrated in
`
`Figure 2 of the ’027 patent, where a memory device 200 includes the periphery
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`components, labeled 210, the memory array, labeled 220, and a portion of the
`
`interface, labeled 230. MX027-1001 at FIG 2.
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`7
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`Page 00008
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`19. Memory devices contain millions of components made up of complex
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`structures fabricated by the repeated deposition of layers on a silicon substrate, or
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`wafer.
`
` MX027-1001 at 1:13-18.
`
` Typical fabrication methods common
`
`in
`
`semiconductor fabrication prior to the invention of the ’027 Patent for forming
`
`memory devices typically formed the operational components and periphery
`
`components separately. Id. at 1:25-26. In other words, when the periphery
`
`components were formed, only the periphery was etched (i.e., the memory was
`
`masked, or protected from being etched), and when the memory array was formed,
`
`only the memory array was etched (i.e., the periphery was masked, or protected from
`
`being etched). For various reasons, by using these different processes, a number of
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`steps having different heights at the interface were created. Id. at 1:24-31. Figure 1 in
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`
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`8
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`Page 00009
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`
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`the ’027 Patent depicts what a step at the interface may look like using these prior art
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`methods. Id. at FIG 1.
`
`20.
`
`Figure 1 shows interface 100 and substrate 110 etched leaving structures
`
`115 and 120. Notably, structure 120 is higher than structure 115—a difference that is
`
`difficult to control because of the different processes being used. MX027-1001 at
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`
`
`1:34-42.
`
`21. As the ’027 Patent further describes, a common occurrence during the
`
`formation of sidewall spacers was the formation of potentially damaging stringer
`
`spacers at these steps. Id. at 1:47-51. These stringer spacers 130 may be easily peeled
`
`from the device and displaced to other locations on the device, resulting in yield loss
`
`of performance by the memory array. Id. at 1:45-53; FIG 1.
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`22. The invention described and claimed in the ’027 Patent provides a
`
`solution to this problem by providing methods for forming a polysilicon structure at
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`9
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`Page 00010
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`
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`the interface between the memory array and the periphery where steps with different
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`heights may be formed. See id. at 2:57-3:2. In so doing, the methods of the ’027
`
`Patent reduce the formation of stringer spacers and allow for a reduction in the
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`number of processing steps, cycle time, cost and yield loss. See id. In particular, the
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`interface structure is the same height as the memory array proximate to the memory
`
`array and the same height as the periphery proximate to the periphery, such that step
`
`size is smoothed out, reducing the occurrence of stringers from spacer etching. See id.
`
`at 5:30-35.
`
`VI. Claim Construction
`23.
`I understand that the Board has construed certain terms of the ’027
`
`Patent in its Institution Decision. Below is a list of the Board’s constructions that I
`
`have applied when rendering the opinions set forth herein:
`
` “poly-2 layer” (claims 1 and 8): “a polysilicon layer deposited later in
`time than a first polysilicon layer.” (ID at 8).
`
` “poly-1 layer” (claims 2, 6, and 8): “a first polysilicon layer.” (ID at 9).
`
` “stacked gate etch” (claims 3 and 9): “a process that etches poly-1 and
`poly-2 layers.” (ID at 11).
`
` “second gate etch” (claims 4 and 10): “a process that etches a poly-2
`layer.” (ID at 12).
`
`24.
`
`I understand that the Board, based on the record then before it and
`
`without the benefit of expert testimony about how these terms would be understood
`
`by a person of ordinary skill in the art, did not agree with the Patent Owner that
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`“etching said poly-1 layer and said poly-2 layer proximate to said memory array”
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`10
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`Page 00011
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`recited in claim 8 requires a single etching step because the Board found that Patent
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`Owner did not “explain sufficiently why ‘etching’ in claim 8 requires the recited
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`structures to be etched in ‘one step’ rather than by a process that involves multiple
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`steps, for example, sequentially etching one structure and then the other, in separate
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`steps.” (ID at 9). The Board similarly was “not persuaded” that “the recited ‘stacked
`
`gate etch’ in claims 3 and 9 must be accomplished in a single step.” (ID at 12).
`
`25. As explained in detail below, it is my opinion that the “etching”
`
`limitations in claims 3, 8-9, as understood by a person of ordinary skill in the art in
`
`view of the ’027 Patent’s specification, requires etching the recited structures in a
`
`single etching step.
`
`26.
`
`First, the plain language of claim 8 requires that both the “said poly-1
`
`layer and said poly-2 layer” 1 are etched as a single “etching” step of the claimed
`
`method.
`
`27.
`
`Second, claim 8’s explicit recitation of “etching said poly-1 layer and said
`
`poly-2 layer proximate to said memory array” as a single “etching” step of the claimed
`
`method stands in contrast to the ’027 Patent’s separate recitation, including in other
`
`claims, of multiple distinct “etching” steps, such as claims 1, 2 and 8. For example,
`
`claim 1 does not recite “etching said poly-2 layer proximate to said memory array and
`
`proximate to said periphery...” Instead, it recites “etching said poly-2 layer proximate
`
`to said memory array; and etching said poly-2 layer proximate to said periphery...”
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`1 All emphasis herein is added unless otherwise stated.
`11
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`Page 00012
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`Moreover, claim 8’s recitation of a single “etching” step for both “said poly-1 layer
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`and said poly-2 layer proximate to said memory array” stands in direct contrast to
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`claims 1 and 2 that recite the etching of poly-1 layer and poly-2 layer as two separate
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`steps: “etching said poly-2 layer proximate to said memory array” in claim 1 and,
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`subsequently, in claim 2, “etching said poly-1 layer proximate to said memory array.”
`
`28. Third, the ’027 Patent explicitly describes the etching of the poly-1 layer
`
`and poly-2 layer proximate to the memory array as a single etching “step” (“step 440”)
`
`in its process. This is clearly illustrated in, for example, the ’027 Patent’s Figure 4,
`
`reproduced below with highlights in orange:
`
`
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`12
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`Page 00013
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`29. This is also confirmed in the text of the ’027 Patent, which states that
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`this is a single step: “At step 440, the poly-1 layer and the poly-2 layer are etched
`
`proximate to the memory array. In one embodiment, the etching is accomplished by
`
`performing a stacked gate etch.” MX027-1001 at 5:21-24.
`
`30. The ’027 Patent further states: “With reference next to FIG. 3E, in the
`
`present embodiment, a known process (such as a stacked gate etch) is used to etch
`
`a portion of poly-1 310 a, dielectric material 315, and poly-2 320 proximate to the
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`memory array.” Id at 4:27-30, Fig. 3D & 3E:
`
`
`31. The ’027 Patent further describes that “[t]his etch is used to form
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`individual transistors of [sic] from the polysilicon layers… The etch creates a distinct
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`boundary between the memory array and the interface region.” Id. at 4:30-35.
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`
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`13
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`Page 00014
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`32. Therefore, it is my opinion that a person of ordinary skill would have
`
`understood from the ’027 Patent’s express disclosure that the claim term “etching
`
`said poly-1 layer and poly 2 layer proximate to said memory array” in claim 8 means
`
`what it says: these two layers are etched in a single etching step.
`
`33. A person of ordinary skill would similarly have recognized that the
`
`“stacked gate etch” claimed in the ’027 Patent is performed in a single step, without,
`
`for example, re-masking. Cf, e.g., Ex. 1002 ¶ 26 (Mr. Brahmbhatt opining that
`
`“etching” refers to a process beginning with masking and concluding with removal of
`
`mask).
`
`34. Moreover, I note that Mr. Brahmbhatt applied the construction for
`
`“stacked gate etch” that was provided to him by Petitioner’s2 attorneys, which is an
`
`“etching step that etches…” Notably, Petitioner’s construction also used a single
`
`“etching step” as opposed to multiple etching “steps.”
`
`35. Therefore, in my opinion, the claimed “stacked gate etch” should
`
`properly be construed as it would have been recognized by a person of ordinary skill
`
`in the art: as a single etching step.
`
`VII. Yuzuriha
`
`
`2 I refer to Petitioners Macronix International Co., Ltd., Macronix Asia Limited,
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`Macronix (Hong Kong) Co., Ltd., and Macronix America, Inc. collectively as
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`“Petitioner” herein.
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`14
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`Page 00015
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`36.
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`Petitioner and Mr. Brahmbhatt contend that Yuzuriha anticipates claims
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`1-4 and 8-10 of the ’027 Patent. I disagree. As discussed below in sub-section VII.A,
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`in my opinion, Yuzuriha does not disclose at least the “etching” limitation recited in
`
`the challenged claims.
`
`37.
`
`Petitioner and Mr. Brahmbhatt further contend that Yuzuriha, in view of
`
`additional prior art references urged by Petitioner, render obvious claims 5-6 and 11-
`
`13. I disagree. As discussed below in sub-section VII.B, in my opinion, a person of
`
`ordinary skill in the art would not have found it obvious, or been motivated, to look
`
`to the teachings of Yuzuriha to begin with.
`
`A.
`
`38.
`
`The “Etching” Limitations (Claims 3 and 8-14)
`
`Independent claim 8 recites, inter alia, “etching said poly-1 layer and said
`
`poly-2 layer proximate to said memory array.” As discussed above, the plain language
`
`of the claim limitation, as understood by a person of ordinary skill in the art in view of
`
`the express disclosure in the ’027 Patent, requires that both the “poly-1 layer and []
`
`poly-2 layer” are etched in a single etching step.
`
`39.
`
`Similarly, claim 3 (which depends from claim 1) recites “etching said
`
`poly-2 layer proximate to said memory array is accomplished by performing a stacked
`
`gate etch.” As discussed above, a “stacked gate etch” as claimed in the ’027 Patent,
`
`which was construed by the Board to mean “a process that etches poly-1 and poly-2
`
`layers” would be understood by a person of ordinary skill in the art to similarly require
`
`that both the poly-1 and poly-2 layers be etched in a single etching step.
`
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`15
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`Page 00016
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`40.
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`In my opinion, Yuzuriha fails to disclose a process that etches the poly-1
`
`layer and poly-2 layer in a single etching step. Petitioner, which has added numerous
`
`annotations to the figures from Yuzuriha shown below, acknowledges that Yuzuriha
`
`discloses between Figures 8 and 9 one step where poly-2 is first etched (both
`
`proximate to the memory array and proximate to the periphery), and subsequently
`
`and separately between Figures 9 and 10 “another etching step is performed to etch
`
`the poly-1 layer (10) (shown in green) proximate to the memory array.” Pet. 12. As
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`can be seen in Petitioner’s heavily annotated Figures 8-10, Yuzuriha first performs
`
`what Petitioner has annotated as the steps of “etching poly-2 proximate to the
`
`memory array” and “etching poly-2 proximate to periphery.” See annotated Figs. 8-9:
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`16
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`Page 00017
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`Then, in what Petitioner itself labels a subsequent “etching step” (Pet. 12),
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`Yuzuriha performs what Petitioner has annotated as the step of “etching poly-1
`
`proximate to the memory array.” See annotated Fig. 10 :
`
`
`
`41.
`
`Importantly, the process that etches the alleged poly-2 layer (colored in
`
`yellow by Petitioner) does not etch the alleged poly-1 layer (colored in green by
`
`Petitioner). The alleged poly-1 layer is not etched until “another etching step is
`
`
`
`performed” (Pet. 12), as shown in Figure 10.
`17
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`Page 00018
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`42. Moreover, in my opinion, this “[]other etching step” to etch poly-1, as
`
`shown between Figures 9 and 10 in Yuzuriha, also etches other portions of the
`
`structure proximate to both the memory (e.g., tunnel oxide film 9) and to the
`
`periphery (e.g., gate oxide 12), in ways that, as even Mr. Brahmbhatt concedes, are not
`
`actually disclosed in Yuzuriha but in his experience, would require additional re-
`
`masking to accomplish – confirming again that they are not part of a single etch step
`
`with the etching of poly-2 as the claims require, and that at minimum Yuzuriha could
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`not support any such finding by a preponderance of the evidence. See, e.g., Ex. 2004
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`at 40:16-41:3, 59:13-61:12 (“there are a whole bunch of things that get[] etched”; “it’s
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`not one etching step”), 62:21-66:18; id. 82:2-5, 83:14-25 (Yuzuriha doesn’t “show all
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`the steps involved”), 71:25-72:16, 73:20-75:11 (responding to question regarding
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`“using the remaining oxide Film 16 as an etching mask and etching the poly-poly
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`insulation mask 11 and the Poly-1” between figures 9 and 10: “like I mentioned
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`before and I will mention this again, I do not have Yuzuriha’s complete process
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`manual in front of me. I don’t know how he did it. All I can tell you is, if it is in my
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`fab, while you’re doing that, you will have to protect the periphery; otherwise, you’re going to
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`cause damage. I mean, that’s physics, I mean, chemistry. I mean, that is going to
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`happen. So my thinking would be that – and I don’t know this how Yuzuriha does it,
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`because there is no description on that.”), 85:18-87:12 (“Q: So you don’t know
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`whether he uses the same mask to etch poly-poly or Poly-1 as to etch Layer 9? A: I
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`would be guessing. I don’t know what he does.”; “I mean, there’s a whole bunch things we
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`Page 00019
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`know that would happen in between, but we just don’t have those details”), 87:25-
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`88:13 (“Q: . . .And between Figures 9 and 10 you’ll agree that two portions of gate
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`oxide 12 are etched, as well; right? A: That’s what I see in the diagram. Q: And so
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`you don't know one way or the other whether Yuzuriha masks the periphery area
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`between 9 and 10; right? A. Well, all he says is – it’s important to read 63, line 63,
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`column 12. Actually, 62 and 63. Poly-to-poly insulation Film 11 and Floating Gate
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`10 are etched only in the memory cell region. That’s what he says.”), 95:18-96:2 (“Q:
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`Focusing now on Gate Oxide 12, which is etched between Figures 9 and 10, is there a
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`disclosure in Yuzuriha about how that etching is done? . . . A: Okay. Let me read.
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`Just a second. (Document Review.) I’m sorry, there’s no disclosure.”). And, in my
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`opinion, Yuzuriha involves separate etching steps, in part because it requires re-
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`masking to perform the disclosed steps.
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`43. Therefore, in my opinion, Yuzuriha does not disclose at least “etching
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`said poly-1 layer and said poly-2 layer proximate to said memory array,” as required in
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`independent claim 8 (and thus in all of its dependent claims), and also fails to disclose
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`at least “etching said poly-2 layer proximate to said memory array is accomplished by
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`performing a stacked gate etch” as recited in Claim 3.
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`B.
`Yuzuriha in The Asserted Obviousness Combinations (Claims 5-6
`and 11-13)
`
`44.
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`Petitioner advances Yuzuriha as the base reference in each of its asserted
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`obviousness combinations for dependent claims 5-6 and 11-13. In my opinion, a
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`19
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`Page 00020
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`person of ordinary skill would not have applied Yuzuriha’s teachings to reach the
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`inventions claimed in the ’027 Patent because the type of isolation and structure used
`
`at the alleged interface in Yuzuriha actually increases the alleged interface area and
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`introduces steps, the problems that the ’027 patent seeks to avoid.
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`45. As Mr. Brahmbhatt acknowledges, “the ’027 Patent is intended to reduce
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`the interface area of a memory device...” MX027-1002 at ¶ 13 13 (opining that
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`“[m]ore particularly, the ’027 Patent is intended to reduce the interface area of a memory
`
`device, by forming an interface structure in the [interface] area between the memory
`
`core and the periphery.”); MX027-1001 2:57-59 (“The present invention provides a
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`method and structure for reducing interface area between the memory array and the periphery
`
`of a memory device.”). For example, the ’027 Patent is entitled “Method and device
`
`for reducing interface area of a memory device,” and describes forming a polysilicon
`
`structure at the interface between the memory array and the periphery of a memory
`
`device that is “operable to smooth out any steps caused by etching” and eliminate the
`
`creation of “stringer spacers.” MX027-1001 at 2:62-66. In particular, the ’027 Patent
`
`states that an intended goal is to avoid the use of methods that would require
`
`“additional area of the interface,” such as the use of salicide block, that would
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`“considerably limit[] the ability to reduce the size of the interface area.” Id. at 1:54-62;
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`2:66-3:2. See also id. 1:19-33, 1:34-42, 1:45-53, 2:57-3:2, 4:50-54, 5:30-35.
`
`46. Yuzuriha, on the other hand, is directed to “prevent[ing] an altered
`
`surface layer of a resist from being removed” during a “dry-etch and wet-etch.”
`20
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`Page 00021
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`
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`MX027-1003 at Abstract. The “Tenth Embodiment” of Yuzuriha relied upon by Mr.
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`Brahmbhatt describes that the “process performed to prevent removal of the altered
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`surface layer of the resist” allows a poly-poly insulation film (11) to recede “closer to
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`the memory cell region” than a conventional process. Id. at 12:30-37, Figs. 7-8:
`
`
`
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`47. As a result, instead of an “abrupt” step variation, a “gentle” step results
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`when a “dummy gate 14” is subsequently formed. Id. at 37-52, Fig. 9:
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`21
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`Page 00022
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`48. A person of ordinary skill in the art would have recognized that
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`Yuzuriha’s explicit goal of “resulting in a gentle step” at the alleged interface area, is
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`directly contrary to the “intended result of the claimed [’027] process” acknowledged
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`by Petitioner (Pet. 5), which is “such that step size is smoothed out reducing the
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`occurrence of stringers from spacer etching.” MX027-1001 at 2:11-12, 4:52-54, 5:34-
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`35, Claims 7 and 14.
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`49. Unlike the ’027 Patent that describes forming the interface structure on,
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`e.g., a “shallow trenched” isolation (“STI”) area that results in the structure having the
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`“same height” as the periphery and memory array , and which a person of skill would
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`recognize would minimize the interface area (MX027-1001 at 3:51-52; 4:49-54; 5:30-
`
`35), Yuzuriha describes, in contrast, forming the asserted “dummy gate” on an
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`“isolating oxide film 8” that, as disclosed in, e.g., Figs. 5-10 of Yuzuriha, is raised above
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`the silicon substrate surface as compared to the structures in the alleged memory array
`
`and periphery and requires additional horizontal and vertical areas of the alleged
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`22
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`Page 00023
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`“dummy gate region.” See EX2004 (Deposition of Plaintiff’s expert, Mr. Brahmbhatt)
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`at 117:3-10, 118:13-25; MX027-1003 at 11:52-54; Fig. 5:
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`50. Again, Mr. Brahmbhatt acknowledges “[a]ny difference in height in the
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`dummy gate of [Yuzuriha’s] Figure 5 result from the fact that the dummy gate is
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`shown on top of ‘isolating oxide film 8…’” MX027-1002 at ¶ 129.
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`51. As depicted in Figure 5 of Yuzuriha, the raised “isolating oxide film 8”
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`not only contributes to Yuzuriha’s goal of a “resulting…gentle step” but also
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`increases the height of the “dummy gate 14” as compared to the memory cell and
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`peripheral circuitry regions, and moreover, increases the area of the alleged interface
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`area (i.e., the “dummy gate region”)—the very problems the ’027 Patent seeks to avoid.
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`52.
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`Petitioner and Mr. Brahmbhatt further acknowledge that “isolating oxide
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`film 8” of Yuzuriha may be formed using “‘local oxidation of silicon,’ or LOCOS.”
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`IPR2014-00898, Pet. 17 (citing MX027II-1002, ¶¶ 58-59). I agree that the “isolating
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`oxide film 8” of Yuzuriha may be formed using LOCOS. See, e.g., MX027-1003 at
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`23
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`Page 00024
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`
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`11:45-62, 12:1-2, Figs. 5-10. Mr. Brahmbhatt stated, “Yuzuriha’s FIG. 5 shows the
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`dummy gate region on the thick isolation oxide based on the then prevalent LOCOS
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`[local oxidation of silicon] technology.” (IPR2014-00898, MX027II-1002, ¶¶ 58-59;
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`see also id., Paper 1 at 17 (citing MX027II-1002, ¶¶ 58-59)).
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`53. A person of ordinary skill in the art would further recognize that the
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`“isolating oxide film 8” formed using LOCOS would require additional vertical and
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`horizontal area in the asserted “dummy gate region,” and therefore would not
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`minimize the alleged “interface.” Mr. Brahmbhatt in fact acknowledges that LOCOS
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`would result in “taller” and “wider” areas: “And, for example, even going back to the
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`LOCOS structures… We have used different techniques in the industry to adjust to
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`the question, the phenomena that you are kind of pointing to, that…when the
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`isolation structure is getting taller…it is also getting wider, and then is it going to
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`then…impact the overall spacing issue…” EX2004 at 117:3-10; 118:13-25.
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`54. A person of ordinary skill in the art would recognize that the alleged
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`“interface” of Yuzuriha contains a raised “isolating oxide film” that would not
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`minimize the required “interface” area, but instead would require “additional area of
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`the interface” and would “considerably limit[] the ability to reduce the size of the
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`interface area”—the problems the ’027 Patent seeks to avoid. Yuzuriha’s use of a
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`raised “isolating oxide film” at the alleged “interface” that requires “additional area of
`
`the interface” on w
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