`
`
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`MACRONIX INTERNATIONAL CO., LTD., MACRONIX ASIA LIMITED,
`MACRONIX (HONG KONG) CO., LTD., and MACRONIX AMERICA, INC.
`Petitioners
`
`v.
`
`SPANSION LLC
`Patent Owner
`
`
`
`Case: IPR2014-00108
`
`
`
`CORRECTED DECLARATION OF DHAVAL J. BRAHMBHATT
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313–1450
`Submitted Electronically via the Patent Review Processing System
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 1
`
`
`
`
`
`
`
`
`I.
`
`I, Dhaval J. Brahmbhatt, hereby declare as follows:
`
`Introduction and Qualifications
`
`1.
`
`I am the founder and am currently the president and CEO of
`
`PHYchip Corporation (“PHYchip”). Among other things, PHYchip provides
`
`expert services in the design of high-speed analog and mixed-signal integrated
`
`circuit (“IC”), a variety of memory devices, with a particular focus on non-
`
`volatile memory devices such as Flash memory modules.
`
`2.
`
`I have prepared this Declaration on behalf of Macronix International
`
`Co., Ltd., Macronix Asia Limited, Macronix (Hong Kong) Co., Ltd., and
`
`Macronix America, Inc. (collectively, “Macronix”) in connection with a petition
`
`for Inter Partes Review of U.S. Patent No. 7,151,027 (“the ’027 Patent”)
`
`(MX027-1001).
`
`3.
`
`I have summarized in this section relevant aspects of my educational
`
`background and career history. My full resume is attached as Appendix A to this
`
`Declaration.
`
`Educational Background
`
`4.
`
`In 1977, I received a Master of Science Degree in Physics with a
`
`specialization in Solid State Electronics from Gujarat University in India. In
`
`1978, I received a second Master of Science Degree, this one in Electrical
`
`Engineering, from the University of Cincinnati in Ohio. I also hold certificates in
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 2
`
`
`
`
`
`
`management trainings from Stanford University Graduate School of Business, a
`
`certificate in marketing from University of London in Ontario, Canada and a
`
`certificate in nanotechnology from the California Institute of Nanotechnology.
`
`Career History
`
`5.
`
`I have over 30 years of substantive experience in the field of IC
`
`memory device design and manufacture. I began my career in 1978 at a Fairchild
`
`Semiconductor, working on the design and development of Erasable
`
`Programmable Read-Only Memory (“EPROM”) products. I later worked on the
`
`design and production of single power supply Electronically Erasable
`
`Programmable Read-Only Memory (“EEPROM”) products for Synertek, which
`
`was a subsidiary of Honeywell International, Inc., and then I worked for National
`
`Semiconductor as a design manager for high density EEPROM memory devices.
`
`6.
`
`In 1996, I was named Vice President of Technology and Business
`
`Development for the Smart Modular Corporation. In that position, I oversaw the
`
`design, development, and marketing of advanced IC memory-based modules
`
`such as Flash memory cards for portable devices produced by major
`
`multinational technology companies.
`
`7.
`
`I later consulted in the Flash memory card industry and served as a
`
`“C” level officer in several start-up companies that developed IC devices prior to
`
`founding PHYchip Corporation in 2002.
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 3
`
`
`
`
`
`
`8.
`
`I am the sole inventor on ten patents and the lead inventor on all
`
`eleven patents listed under my name at the USPTO. Most of these patents relate
`
`to EPROM, EEPROM, and/or Flash memory IC design, memory cell design,
`
`memory array architecture, etc.
`
`II.
`
`Scope of Assignment
`
`9.
`
`I have been asked to provide my opinion on the validity of the ’027
`
`Patent. In particular, I have been asked to consider whether the inventions
`
`recited in claims 1-14 of the ’027 Patent are unpatentable over certain published
`
`prior art references. This Declaration sets forth my opinion on this topic.
`
`10.
`
`In my analysis, I considered the ’027 Patent and its file history, as
`
`well as the prior art references and related documentation discussed below. I
`
`have considered these documents in light of the general knowledge in the art at
`
`the time of the alleged inventions. In formulating my opinion, I have relied upon
`
`my experience, education, and knowledge in the relevant art. I have also helped
`
`prepare and reviewed in detail the claim charts that are to be included with the
`
`petition for Inter Partes Review of the ’027 Patent, to which this Declaration
`
`relates.
`
`11. Additional information may become available which would further
`
`support or modify the conclusions that I have reached to date. Accordingly, I
`
`reserve the right to modify and/or enlarge this opinion or the bases thereof upon
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 4
`
`
`
`
`
`
`consideration of any further discovery, testimony, or other evidence, or based
`
`upon the interpretations of or conclusions about any claim term by the Patent
`
`Office different than those proposed in this declaration.
`
`III. The ’027 Patent
`It appears from the face of the ’027 Patent that it issued from U.S.
`12.
`
`patent application number 10/859,369, which was filed on June 1, 2004. It does
`
`not appear the patent claims an earlier filing date.
`
`13. The ’027 Patent generally relates to a method for manufacturing a
`
`semiconductor memory device. More particularly, the ’027 Patent is intended to
`
`reduce the interface area of a memory device, by forming an interface structure in
`
`the area between the memory core and the periphery.
`
`14. The ’027 Patent discloses an embodiment of the steps required to
`
`form this interface structure in Figures 3A through 3G, along with the
`
`accompanying text. In the following discussion, each of Figures 3A through 3G
`
`have been annotated to help distinguish the various layers.
`
`15. First, as shown in Figure 3A, a first layer of polysilicon, or “poly-1,”
`
`(green) is formed over an isolation area (light blue) over a silicon substrate
`
`(darker blue). See MX027-1001 at 3:50-67.
`
`
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 5
`
`
`
`
`
`
`
`16. Next, as shown in Figure 3B, a dielectric material (red) is formed
`
`over the entire surface. The ’027 Patent describes an embodiment in which
`
`this dielectric consists of “ONO,” a well-known dielectric material that consists
`
`of layers of Silicon Oxide, Silicon Nitride, and Silicon Oxide. See MX027-1001
`
`at 4:1-9.
`
`
`
`17. Next, as shown in Figure 3C, a known etching process is used to
`
`remove some of the dielectric and polysilicon layers.
`
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 6
`
`
`
`
`
`
`
`18. Next, as shown in Figure 3D, a second poly silicon layer, or “poly-
`
`
`
`2,” (yellow) is formed over the entire structure. MX027-1001 at 3:10-21
`
`
`
`
`19. Next, a known etch process, such as a “stacked gate etch,” is used to
`
`
`
`etch the structure on the side nearest the memory core. This etch removes the
`
`poly-2 layer, the dielectric layer, and the poly-1 layer in the unmasked region.
`
`The resulting structure is illustrated in Figure 3E. MX027-1001 at 4:27-37.
`
`
`
`
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 7
`
`
`
`
`
`
`20. Next, a second etching process, such as a “second gate etch,” is used
`
`to etch the structure on the side nearest the periphery. This etch removes only the
`
`poly-2 layer (as that is the only layer in the unmasked region). After the
`
`completion of these two etch steps, the interface structure remains in the interface
`
`area between the memory core and periphery. The resulting structure is
`
`illustrated in Figure 3F. MX027-1001 at 4:38-49.
`
`
`
`
`21. Finally, as illustrated in Figure 3G, dielectric material (purple) is
`
`
`
`deposited on the entire structure, and selectively etched to form dielectric film
`
`345 over the top of the core, interface structure, and periphery. This dielectric
`
`deposit and etch process also creates spacers 350 on the side walls of the core,
`
`interface structure, and periphery. MX027-1001 at 4:55 – 5:4.
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 8
`
`
`
`
`
`
`
`I.
`
`Summary of My Opinions
`
`
`
`22. Based on my investigation and analysis, and for the reasons set forth
`
`below, it is my opinion that all of the elements recited in claims 1–14 of the ’027
`
`Patent are disclosed in prior art references, and that those claims are anticipated
`
`by and/or rendered obvious in view of these references. In particular, I have
`
`reviewed the following prior art references:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`•
`
`•
`
`•
`
`U.S. Patent No. 6,458,655 to Yuzuriha, et al. (“Yuzuriha”) (MX027-
`
`1003)
`
`U.S. Patent No. 6,258,648 to Lee (“Lee”) (MX027-1004)
`
`U.S. Patent No. 6,599,012 to Shukuri, et al. (“Shukuri”) (MX027-
`
`1005)
`
`•
`
`U.S. Patent No. 6,359,304 to Nakagawa (“Nakagawa”) (MX027-
`
`1006)
`
`23.
`
`I have read and understood the claim charts attached to the Petition,
`
`and agree with the technical analysis set forth therein.
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 9
`
`
`
`
`
`
`II. Background of Relevant Technology
`“Floating Gate” Memory Cells: EPROM and Flash
`
`24. The ’027 Patent states that “[t]he present invention relates to the
`
`field of floating gate devices.” MX027-1001 at 1:6-7. A “floating gate” is a
`
`well- known configuration that is used to create non-volatile memory, a class of
`
`semiconductor memory that retains storage of data even after a power supply is
`
`removed from the memory. Examples of technologies that can be implemented
`
`using a floating gate include EPROM, EEPROM, and Flash – all of which are
`
`types of non-volatile memory.
`
`25. The floating gate structure has been in use since at least 1972, when
`
`Dov Frohman of Intel was awarded U.S. Patent number 3,660,819. In this kind
`
`of device, each storage location consists of a single Field Effect Transistor (FET)
`
`that is different from other transistors because it also has over the transistor
`
`channel gate oxide, an additional gate which is called the “floating gate” because
`
`it is not connected to any node. Above the floating gate will be formed another
`
`insulating layer, over which a second conducting gate called “control gate” will
`
`be deposited. A cross section of a memory cell utilizing a floating gate can be
`
`illustrated as follows:
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 10
`
`
`
`
`
`
`
`
`Etching
`
`
`
`26.
`
`In semiconductor processing, “etching” generally refers to process
`
`of applying a temporary layer commonly known as a “photoresist,” patterning
`
`the photoresist into a “mask,” and then using chemicals to remove portions of the
`
`semiconductor structure not covered by the mask. Once the intended removal is
`
`complete, the photoresist is removed.
`
`27. Etching is one of the fundamental techniques in semiconductor
`
`device manufacture; the manufacture of a semiconductor device will typically
`
`include many repetitions of the process of growing or depositing a layer of
`
`material, and selectively etching the material in areas uncovered by the mask for
`
`that layer. The ’027 Patent does not utilize any novel etch processes, but
`
`describes the use of known etch processes such as a “stacked gate etch.”
`
`See,
`
`e.g., MX027-1001 at 4:27-30.
`
`
`
`
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 11
`
`
`
`
`
`
`
`III. Legal Principles Used in Analysis
`I am not a patent attorney, nor have I independently researched the
`28.
`
`law of patent validity. Attorneys have explained certain legal principles to me
`
`that I have relied on in forming my opinions set forth in this Declaration.
`
`Person of Ordinary Skill in the Art
`
`29.
`
`I understand that assessment of the validity of claims 1-14 of the
`
`’027 Patent must be undertaken from the perspective of what would have been
`
`known or understood by someone of ordinary skill in the art as of the earliest
`
`claimed priority date of the ’027 Patent – June 1, 2004. From analyzing the ’027
`
`Patent and the prior art, it is my opinion that a person of ordinary skill in the art
`
`would have a bachelor’s degree in Electrical Engineering and 2-3 years of
`
`experience in design or fabrication of semiconductor memories. An individual
`
`with additional education or industry experience could also be one of ordinary
`
`skill in the art if that additional experience compensated for a deficit in the other
`
`aspect stated above. Unless otherwise stated, when I state that something
`
`would be known or understood by one skilled in the art, or having ordinary
`
`skill in the art, I am referring to a person with this level of education and
`
`experience.
`
`30. A person of ordinary skill in the art of semiconductor memory
`
`design and fabrication would have looked to various sources of available
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 12
`
`
`
`
`
`
`information in order to address the purported problem of the ’027 Patent –
`
`improving the fabrication of memory devices at the interface between memory
`
`array and periphery.
`
`Identification of this problem, along with various
`
`solutions, can be found in numerous references including Yuzuriha (MX027-
`
`1003).
`
`Prior Art
`
`31.
`
`I have been informed that the law provides certain categories of
`
`information (known as prior art) that may be used to anticipate or render obvious
`
`patent claims. I have been asked to presume that the reference materials I opine
`
`on below are prior art, and have not formed an opinion whether these references
`
`are, in fact, prior art as applied against the ’027 Patent.
`
`Anticipation
`
`32.
`
`I have been informed that a claim is not patentable when a single
`
`prior art reference describes every element of the claim, either expressly or
`
`inherently to a person of ordinary skill in the art. I understand that this is
`
`referred to as “anticipation.” I have also been informed that, to anticipate a
`
`patent claim, the prior art reference need not use the same words as the claim, but
`
`it must describe the requirements of the claim with sufficient clarity that a person
`
`of skill in the art would be able to make and use the claimed invention based on
`
`the single prior art reference.
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 13
`
`
`
`
`
`
`33.
`
`In addition, I was informed and understand that, in order to establish
`
`that an element of a claim is “inherent” in the disclosure of a prior art reference,
`
`it must be clear to one skilled in the art that the missing element is an inevitable
`
`part of what is explicitly described in the prior art, and that it would be
`
`recognized as necessarily present by a person of ordinary skill in the art.
`
`D. Obviousness
`
`34.
`
`I have been informed that, even if every element of a claim is not
`
`found explicitly or implicitly in a single prior art reference, the claim may still be
`
`unpatentable if the differences between the claimed elements and the prior art are
`
`such that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person of ordinary skill in the art. That is, the invention
`
`may be obvious to a person having ordinary skill in the art when seen in light of
`
`one or more prior art references. I understand that a patent is obvious when it is
`
`only a combination of old and known elements, with no change in their
`
`respective functions, and that these familiar elements are combined according to
`
`known methods to obtain predictable results.
`
`35.
`
`I have been informed that the following four factors are considered
`
`when determining whether a patent claim is obvious: (1) the scope and content of
`
`the prior art; (2) the differences between the prior art and the claim; (3) the level
`
`of ordinary skill in the art; and (4) secondary considerations tending to prove
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 14
`
`
`
`
`
`
`obviousness or nonobviousness. I have also been informed that the courts have
`
`established a collection of secondary factors of nonobviousness, which include:
`
`unexpected, surprising, or unusual results; non-analogous art; teachings away
`
`from the invention; substantially superior results; synergistic results; long-
`
`standing need; commercial success; and copying by others. I have also been
`
`informed that there must be a connection between these secondary factors and
`
`the scope of the claim language.
`
`36.
`
`I have also been informed that some examples of rationales that may
`
`support a conclusion of obviousness include: (A) combining prior art elements
`
`according to known methods to yield predictable results; (B) simply substituting
`
`one known element for another to obtain predictable results; (C) using known
`
`techniques to improve similar devices (methods, or products) in the same way;
`
`(D) applying a known technique to a known device (method, or product) ready
`
`for improvement to yield predictable results; (E) choosing from a finite number
`
`of identified, predictable solutions, with a reasonable expectation of success—in
`
`other words, whether something is “obvious to try”; (F) using work in one field
`
`of endeavor to prompt variations of that work for use in either the same field or a
`
`different one based on design incentives or other market forces if the variations
`
`are predictable to one of ordinary skill in the art; and (G) arriving at a claimed
`
`invention as a result of some teaching, suggestion, or motivation in the prior art
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 15
`
`
`
`
`
`
`that would have led one of ordinary skill to modify the prior art reference or to
`
`combine prior art reference teachings.
`
`37.
`
`I have also been informed that other rationales to support a
`
`conclusion of obviousness may be relied upon, for instance, that the common
`
`sense (where substantiated) of the person of skill in the art may be a reason to
`
`combine or modify prior art to achieve the claimed invention.
`
`IV. Claim Construction
`38. Attorney have provided me with constructions of various terms
`
`within the ’027 Patent’s claims. I have not been asked to form, and I have not
`
`formed, an opinion regarding these claim constructions. Below is a list of the
`
`provided constructions, which I applied when rendering the opinions set forth
`
`herein:
`
`
`
`
`
`
`
`
`
`Claim Term
`
`
`
`
`“interface between a memory
`
`array and a periphery”
`
`“stacked gate etch”
`
`“second gate etch”
`
`
`
`
`
`
`
`
`
`
`
`
`
`Broadest Reasonable
`
`Interpretation
`
`an area between an array of
`
`memory cells and a periphery
`
`etching step that etches at least a
`
`portion of a stacked gate structure
`
`etching step that etches at least a
`
`portion of a second gate
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 16
`
`
`
`
`
`
`
`
`
`“such that step size is smoothed
`
`not a limitation
`
`out, reducing an occurrence of
`
`stringers from spacer etching”
`
`V.
`
`Invalidity Analysis
`A. Claims 1-4, 6, 8-10, and 13 are anticipated by
`
`Yuzuriha i. Description of the reference
`
`39. United States Patent 6,458,655 to Yuzuriha, et al. (“Yuzuriha”) is
`
`entitled “Method of Manufacturing Semiconductor Device and Flash Memory.” I
`
`understand that Yuzuriha will be designated as Exhibit MX027-1003 to the
`
`Petition for Inter Partes Review. Based on the face of the patent, Yuzuriha was
`
`issued on October 1, 2002.
`
`40. Like the ’027 Patent, Yuzuriha is directed to a method for
`
`manufacturing a semiconductor memory that includes forming a structure
`
`between a memory array (referred to in Yuzuriha as a “memory cell
`
`region”) and a periphery (“peripheral circuit region”).
`
`41. As shown in Figure 5 of Yuzuriha, a structure composed of poly-1
`
`layer 10 (green), inter-layer dielectric 11 (red), poly-2 layer 13 (yellow), and top
`
`layer of oxide 16 is formed in the “dummy gate region” between the memory
`
`array and the periphery.
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 17
`
`
`
`
`
`
`
`
`
`42. As discussed in more detail below, Yuzuriha discloses every
`
`
`
`element of claims 1-4, and 8-10 of the ’027 Patent. It is therefore my opinion
`
`that these claims are unpatentable as anticipated by Yuzuriha.
`
`ii. Application to the claims of the ’027 Patent
`
`43. Claims 1, 2, and 8. Claim 1 of the ’027 Patent claims a method for
`
`fabricating a memory device, comprising forming a poly-2 layer above a
`
`substrate at an interface between a memory array and a periphery; etching the
`
`poly-2 layer proximate to the memory array, and etching the poly-2 layer
`
`proximate to the periphery, such that a portion of the poly-2 layer remains at the
`
`interface.
`
`44. Claim 2 depends from claim 1, and adds the limitations that a layer
`
`of poly-1 is formed in the interface between the substrate and the poly-2, and that
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 18
`
`
`
`
`
`
`said poly-1 layer is etched proximate to the memory array, and etched proximate
`
`to the periphery, so that a portion of poly-1 remains at the interface.
`
`45.
`
`Independent claim 8 claims a method for fabricating a memory
`
`device, comprising forming a poly-1 layer above a substrate at an interface
`
`between a memory array and a periphery; forming a poly-2 layer above the poly-
`
`1 layer at the interface, etching the poly-1 and poly-2 layers proximate to the
`
`memory array, and etching the poly-2 layer proximate to the periphery, such that
`
`a portion of the poly 1 and poly-2 layers remain at the interface.
`
`46. Yuzuriha discloses forming such a structure in its description of a
`
`tenth embodiment, which is illustrated in Figures 5-10. MX027-1003 at 11:39-
`
`62. As described in Yuzuriha, Figure 5 is a cross section of a memory device,
`
`and Figures 6-10 are cross sections of the device at various stages of its
`
`manufacture. MX027-1003 at 8:4-10.
`
`47. Figure 5 of Yuzuriha shows that a “dummy gate region” is located
`
`between a “memory cell region” and a “peripheral circuit region.”
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 19
`
`
`
`
`
`
`48. This paragraph intentionally left blank.
`
`
`
`49. To a person of skill in the art, the “memory cell region” of Yuzuriha
`
`is the same as the “memory array” of the ’027 Patent. Similarly, the “peripheral
`
`circuit region” is the same as the “periphery” of the ’027 Patent. The “dummy
`
`gate region” of Yuzuriha is therefore the “interface between a memory array and
`
`a periphery” claimed in the ’027 Patent.
`
`50. As part of the process of forming the structure in the interface of
`
`Figure 5, Yuzuriha discloses that a “first polysilicon layer 10” is deposited across
`
`the surface of the memory array, the interface, and the periphery. On top of the
`
`polysilicon 10, a layer of dielectric, referred to as “poly-poly insulation film 11”
`
`is also formed. Finally, a layer of photoresist 15 is added and patterned, so that it
`
`is covering the memory cell region and part of the interface, which are not to be
`
`etched. Figure 6 shows the cross section of the device after these steps have been
`
`performed.
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 20
`
`
`
`
`
`
`
`
`
`
`
`
`51.
`
`It is common in the art to refer to layers of polysilicon by a number
`
`that indicates the position of the layer relative to the substrate (which will
`
`typically correspond to the order of manufacture). Because the “first polysilicon
`
`layer 10” of Figures 5-10 is the polysilicon layer closest to the substrate, one of
`
`skill in the art would refer to polysilicon layer 10 as “the poly-1 layer” (or more
`
`simply, “poly-1”).
`
`52.
`
`In the next step, Yuzuriha discloses etching the poly-1 layer
`
`proximate to the periphery (using the photoresist shown in Figure 6 as a mask),
`
`so that some of the poly-1 remains over the interface area. MX027-1003 at 12:6-
`
`13. Figure 7 shows the structure after the unmasked area of poly-1 has been
`
`etched.
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 21
`
`
`
`
`
`
`
`53. After removal of the photoresist, a second layer of polysilicon (13)
`
`is formed over the surface of the device, and a layer of oxide 16 is formed on top.
`
`MX027-1003 at 12:28-30. Because this is the second layer of polysilicon
`
`deposited, a person of skill in the art would refer to this as the poly-2 layer.
`
`Figure 8 shows the structure after these steps have been performed.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 22
`
`
`
`
`
`
`54. Although the text of Yuzuriha at column 12, lines 28 through 55
`
`makes reference to Figure 7, it is clear from the context that this text is actually
`
`describing Figure 8. First, Figure 7 was already described at lines 10 through 22.
`
`Second, the arrows A, B, and C that are described in this text appear only in
`
`Figure 8. A person of skill in the art would easily recognize this typographical
`
`error, and would understand that this description applies to Figure 8.
`
`55. After formation of the poly-2 layer and oxide 16, the oxide and
`
`poly-2 are etched, and “a memory cell’s control gate 13 and a peripheral
`
`circuitry’s transistor gate 13 are patterned.” MX027-1003 at 12:56-59. As can
`
`be seen from Figure 9, this involves etching the poly-2 in the interface structure
`
`proximate to memory, and etching the poly-2 proximate to the periphery. After
`
`these etch steps, a portion of poly-2 remains in the interface area.
`
`
`
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 23
`
`
`
`
`
`
`56. Finally, Yuzuriha describes using the remaining oxide film 16 as an
`
`etching mask, and etching the poly-poly insulation mask 11 and the poly-1.
`
`MX027-1003 at 12:60-63. As such, the poly-1 in the interface area is etched
`
`proximate to the memory array. Figure 10 shows the result of this etch.
`
`
`
`
`57. Accordingly, as discussed above, Yuzuriha discloses all elements of
`
`
`
`claims 1, 2, and 8.
`
`58. Claims 3 and 9. Claims 3 and 9 of the ’027 Patent depend from
`
`claims 1 and 8, respectively, and add the limitation that etching the poly-2 layer
`
`proximate to the memory array is accomplished by performing a stacked gate
`
`etch.
`
`59. Yuzuriha discloses etching the poly-2, inter-poly film, and poly-1
`
`layer by using the oxide 16 as an etching mask. MX027-1003 at 12:56-59. As
`
`can be seen from Figure 10, these etching steps are used to form the stacked gate
`
`structure of the memory cells. See MX027-1003 at 43-45.
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 24
`
`
`
`
`
`
`
`
`
`The etching of poly-2, poly-poly insulation, and poly-1 using patterned oxide 16
`
`is an example of a stacked gate etch.
`
`60. Claims 4 and 10. Claims 4 and 10 depend from claims 1 and 8,
`
`respectively, and add the limitation that etching the poly-2 layer proximate the
`
`periphery is accomplished by performing a second gate etch.
`
`61. As shown in Figure 9, the poly-2 layer is etched proximate the
`
`periphery to form the gate of the peripheral circuit transistor, and to leave a
`
`portion of the poly-2 in the interface area. Because this etch forms the peripheral
`
`circuit transistor gate from poly-2, this is the “second gate etch” required by
`
`claims 4 and 10 of the ’027 Patent.
`
`B. Claims 1-6 and 8-13 are anticipated by
`
`Shukuri i. Description of the reference
`
`62. United States Patent 6,559,012 to Shukuri, et al. (“Shukuri”) is
`
`entitled “Method for Manufacturing Semiconductor Integrated Circuit Device
`
`Having Floating Gate and Deposited Film.” I understand that Shukuri will be
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 25
`
`
`
`
`
`
`designated as Exhibit MX027-1005 to the Petition for Inter Partes Review.
`
`Based on the face of the patent, Shukuri was issued on May 6, 2003.
`
`63. Shukuri is directed to methods for manufacturing semiconductor
`
`devices using different process technologies on the same integrated circuit.
`
`Shukuri discloses the formation of multiple “element forming regions” that are
`
`used to form different types of transistors. The third embodiment of Shukuri
`
`discloses the manufacture of a microprocessor with a built in flash memory, in
`
`which one “element forming region” is used for non-volatile memory cells, and
`
`two other regions are used for logic transistors operating at different voltages.
`
`MX027-1005 at 17:13-17, FIG. 24.
`
`64.
`
`In this third embodiment, Shukuri discloses the formation of a
`
`structure at the interface between the first (or memory) element forming region
`
`and the second (logic transistor) element forming region. See id. at Fig. 24.
`
`
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 26
`
`
`
`
`
`
`
`
`
`65. As shown in Figure 24, the interface structure is formed above
`
`
`
`substrate 51 at the interface between the memory and the periphery, and is
`
`composed of a poly-1 layer (green), an inter-poly dielectric (red), and a poly-2
`
`layer (yellow).
`
`66. Shukuri also discloses the formation of sidewall spacers (orange)
`
`made of Silicon Nitride, in the periphery, in the interface, and in the memory
`
`core. MX027-1005 at 21:4-10. Shukuri discloses leaving the sidewall spacers in
`
`place as source and drain implants are performed. Id. at 21:11-19.
`
`ii. Application to the claims of the ’027 Patent
`67. Claims 1, 2, and 8. Claim 1 of the ’027 Patent claims a method for
`
`fabricating a memory device, comprising forming a poly-2 layer above a
`
`substrate at an interface between a memory array and a periphery; etching the
`
`poly-2 layer proximate to the memory array, and etching the poly-2 layer
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 27
`
`
`
`
`
`
`proximate to the periphery, such that a portion of the poly-2 layer remains at the
`
`interface.
`
`68. Claim 2 depends from claim 1, and adds the limitations that a layer
`
`of poly-1 is formed in the interface between the substrate and the poly-2, and that
`
`said poly-1 layer is etched proximate to the memory array, and etched proximate
`
`to the periphery, so that a portion of poly-1 remains at the interface.
`
`69.
`
`Independent claim 8 claims a method for fabricating a memory
`
`device, comprising forming a poly-1 layer above a substrate at an
`
`interface between a memory array and a periphery; forming a poly-2 layer above
`
`the poly-1 layer at the interface, etching the poly-1 and poly-2 layers
`
`proximate to the memory array, and etching the poly-2 layer proximate to the
`
`periphery, such that a portion of the poly 1 and poly-2 layers remain at the
`
`interface.
`
`70. Shukuri discloses the formation of this structure in its third
`
`embodiment, which is illustrated in Figures 23-32. MX027-1005 at 16:57-61.
`
`Figure 24 of Shukuri is a cross section of an integrated circuit device, and
`
`Figures 25-32 are cross sections at stages in the process of manufacture. Id. at
`
`5:28-50.
`
`71. Figure 24 of Shukuri illustrates that such a structure has been
`
`formed at the interface between a first element forming region (where non-
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 28
`
`
`
`
`
`
`volatile floating-gate memory cells are formed) and a second element forming
`
`region (where logic transistors are formed).
`
`
`
`
`
`
`72. Although Shukuri does not use the term “periphery”, a person of
`
`
`
`skill in the art would recognize that the logic transistor forming regions shown in
`
`Figure 24 form a portion of the periphery of the memory array. Accordingly, the
`
`structure is formed at the interface of the memory array and the periphery.
`
`73.
`
`In forming the interface structure, Shukuri discloses that a
`
`polycrystalline silicon film (green) “is formed by a chemical vapor deposition all
`
`over the p-type semiconductor substrate 51 including the element forming
`
`regions.” MX027-1005 at 19:31-36. Because it is the first layer formed over the
`
`substrate, a person of skill in the art would refer to this layer as “poly-1.”
`
`
`
`
`
`
`
`IPR2014-00108
`Corrected Exhibit MX027-1002, p. 29
`
`
`
`
`
`
`74. On top of the poly-1 layer, an interlayer insulting film 61 (red) is
`
`formed of “an oxide film having a thickness of about 4 nm, a nitride film having
`
`a thickness of about 7 nm, an oxide film having a thickness of about 4 nm and a
`
`nitride film having a thickness of about 11 nm sequentially[.]” Id. at 19:38-43.
`
`75. Next, a photoresist mask M50 is formed over the memory region
`
`and a portion of the interface region, and used to etch away the p
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
