INSTITUTE OF PHYSICS PUBLISHING
`
`Semicond. Sci. Technol. 18 (2003) 158–162
`
`SEMICONDUCTOR SCIENCE AND TECHNOLOGY
`
`PII: S0268-1242(03)36843-9
`
`An empirical model for charge leakage
`through oxide–nitride–oxide interpoly
`dielectric in stacked-gate flash memory
`devices
`
`Jang Han Kim1, Jung Bum Choi1, Bong Jo Shin2
`and Keun Hyung Park2
`
`1 Department of Physics, Chungbuk National University, Chungbuk 361–763, Korea
`2 School of Electrical and Computer Engineering, Chungbuk National University,
`Chungbuk 361–763, Korea
`
`Received 10 May 2002, in final form 2 December 2002
`Published 16 January 2003
`Online at stacks.iop.org/SST/18/158
`
`Abstract
`We have studied the reliability problems in the degradation of the data
`retention characteristics of the stacked-gate flash EEPROM devices
`with an oxide–nitride–oxide (ONO) interpoly dielectric. Threshold
`voltage shift measured as a function of bake time at all tested temperatures
`shows that there are two distinct phases which have different dependences
`on the bake temperature and time; the first phase shows a very fast shift rate
`of the threshold voltage while the second phase has a gradual shift rate.
`Based on the high-temperature accelerated test, an empirical model was
`developed for each phase, which explains the dominant mechanisms for the
`spontaneous charge leakage through the ONO interpoly dielectric.
`
`1. Introduction
`
`Degradation of the data retention capability in floating
`gate flash EEPROM has recently become a greater critical
`reliability issue as the scale-down process in the devices goes
`on. The reliability is due to the instability of a cell threshold
`voltage which is very sensitive to charge-leakage mechanisms
`occurring in the programmed cells. Oxide–nitride–oxide
`(ONO) stacked film has been widely used as the interpoly
`dielectric in stacked-gate flash EEPROM for improvement
`of the reliability problem since it has the advantages of a
`higher coupling ratio and a better charge retention capability
`compared to the pure polysilicon oxide film used earlier
`[1, 2]. However, the ONO interpoly dielectric provides many
`leakage paths of the charge stored in the floating gate during
`long-term memory operation since the bottom polyoxide and
`internitride of the ONO layer are much more defective and
`conductive compared to the tunnel-gate oxide which is grown
`thermally on a single crystalline silicon. Hence, the long-term
`instability of cell threshold voltage caused by charge leakage
`through the ONO interpoly dielectric becomes still one of the
`most serious reliability issues in stacked-gate flash EEPROM
`devices [1–4]. It is very important to understand the charge
`
`leakage mechanisms through the interpoly dielectric in order
`to forecast accurately the degradation of the device lifetime
`due to the charge leakage under normal operation condition.
`As is well known, the device lifetime is measured by using
`the high temperature acceleration test, where the threshold
`voltage shift at normal operation temperature can be obtained
`by extrapolating data obtained at higher temperatures [5]. It is
`therefore very important to have an accurate empirical model
`in order to evaluate the device lifetime correctly. Although
`the charge transport mechanisms through the ONO layer and
`their effects on the data retention characteristics of stacked-
`gate EPROM or flash EEPROM devices have been intensively
`studied in the previous literatures [1, 2, 4, 6–10], the model for
`the temperature–time dependency of the cell threshold voltage
`shift, which can explain the charge leakage mechanisms during
`a high-temperature accelerated testing, has not been cleared
`yet based on the experimental results. Previous literatures
`[1, 6] reported that in stacked-gate flash EEPROM cells
`with ONO interpoly dielectric the spontaneous charge leakage
`proceeds in three distinct phases as the bake time prolongs.
`However, our studies here showed that the threshold voltage
`shift proceeds in two distinct phases for all
`the tested
`temperatures; the first phase shows a very fast shift rate of
`
`0268-1242/03/020158+05$30.00 © 2003 IOP Publishing Ltd Printed in the UK
`
`158
`
`

`

`An empirical model for charge leakage through oxide–nitride–oxide interpoly dielectric
`
`
`3 6 0°…360°C
`
`3 4 0°…340°C
`
`3 2 0°…320°C
`
`3 0 0°…300°C
`
`2 7 0°…270°C
`
`2 4 0°…240°C
`
`2 0 0°…200°C
`
`10
`
`1
`
`0.1
`
`0.01
`
`VT [V]
`
`∆
`
`
`360°…360°C
`
`340°…340°C
`
`320°…320°C
`
`300°…300°C
`
`270°…270°C
`
`240°…240°C
`
`200°…200°C
`
`0123456
`0123456
`
`]
`
`VT [V
`
`T
`
`∆
`
`
`
`00
`
`
`
`100100
`
`
`
`200200
`
`
`
`300300
`
`
`
`400400
`
`
`
`500500
`
`
`
`600600
`
`0.1
`
`1
`
`10
`
`100
`
`1000
`
`
`
`BBake T ime [hrs]
`
`Bake Time [hrs]
`
`Figure 1. Threshold voltage decrease versus bake time for various
`bake temperatures.
`
`Figure 2. The decrease of the threshold voltage versus bake time for
`various bake temperatures in log–log scale.
`
`
`
`xp( -0. 5431 e V /kT )•‚ ( T ) = 36337eβ ( T ) = 36337 exp (- 0. 5431 e V / k T )
`
`
`
`1E +1
`1
`
`1E +0
`
`1E − 1
`
` [V]
` β
`
`1E − 2
`
`17.5
`
`19.5
`
`21.5
`
`23.5
`
`25.5
`
`1/kT [eV
`
`-1
`
`]
`
`Figure 3. Arrhenius plot of the β which were obtained by fitting the
`measurement data to the model.
`
`spontaneous threshold voltage shift proceeds in two phases
`with different time dependences, where the shift rate of
`threshold voltage in the first initial phase is much faster than
`that in the second long-term phase.
`In order to develop a
`new model equation for the time–temperature dependency of
`the accumulative threshold voltage shift during the first initial
`phase, we replot figure 1 in log–log scale as shown in figure 2.
`Figure 2 shows that threshold voltage shift, VT , is linearly
`proportional to t m in the initial short time and low temperature
`region. Hence, VT can be expressed as below,
` VT = βt m,
`where β and m are the bake time-independent parameters. The
`slopes of the profiles are almost same for all bake temperatures
`and independent of the bake time, which yields m ≈ 0.332
`from the average value of the slopes for each temperature in
`figure 2. On the other hand, the parameter β was found to
`be strongly dependent on the bake temperature as shown in
`figure 3, where the values of β for each temperature were
`obtained by fitting the measurement data to the model of
`equation (1) as seen in figure 2. Figure 3 shows clearly that the
`parameter β is exponentially proportional to the inverse of the
`
`(1)
`
`159
`
`the threshold voltage while the second phase has a gradual
`shift rate. We propose a new empirical model for each phase
`of the charge leakage through the interpoly ONO dielectric and
`evaluate it based on the experimental results of the threshold
`voltage shift obtained by the high-temperature baking tests.
`
`2. Experiments
`
`The stacked-gate flash EEPROM cells with ONO interpoly
`dielectric layer were fabricated using 0.35 µm CMOS.Their
`structures are similar to a conventional cell structure [11]. The
`effective channel length and width of the devices were 0.45 and
`0.65 µm, and the tunnel oxide and the effective ONO interpoly
`dielectric layer were about 10 and 25 nm thick, respectively.
`Our process for ONO stacked film was similar to that reported
`recently [12]. Firstly, the fresh 30 sample devices have been
`programmed to the predetermined threshold voltage on the
`wafer level by using the channel hot electron injection (CHEI)
`method. Cell programming was carefully adjusted such that all
`the programmed cells have the same initial program threshold
`voltage of VTP(0) = 7.0 ± 0.05 V, in order to minimize the
`sample-to-sample variation effects of the initial charge amount
`stored in each individual cell. After this initial programming,
`they were baked at one of the various temperatures ranging
`◦
`◦
`from 200
`C to360
`C for predetermined times in a heat-flow
`oven with a temperature controllability of T = ±1
`◦
`C. No
`external bias was applied on the devices during the baking
`testing which accelerates the charge leakage process. At
`the end of each bake, the shift of the threshold voltage was
`measured by using an HP4156A device parameter analyser.
`The shift of the threshold voltage due to the charge leakage
`during the bake testing is related to the charge loss amount by
` VT = − Q/CPP, where Q is the charge loss amount in
`the floating gate and CPP is the equivalent capacitance between
`the floating and control gates. The charge loss rate can then
`be characterized by the time derivative of VT .
`
`3. Results and discussion
`
`Figure 1 shows the measurement results of the accumulative
`threshold voltage shift as a function of bake time at various
`bake temperatures. As shown in the data profiles,
`the
`
`IPR2004-00108
`Exhibit MX027-1009, p. 2
`
`

`

`
`360°360°C
`
`340°340°C
`
`320°320°C
`
`300°300°C
`
`270°270°C
`
`240°240°C
`
`200°200°C
`
`6
`
`4
`
`2
`
`0
`
`∆VT [V]
`
`
`360°…360°C
`
`340°…340°C
`
`320°…320°C
`
`300°…300°C
`
`270°…270°C
`
`240°…240°C
`
`200°…200°C
`
`M o d e lModel
`
`J H Kimet al
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`∆VT [V]
`
`0
`
`20
`
`40
`
`60
`
`80
`
`100
`
`Bake Time [hrs]
`
`Figure 4. Comparison of calculated threshold voltage shift versus
`the measured threshold voltage shift during the first initial phase.
`
`bake temperature. Hence, β can be expressed by Arrhenius
`law as
`
`(2)
`
`(3)
`
`eEa / kT
`
`.
`
`(4)
`
` VT
`β0
`From equation (4), the lifetime of the test sample devices
`was found to be approximately 136 years at the operating
`◦
`temperature, 125
`C, which seems to be of good enough quality
`to satisfy the requirements for data retention.
`Figure 5 shows the replotting of figure 1 in order to find
`the model equation for VT in the second long-term phase.
`Unlike the first phase, the decrease in the threshold voltage
`can be expressed as
` VT = α Ln(t ) + β,
`where α and β are independent of the bake time. Figure 6
`shows the Arrhenius plot of the parameter α which was
`obtained at various temperatures by data fit to equation (5). It is
`clearly seen that the parameter α is exponentially proportional
`to the inverse of the absolute temperature.
`Thus,
`the
`temperature dependency of α can be expressed by Arrhenius
`law as
`
`(5)
`
`(6)
`
`α = α0 e
`−Ea / kT ,
`
`160
`
`1
`0.1
`
`1
`1
`
`10
`10
`Bake Time [hrs]
`
`100
`100
`
`1000
`1000
`
`Figure 5. Decrease in the threshold voltage versus bake time for
`various bake temperatures during the second phase in semi-log scale.
`
`
`Ξ ( T)a (T)
`= 2.1415 exp(− 0.0634 eV/kT)
`= 2 . 1 4 1 5 e x p ( - 0 . 0 6 3 4 e V /kT)
`
`1
`1
`
`]
`
`(T) [V]
`
`a
`
`0. 1
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`Temperature (1/KT) [eV
`
`−1]
`
`Figure 6. Arrhenius plot of the parameter α(T ).
`
`β (T)
`Ξ ( T)
` = 0 . 0 2 9 2 * T − 1 6 . 9 1 9
` = 0 . 0 2 9 2 * T - 1 6 . 9 1 9
`
`2.3
`
`1.4
`
`0.5
`
`-0.4
`
`-1.3
`
`-2.2
`
`(T) [V]
`
` β
`
`500
`
`530
`
`560
`
`590
`
`620
`
`650
`
`Temperature [K]
`
`Figure 7. Temperature dependence of the parameter β(T ).
`
`where α0 is a constant, Ea is the activation energy, k is the
`Boltzmann constant and T is the absolute bake temperature.
`Here, the values of α0 and Ea were determined to be 2.1415 V
`and 0.0634 eV, respectively. Similarly, the parameter β was
`obtained as a function of the bake temperature. Figure 7 shows
`
`β = β0 e
`−Ea / kT ,
`where β0 is a temperature-independent constant, Ea is the
`activation energy, T is the absolute bake temperature and k is
`Boltzmann’s constant. In addition, the values of 3.63 × 104
`for β0 and 0.54 eV for Ea were determined from the profile in
`figure 3. By putting equation (2) into equation (1), the model
`equation for VT in the first phase can be expressed as
` VT = β0t m e
`−Ea / kT .
`Figure 4 shows the simulation results using equation (3),
`comparing with the measurement results of figure 1 for various
`bake times and temperatures. As expected, the measurement
`data for various bake temperatures and times very well fitted
`the model initially, but gradually deviated from the model with
`increasing bake time. The higher the bake temperature, the
`earlier this deviation occurs. This implies that the electron
`leakage process in the first initial phase is quite different from
`that in the second long-term phase, where a different empirical
`model equation is needed. The device lifetime can be derived
`from equation (3):
`τ = exp
`
`(cid:1)
`
`(cid:2)
`
`(cid:3)(cid:4)
`
`Ln
`
`1 m
`
`IPR2004-00108
`Exhibit MX027-1009, p. 3
`
`

`

`An empirical model for charge leakage through oxide–nitride–oxide interpoly dielectric
`
`is the detrapping by the thermionic emission of electrons
`which were trapped initially at the interface between the
`bottom oxide and the internitride during the programming,
`and their movement by the hopping conduction through the
`internitride layer towards the top oxide. Leakage path k3 is
`the movement of electrons trapped during the programming
`inside the internitride layer towards the top oxide by Frenkel–
`Poole hopping conduction. Finally, leakage path k4 is the
`direct tunnelling of electrons through the thin top oxide of
`the ONO layer to the control gate after escaping from the
`interface trap sites between the internitride and top oxide by
`the thermionic emission mechanism. In the ONO dielectric
`layer of programmed cells, the nitride layer plays a key role in
`protecting the charge stored in a floating gate programmed
`cell. During the program operation, some electrons were
`injected from the floating gate into the ONO layer through
`the conductive and defective bottom polyoxide layer by the
`−1 [1, 6] and some of
`electric field, about 3.5–4.0 MV cm
`them were trapped at the interface between the bottom oxide
`and the nitride or inside the nitride layer. During baking
`testing, these initially trapped electrons prevent the electrons
`stored in the floating gate from flowing into the nitride layer
`through the bottom oxide layer in the first initial phase.
`Hence, it is believed that during the first phase of the charge
`leakage, most of the electrons move just inside the nitride layer
`and were relocated from the bottom to the top region, although
`there are few electrons which move over from the floating gate
`into the nitride layer or tunnel through the top oxide to the
`control gate. Only after the electrons trapped at the interface
`are removed will the second phase of charge leakage start,
`in which many electrons move over from the floating gate to
`the nitride layer, then flow upwards in the nitride layer and
`finally pass through the top oxide layer into the control gate by
`the direct tunnelling. Therefore, it takes time for the second
`phase to start because the electrons trapped at the interface
`must be removed during the first phase. As seen in figures 4
`and 8, the second phase starts earlier as the bake temperature
`increases, which is consistent with the above argument since
`the electrons trapped at the interface are removed more quickly
`by the thermal activation.
`In such a case,
`the threshold
`voltage decreases remarkably fast with the strong temperature
`dependency due to its high activation energy. This process
`occurs in the first initial phase as seen in figure 5. Thus,
`the high activation energy (0.54 eV) in the model implies
`that the threshold voltage shift in the initial phase is believed
`to be caused not by the leakage of electrons stored in a
`floating gate, but mainly by the detrapping and movement
`of electrons trapped at the interface between the bottom
`oxide and the nitride or inside the very trappy internitride layer
`towards the top oxide of the ONO layer (the leakage paths k2
`and k3). On the other hand, the decrease of the threshold voltage
`goes on gradually in the second phase as in figure 8, which
`implies that the dominant mechanism of charge leakage for
`the second phase is different from that for the first phase and is
`mainly due to the direct tunnelling of the electrons through
`the top oxide, which follows along the electron-leakage
`path k4 , as discussed elsewhere [14]. This is highly possible
`since the bottom polyoxide and the internitride film are more
`defective and more conductive than the top thermal oxide,
`although electron leakage proceeds simultaneously through
`
`161
`
`200°C2 0 0 C
`
`240°C2 4 0 C
`
`270°C2 7 0 C
`
`300°C3 0 0 C
`
`320°C3 2 0 C
`
`340°C3 4 0 C
`
`360°C3 6 0 C
`
`
`M o d e lModel
`
`6
`
`4
`
`2
`
`0
`
`∆VT [V]
`
`0
`
`100
`
`200
`
`300
`
`400
`
`500
`
`600
`
`700
`
`Bake Time [hrs]
`
`Figure 8. Comparison of the calculated threshold voltage shift
`versus the measured threshold voltage shift during the second
`long-term phase.
`
`
`111
`Electron
`
`Floating Gate
`
`
`
`222
`
`
`
`333
`
`Hopping
`Conduction
`
`
`
`444
`
`Control Gate
`
`Bottom Oxide
`
`Nitride
`
`Figure 9. Electron conduction mechanisms through the ONO
`interpoly dielectric in the stacked-gate flash EEPROM cell.
`
`Top Oxide
`
`that β is linearly proportional to the ambient temperature, and
`can be expressed as
`β = β0T + γ ,
`(7)
`where β0 and γ are temperature-independent constants which
`−1 and −16.919 V,
`were determined to be 0.0292 V K
`respectively.
`By putting equations (6) and (7) into equation (5), the
`model equation for the time and temperature dependence of
` VT in the second phase can be expressed as
`
` VT = α0 e−Ea / kT Ln(t ) + β0T + γ .
`(8)
`Figure 8 shows the simulation results using equation (8). As
`expected, most of the measurement data are found to fit well
`with the model in the second phase, except for some cases at
`low temperatures and also initial short time which fit well with
`the model for VT in the first phase as shown in figure 4.
`For charge leakage from the floating gate in the
`programmed stacked-gate flash EEPROM cell during the
`baking test, there are four possible mechanisms of electron
`conduction through the ONO interpoly dielectric [1, 2, 6, 13].
`As seen in figure 9, leakage path k1 is the tunnelling of the
`electrons stored in the floating gate into the internitride layer
`through the bottom oxide of the ONO layer. Leakage path k2
`
`IPR2004-00108
`Exhibit MX027-1009, p. 4
`
`

`

`J H Kimet al
`
`all the paths k1 , k2 , k3 and k4. This argument is strongly
`supported by the experimental results shown in figure 6, where
`the activation energy of VT during the second phase is
`found to be extremely low, about 0.06 eV. This is a well-
`known property of the tunnelling phenomena. In contrast, the
`activation energy of VT during the first phase was found
`to be 0.54 eV as shown in figure 3. This analysis is different
`from the previous literatures, where the long-term phase occurs
`mainly due to the leakage of the charge stored in the floating
`gate through FN tunnelling [4], the thermionic emission [8] or
`multi-phonon assisted tunnelling [15].
`
`gate occurs in the second long-term phase and the dominant
`mechanism of the charge leakage causing the threshold voltage
`shift is the direct tunnelling of the electrons through the top
`oxide of ONO layer.
`
`Acknowledgments
`
`This work was supported by the MOST through the Frontier
`21 Program for Development of Tera-level Nanoscale Devices
`and by KOSEF through the QSRC Program.
`
`4. Conclusions
`
`References
`
`In this work, we have studied the reliability problems in the
`degradation of the data retention characteristics of the stacked-
`gate flash memory devices with an ONO interpoly dielectric.
`Threshold voltage shift measured as a function of bake time at
`all tested temperatures shows that there are two distinct phases
`which have different dependences on the bake temperature
`and time. Based on the high-temperature accelerated test, an
`empirical model was developed for each phase of the threshold
`voltage shift, which explains the dominant mechanisms for the
`spontaneous charge leakage through the interpoly dielectric.
`In the first initial phase where the threshold voltage decreases
`very fast, the empirical model for the threshold shift can
`be expressed as VT = β0t m e
`−Ea / kT . The high activation
`energy (0.54 eV) in the model implies that the threshold
`shift in the first phase occurs not by the leakage of electrons
`stored in a floating gate, but due to the detrapping of electron
`trapped originally at the interface between the bottom oxide
`and internitride or inside the internitride layer and their
`movement through the internitride towards the top oxide of
`the ONO layer. In the second phase where the threshold shift
`occurs gradually, the empirical model can be expressed as
`
` VT = α0 e−Ea / kT Ln(t ) + β0T + γ . Unlike the first phase,
`it is found that the threshold shift has a weak temperature
`dependence with extremely low activation energy of 0.06 eV.
`This clearly shows that actual charge leakage from the floating
`
`[1] Pan C S, Wu K, Freiberger P, Chatterjee A and Sery G 1990
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`[15] Hermann M and Schenk A 1995 J. Appl. Phys. 77 4522
`
`162
`
`IPR2004-00108
`Exhibit MX027-1009, p. 5
`
`