`Adachi et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006461916Bl
`US 6,461,916 B1
`Oct. 8, 2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) NON-VOLATILE SEMICONDUCTOR
`MEMORY AND METHOD OF MAKING
`SAME, AND SEMICONDUCTOR DEVICE
`AND METHOD OF MAKING THE DEVICE
`
`(75)
`
`Inventors: Tetsuo Adachi, Orne; Masataka Kato,
`Koganei; Toshiakl Nishimoto,
`Higashimurayama; Nozomu Matsuzaki,
`Kokubunji; Takashi Kobayashi,
`Tokorozawa; Yoshimi Sudou, Akiruno;
`Toshiyuki Mine, Fussa, all of (JP)
`
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.:
`
`09/402,078
`
`(22) PCT Filed:
`
`Feb. 20, 1998
`
`(86) PCTNo.:
`
`PCT/JP98/00710
`
`§ 371 (c)(l),
`(2), ( 4) Date:
`
`Feb. 7, 2000
`
`(87) PCT Pub. No.: W098/44567
`
`PCT Pub. Date: Oct. 8, 1998
`
`(30)
`
`Foreign Application Priority Data
`
`Mar. 28, 1997
`Jul. 8, 1997
`
`(JP) ............................................. 9-077175
`(JP) ............................................. 9-182102
`
`(52) U.S. Cl. ........................................ 438/257; 438/197
`(58) Field of Search .................................. 438/257, 197
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,946,548 A * 8/1999 Hashimoto eta!. ........... 438/41
`2001/0002714 A1 * 6/2001 Doan
`......................... 257/316
`* cited by examiner
`Primary Examiner-Richard Elms
`Assistant Examiner-Beth E. Owens
`(74) Attorney, Agent, or Firm-Antonelli, Terry, Stout &
`Kraus, LLP
`
`(57)
`
`ABSTRACT
`
`A semiconductor device, which ensures device reliability
`especially in fine regions and enables great capacitance and
`high-speed operations, has memory cells including, in a first
`region of a main surface of a semiconductor substrate, a gate
`insulating film, a floating gate electrode, an interlayer insu(cid:173)
`lating film, a control gate electrode, and source and drain
`regions of the second conduction type arranged in a matrix,
`with a shallow isolation structure for isolating the memory
`cells. When using a shallow structure buried with an insu(cid:173)
`lating film for element isolation, the isolation withstand
`voltage in fine regions can be prevented from lowering and
`the variation in threshold level of selective transistors can be
`reduced. When the memory cells in a memory mat are
`divided by means of selective transistors, the disturb resis(cid:173)
`tance of the memory cells can be improved.
`
`(51)
`
`Int. Cl? .................... HOlL 29/788; HOlL 21!8247
`
`50 Claims, 83 Drawing Sheets
`
`130
`
`129
`
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`
`125
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`107
`
`108
`
`125 105
`
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`
`102
`
`118
`
`108
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 1 of 83
`
`US 6,461,916 B1
`
`FIG. 1
`
`DISCHARGE
`
`MEMARRAY
`
`Vee
`
`AD
`
`IPR2004-00108
`Exhibit MX027-1007, p. 2
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 2 of 83
`
`US 6,461,916 B1
`
`FIG. 2
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`
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`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 3 of 83
`
`US 6,461,916 B1
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`IPR2004-00108
`Exhibit MX027-1007, p. 4
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`
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`U.S. Patent
`US. Patent
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`Oct. 8, 2002
`Oct. 8, 2002
`
`Sheet 4 0f 83
`Sheet 4 of 83
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`US 6,461,916 B1
`US 6,461,916 B1
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`IPR2004-00108
`Exhibit MX027-1007, p. 5
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 5 of 83
`
`US 6,461,916 B1
`
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`Exhibit MX027-1007, p. 6
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`
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`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 6 of 83
`
`US 6,461,916 B1
`
`FIG. 8
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`IPR2004-00108
`Exhibit MX027-1007, p. 7
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 7 of 83
`
`US 6,461,916 B1
`
`F/(3. 10
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`IPR2004-00108
`Exhibit MX027-1007, p. 8
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 8 of 83
`
`US 6,461,916 B1
`
`FIG. 12
`
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`IPR2004-00108
`Exhibit MX027-1007, p. 9
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 9 of 83
`
`US 6,461,916 B1
`
`FIG7. 14
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`IPR2004-00108
`Exhibit MX027-1007, p. 10
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 10 of 83
`
`US 6,461,916 B1
`
`FIG. 16
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`IPR2004-00108
`Exhibit MX027-1007, p. 11
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 11 of 83
`
`US 6,461,916 B1
`
`FIG,. 18
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`Exhibit MX027-1007, p. 12
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`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 12 of 83
`
`US 6,461,916 B1
`
`FIG. 20
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`IPR2004-00108
`Exhibit MX027-1007, p. 13
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 13 of 83
`
`US 6,461,916 B1
`
`FIG. 21
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`IPR2004-00108
`Exhibit MX027-1007, p. 14
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 14 of 83
`
`US 6,461,916 B1
`
`FIG. 23
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`IPR2004-00108
`Exhibit MX027-1007, p. 15
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 15 of 83
`
`US 6,461,916 B1
`
`FIG .. 25
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`IPR2004-00108
`Exhibit MX027-1007, p. 16
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 16 of 83
`
`US 6,461,916 B1
`
`FIG. 27
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`IPR2004-00108
`Exhibit MX027-1007, p. 17
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 17 of 83
`
`US 6,461,916 B1
`
`FIG. 29
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`IPR2004-00108
`Exhibit MX027-1007, p. 18
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 18 of 83
`
`US 6,461,916 B1
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`FIG. 31
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`IPR2004-00108
`Exhibit MX027-1007, p. 19
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 19 of 83
`
`US 6,461,916 B1
`
`FIG. 33
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`IPR2004-00108
`Exhibit MX027-1007, p. 20
`
`
`
`U.S. Patent
`US. Patent
`
`Oct. 8, 2002
`Oct. 8, 2002
`
`Sheet 20 0f 83
`Sheet 20 of 83
`
`US 6,461,916 B1
`US 6,461,916 B1
`
`FIG. 35
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`|PR2004-00108
`Exhibit MX027-1007, p. 21
`
`IPR2004-00108
`Exhibit MX027-1007, p. 21
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 21 of 83
`
`US 6,461,916 B1
`
`FIG. 36
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`IPR2004-00108
`Exhibit MX027-1007, p. 22
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`
`
`U.S. Patent
`US. Patent
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`Oct. 8, 2002
`Oct. 8, 2002
`
`Sheet 22 0f 83
`Sheet 22 of 83
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`US 6,461,916 B1
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`|PR2004-00108
`Exhibit MX027-1007, p. 23
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`IPR2004-00108
`Exhibit MX027-1007, p. 23
`
`
`
`U.S. Patent
`
`Oct. 8, 2002
`
`Sheet 23 of 83
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`US 6,461,916 B1
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`IPR2004-00108
`Exhibit MX027-1007, p. 24
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`U.S. Patent
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`Oct. 8, 2002
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`Sheet 24 of 83
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`US 6,461,916 B1
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`|PR2004-00108
`Exhibit MX027-1007, p. 25
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`IPR2004-00108
`Exhibit MX027-1007, p. 25
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`U.S. Patent
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`Oct. 8, 2002
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`Sheet 25 of 83
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`US 6,461,916 B1
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`Exhibit MX027-1007, p. 26
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`Oct. 8, 2002
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`Sheet 26 of 83
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`US 6,461,916 B1
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`IPR2004-00108
`Exhibit MX027-1007, p. 27
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`Oct. 8, 2002
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`Sheet 27 of 83
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`US 6,461,916 B1
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`Exhibit MX027-1007, p. 28
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`U.S. Patent
`US. Patent
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`Oct. 8, 2002
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`Sheet 28 of 83
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`|PR2004-00108
`Exhibit MX027-1007, p. 29
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`IPR2004-00108
`Exhibit MX027-1007, p. 29
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`Oct. 8, 2002
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`US 6,461,916 B1
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`Exhibit MX027-1007, p. 30
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`Oct. 8, 2002
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`Sheet 30 of 83
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`US 6,461,916 B1
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`Exhibit MX027-1007, p. 31
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`U.S. Patent
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`Oct. 8, 2002
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`Sheet 31 of 83
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`US 6,461,916 B1
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`Sheet 51 of 83
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