(12) United States Patent
`Shukuri et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006559012B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,559,012 B2
`May 6, 2003
`
`(54) METHOD FOR MANUFACTURING
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE HAVING FLOATING GATE AND
`DEPOSITED FILM
`
`(75)
`
`Inventors: Shoji Shukuri, Koganei (JP); Norio
`Suzuki, Mito (JP); Yasuhiro Taniguchi,
`Kodaira (JP)
`
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/961,301
`
`(22)
`
`Filed:
`
`Sep. 25, 2001
`
`(65)
`
`Prior Publication Data
`
`US 2002/0009851 A1 Jan. 24, 2002
`
`Related U.S. Application Data
`
`(62) Division of application No. 09/208,019, filed on Dec. 9,
`1998, now Pat. No. 6,376,316.
`Foreign Application Priority Data
`
`(30)
`
`Dec. 9, 1997
`
`(JP) ............................................. 9-338586
`
`Int. Cl? .............................................. H01L 21/336
`(51)
`(52) U.S. Cl. ........................ 438/275; 438/287; 438/294
`(58) Field of Search ................................. 257/369, 374,
`257/392, 393, 406, 410, 411, 314, 315,
`316, 324, 338, 350; 438/201, 211, 216,
`257, 276, 287, 294, 295, 296
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,104,819 A
`5,285,096 A
`5,293,336 A
`5,514,889 A *
`5,712,178 A *
`
`4/1992 Freiberger et a!.
`2/1994 Ando eta!. ................. 257/379
`3/1994 Ishii et a!.
`.................. 438/241
`5/1996 Cho eta!. ................... 257/316
`1!1998 Cho et a!. ................... 438/201
`
`8/1998 Pio eta!. .................... 438/257
`5,792,670 A
`5,795,627 A * 8/1998 Mehta eta!. ............... 427/526
`5,907,171 A * 5/1999 Santin eta!. ............... 257/315
`5,911,105 A * 6/1999 Sasaki ........................ 438/258
`5,917,222 A * 6/1999 Smayling eta!. ........... 257/370
`5,966,616 A
`10/1999 Woerlee ..................... 438/424
`5,989,962 A
`11/1999 Holloway eta!. .......... 438/275
`6,025,234 A
`2/2000 Chou ......................... 438/279
`6,037,201 A
`3/2000 Tsai et a!. ................... 438/197
`6,133,093 A * 10/2000 Prinz et a!. ................. 438/257
`6,194,320 B1 * 2/2001 Oi .............................. 438/703
`
`FOREIGN PATENT DOCUMENTS
`403105981 A * 5/1991
`JP
`411068070 A * 3/1999
`JP
`* cited by examiner
`
`Primary Examiner-Wael M Fahmy
`Assistant Examiner---Hoai Pham
`(74) Attorney, Agent, or Firm-Antonelli, Terry, Stout &
`Kraus, LLP
`
`(57)
`
`ABSTRACT
`
`A method for manufacturing a semiconductor integrated
`circuit device including a first field effect transistor having
`a gate insulating film formed over a first element forming
`region of a main surface of a semiconductor substrate; and
`a second field effect transistor having a gate insulating film
`formed over a second element forming region of the main
`surface of the semiconductor substrate and made thinner
`than the gate insulating film of the first field effect transistor.
`The method comprises the steps of forming a thermally
`oxidized film over a first element forming region and a
`second element forming region of the main surface of the
`semiconductor substrate; forming a deposited film over the
`main surface of the semiconductor substrate including said
`thermally oxidized film; removing the deposited film and
`said thermally oxidized film from over the second element
`forming region; and forming a thermally oxidized film over
`the second element forming region to form a gate insulating
`film individually over the first element forming region and
`the second element forming region.
`
`32 Claims, 36 Drawing Sheets
`
`65
`
`64
`'6362'
`/68
`
`67
`
`55
`
`57
`
`56
`
`51
`
`

`

`U.S. Patent
`US. Patent
`
`May 6,2003
`May 6, 2003
`
`Sheet 1 of 36
`Sheet 1 0f 36
`
`US 6,559,012 B2
`US 6,559,012 B2
`
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`|PR2004-00108
`Exhibit MX027-1005, p. 2
`
`IPR2004-00108
`Exhibit MX027-1005, p. 2
`
`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 2 of 36
`
`US 6,559,012 B2
`
`FIG. 2
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`IPR2004-00108
`Exhibit MX027-1005, p. 3
`
`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 3 of 36
`
`US 6,559,012 B2
`
`FIG. 4
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`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 4 of 36
`
`US 6,559,012 B2
`
`FIG. 6
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`
`IPR2004-00108
`Exhibit MX027-1005, p. 5
`
`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 5 of 36
`
`US 6,559,012 B2
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`Exhibit MX027-1005, p. 6
`
`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 6 of 36
`
`US 6,559,012 B2
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`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 7 of 36
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`US 6,559,012 B2
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`

`

`U.S. Patent
`US. Patent
`
`May 6, 2003
`May 6, 2003
`
`Sheet 10 0f 36
`Sheet 10 of 36
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`US 6,559,012 B2
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`IPR2004-00108
`Exhibit MX027-1005, p. 11
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`

`

`U.S. Patent
`US. Patent
`
`May 6,2003
`May 6, 2003
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`Sheet 11 of 36
`Sheet 11 0f 36
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`U.S. Patent
`
`May 6, 2003
`
`Sheet 15 of 36
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`US 6,559,012 B2
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`

`U.S. Patent
`US. Patent
`
`May 6, 2003
`May 6, 2003
`
`Sheet 17 of 36
`Sheet 17 0f 36
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`US 6,559,012 B2
`US 6,559,012 B2
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`IPR2004-00108
`Exhibit MX027-1005, p. 18
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`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 18 of 36
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`US 6,559,012 B2
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`May 6,2003
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`May 6, 2003
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`U.S. Patent
`US. Patent
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`May 6, 2003
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`Sheet 26 0f 36
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`Exhibit MX027-1005, p. 27
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`Exhibit MX027-1005, p. 27
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`U.S. Patent
`US. Patent
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`May 6, 2003
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`Sheet 27 of 36
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`US. Patent
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`May 6, 2003
`May 6, 2003
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`Sheet 28 of 36
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`May 6, 2003
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`U.S. Patent
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`May 6, 2003
`May 6, 2003
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`Sheet 32 0f 36
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`

`U.S. Patent
`US. Patent
`
`May 6, 2003
`May 6, 2003
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`Sheet 34 of 36
`Sheet 34 0f 36
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`US 6,559,012 B2
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`Exhibit MX027-1005, p. 35
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`U.S. Patent
`
`May 6, 2003
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`Sheet 35 of 36
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`US 6,559,012 B2
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`

`

`U.S. Patent
`
`May 6, 2003
`
`Sheet 36 of 36
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`US 6,559,012 B2
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`

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`US 6,559,012 B2
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`1
`METHOD FOR MANUFACTURING
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE HAVING FLOATING GATE AND
`DEPOSITED FILM
`
`This application is a Divisional application of Ser. No.
`09/208,019, filed Dec. 9, 1998 now U.S. Pat. No. 6,376,316,
`a Continued Prosecution Application (CPA) thereof having
`been filed Aug. 13, 2001.
`
`FIELD OF THE INVENTION
`
`The present invention relates to a semiconductor inte(cid:173)
`grated circuit device and, more particularly, to a technique
`which is effective when applied to a semiconductor inte(cid:173)
`grated circuit device including a plurality of kinds of field
`effect transistors having gate insulating films of different
`thicknesses.
`
`BACKGROUND OF THE INVENTION
`
`One of the techniques supporting the high integration of
`a semiconductor memory is known as element isolation. The
`element isolation of a semiconductor integrated circuit(cid:173)
`device using the 0.25-microns technique, such as a random
`access memory (hereinafter abbreviated to the DRAM) of 64
`Mbits, has been developed from the LOCOS (Local Oxida(cid:173)
`tion of silicon) element isolation of the prior art to the
`so-called groove type element isolation, in which element
`forming regions are insulated and isolated by forming
`grooves in the element isolating regions of a silicon sub(cid:173)
`strate and by forming a buried insulating film in the grooves.
`This groove type element isolation enables an element
`isolation length of 0.3 microns or less, which has been
`impossible to achieve by the LOCOS element isolation,
`thereby to improve the degree of memory isolation greatly.
`Meanwhile, in addition to the market needs for a lower
`voltage and small power consumption, the rapid spread of
`portable devices, such as the PDAs (Personal Digital
`Assistants) and electronic still cameras, has intensified the
`demand for the simultaneous on-chip location of the ele(cid:173)
`ments which have been formed in different chips in the prior
`art. For example, microcomputers have been manufactured
`having a built-in flash memory or microcomputers having a
`built-in DRAM of an intermediate capacity have been
`manufactured.
`
`SUMMARY OF THE INVENTION
`
`45
`
`2
`film having a thickness of 4 to 5 [nm] (for 1.8 [V]); a gate
`insulating film having a thickness of 7 to 10 [nm] for 3.3
`[V]); and a gate insulating film having a thickness of 15 to
`25 [ nm] (for a flash memory). In short, it is necessary to form
`5 gate insulating films having three different thicknesses.
`We have discovered the following problem by investigat(cid:173)
`ing the technique used when two kinds of gate insulating
`films having different thicknesses are separately formed over
`two elements forming regions of the silicon substrate, insu-
`10 lated and isolated by the aforementioned groove type ele(cid:173)
`ment isolation. This problem will be described with refer(cid:173)
`ence to FIGS. 40(A) to 46. Of FIGS. 40(A) to 46, FIGS.
`40(A) to 44 are sections for explaining the problem, FIGS.
`40(A) to 42 are sections (corresponding to a later-described
`15 FIG. 2) of a field effect transistor, taken in the gate length
`direction, and FIGS. 43 and 44 are sections (corresponding
`to a later description referring to FIG. 3) of a field effect
`transistor, taken in the gate width direction. FIG. 45 is a
`diagram for comparing the breakdown voltage distribution
`20 (a) of a capacitor with the groove type element isolation and
`the breakdown voltage distribution (b) of a capacitor with
`the LOCOS element isolation. FIG. 46 is a diagram for
`comparing the sub-thresh characteristics (a) of a field effect
`transistor with the groove type element isolation and sub-
`25 thresh characteristics (b) of a field effect transistor with the
`LOCOS element isolation. In FIG. 45, the abscissa indicates
`a capacitor gate applied voltage, and the ordinate indicates
`the cumulative number of defects. In FIG. 46, the abscissa
`indicates the gate voltage, and the ordinate indicates the
`30 drain current.
`First, as shown in FIG. 40(A), the groove type element
`isolation is achieved by forming grooves 152 for defining a
`first element forming region and a second element forming
`region in element isolating regions of a main surface of a
`35 silicon substrate 151, and subsequently by forming a buried
`insulating film 153 of a silicon oxide film in the grooves 152.
`After this, an impurity introducing buffer insulating film 154
`is formed over the first element forming region and the
`second element forming region. After this, channel implan-
`40 tation layers 155A and 155B for controlling the threshold
`voltages of the field effect transistors are individually
`formed in the individual surface layers of the first element
`forming region and the second element forming region.
`Next, the buffer insulating film 154 is removed, and
`thermal oxidation is then executed to form a gate insulating
`film 156 made of a thermally oxidized (Si0 2 ) film having a
`thickness of about 20 [ nm ], over the first element forming
`region and the second element forming region, as shown in
`FIG. 40(B).
`Next, a mask 157 is formed by using the photolitho(cid:173)
`graphic technique so as to cover the first element forming
`region, while leaving the second element forming region
`open.
`Next, the mask 157 is used as an etching mask to remove
`the gate insulating film 156 from over the second element
`forming region by a wet-etching method using an aqueous
`solution of hydrofluoric acid, as shown in FIG. 41(C).
`Next, the mask 157 is removed, and thermal oxidation is
`executed to form a gate insulating film 158 of a thermally
`oxidized (Si0 2) film having a thickness of about 5 [nm],
`over the second element forming region, as shown in FIG.
`41(D). At this step, the gate insulating film 156 and the gate
`insulating film 158 of different thicknesses can be separately
`formed over the first element forming region and the second
`element forming region which are insulated and isolated by
`the groove type element isolation.
`
`50
`
`On these semiconductor integrated circuit devices having
`devices of different functions, there are mounted a plurality
`of kinds of field effect transistors having different operating
`voltages. For the operations to write/erase information
`in/from the flash memory, for example, a voltage as high as
`15 to 20 [V] is required, so that in part of the peripheral
`circuits, field effect transistors having a gate insulating film
`with a thickness of 15 to 25 [ nm] capable of withstanding 55
`such a voltage application are used. In the logic circuit
`section of the microcomputer operating at an ordinary
`voltage of 3.3 [V], there are used field effect transistors
`having a gate insulating film with a thickness of 7 to 10
`[ nm]. In order to realize highs-peed operation at a supply 60
`voltage as low as about 1.8 [V] in a microcomputer with a
`built-in flash memory according to the 0.25 micron tech(cid:173)
`nique of recent years, there are used in the logic circuit
`section, field effect transistors which have a gate insulating
`film with a thickness of 4 to 5 [ nm]. In order that the 65
`input/output units may operate also at 3.3 [V], it is necessary
`to form gate insulating films of three types: a gate insulating
`
`IPR2004-00108
`Exhibit MX027-1005, p. 38
`
`

`

`US 6,559,012 B2
`
`3
`Next, gate electrodes 159 of a polycrystalline silicon film
`doped with an impurity are individually formed over the first
`element forming region and the second element forming
`region. After this, a pair of semiconductor regions 160 for
`the source region and the drain region are formed in the 5
`surface layer of the first element forming region. After this,
`a pair of semiconductor regions for the source region and the
`drain region are formed in the surface layer of the second
`element forming region. Thus, there are formed a field effect
`transistor Q12 and a field effect transistor Q13 having gate 10
`insulating films of different thicknesses, as shown in FIG.
`42. Here, the individual gate electrodes of the field effect
`transistors Q12 and Q13 are so formed that their gate
`electrodes in the gate width direction are led out over the
`buried insulating film 153, as shown in FIGS. 43 and 44.
`In the separate formation of the gate insulating films by
`the technique of the prior art, when the gate insulating film
`156 is removed from the second element forming region by
`a wet-etching method, the buried insulating film 153 buried
`in the grooves 152 is simultaneously etched off, as shown in 20
`FIG. 41(C). As a result, a step exposing the side faces of the
`second element forming region is formed in the end portions
`of the element isolating regions between the second element
`forming region and the element isolating region. According
`to the experiments made by the inventors, a step 25 [ nm] is 25
`formed in the case of the gate insulating film, which is
`formed so as to have a thickness of 4.5 [nm] over the second
`element forming region. There are two major problems
`caused by this step.
`The first problem is that the gate insulating film 158 is 30
`thinned by the mechanical stress concentration on the
`stepped portion, as indicated by arrow 162 in FIG. 44, at the
`end portions of the element isolating regions between the
`second element forming region and the element isolating
`region, so that the reliability of the gate insulating film 158 35
`is deteriorated. In the groove element isolation, as shown in
`FIG. 45 by characteristic (a), the breakdown voltage is
`lowered by 5 to 10% from that of the LOCOS element
`isolation, as shown in FIG. 45 by characteristic (b).
`The second problem is that the characteristics of the field 40
`effect transistor Q13 are varied because the channel implan(cid:173)
`tation concentration in the vicinity of the bottom of the step
`on the side faces of the second element forming region drops
`to a lower level than that of the channel implantation layer
`155b of the fiat portion, as indicated by arrow 163 in FIG. 45
`44. In the groove type element isolation, as shown in FIG.
`46 by characteristic (a), the phenomenon called a kink in
`which the voltage current characteristics change in the
`course occurs, causing problems, i.e., a drop in the threshold
`voltage of the field effect transistor Q13, and a variation 50
`thereof.
`An object of the invention is to provide a technique which
`is capable of enhancing the reliability of a semiconductor
`integrated circuit device which includes a plurality of kinds 55
`of field effect transistors having gate insulating films of
`different thicknesses.
`The above-specified and other objects and novel features
`of the invention will become apparent from the following
`description to be made with reference to the accompanying 60
`drawings.
`A representative aspect of the invention to be described
`herein will be summarized in the following.
`There is provided a method for manufacturing a semi(cid:173)
`conductor integrated circuit device including a first field
`effect transistor having a gate insulating film formed over a
`first element forming region of a main surface of a semi-
`
`4
`conductor substrate, and a second field effect transistor
`having a gate insulating film formed over a second element
`forming region of the main surface of the semiconductor
`substrate and which is made thinner than the gate insulating
`film of the first field effect transistor. The manufacturing
`method comprises the steps of forming a thermally oxidized
`film over the first element forming region and the second
`element forming region of the main surface of the semicon(cid:173)
`ductor substrate; subsequently forming a deposited film over
`the main surface of the semiconductor substrate including
`the thermally oxidized film; subsequently removing the
`deposited film and the thermally oxidized film from over the
`second element forming region; and subsequently forming a
`thermally oxidized film over the second element forming
`15 region to form a gate insulating film individually over the
`first element forming region and the second element forming
`region.
`The first element forming region and the second element
`forming region are individually insulated and isolated by
`grooves, which are formed in the element isolating regions
`of the main surface of the semiconductor substrate, and a
`buried insulating film which is buried in the grooves.
`By the aforementioned means, when the deposited film
`and the thermally oxidized film formed over the second
`element forming region are removed, the etching rate of the
`buried insulating film can be reduced to an extent corre(cid:173)
`sponding to the thickness of the deposited film because the
`buried insulating film is covered with the deposited film, so
`that it is not etched until the deposited film is removed. As
`a result, the step formed at the end portions of the element
`isolating regions between the second element forming
`region and the element isolating region can be reduced to
`avoid the deterioration and the characteristic variation of the
`gate breakdown voltage, which might otherwise be caused
`by the step, of the field effect transistors. As a result, it is
`possible to enhance the reliability of the semiconductor
`integrated circuit device.
`As the ratio of the thickness of the deposited film to the
`thickness of the gate insulating film formed over the first
`element forming region increases, the thermally oxidized
`film formed over the second element forming region is made
`thinner, so that the etching rate of the buried insulating film
`can be reduced. The etching rate of the buried insulating film
`is increased in proportion to the thickness of the thermally
`oxidized film.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a schematic top plan view showing two field
`effect transistors mounted in a semiconductor integrated
`circuit device representing an Embodiment 1 according to
`the invention;
`FIG. 2 is a section taken along line A-A of FIG. 1;
`FIG. 3 is a section taken along line B-B of FIG. 1;
`FIG. 4 is a section taken along line C-C of FIG. 1;
`FIG. 5 is a section for illustrating a method for manufac(cid:173)
`turing the semiconductor integrated circuit device;
`FIG. 6 is a section for illustrating the method for manu(cid:173)
`facturing the s