(12)
`
`United States Patent
`Lee
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,258,648 B1
`Jul. 10, 2001
`
`US006258648B1
`
`(54) SELECTIVE SALICIDE PROCESS BY
`REFORMATION ()F SILICON NITRIDE
`SIDEWALL SPACERS
`
`9/1997 Lee ....................................... .. 437/41
`5,672,527
`2/1998 Yoo et a1.
`438/238
`5,719,079
`5,792,684 * 8/1998 Lee et a1. .
`438/238
`
`5,807,779 * 9/1998 LiaW . . . . . . . .
`
`. . . .. 438/279
`
`(75) Inventor: Yong Meng Lee, Singapore (SG)
`
`6,025,267 * 2/2000 Pey et a1. ........................... .. 438/656
`
`(73) Assignee: Chartered Semiconductor
`Manufacturing Ltd., Singapore (SG)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`* cued by exammer
`
`_
`Primary Examiner—Jey Tsa1
`(74) Attorney, Agent, 0" F i" m—G@0rg@ 0- Sane; Rosemary
`L- S Plke
`(57)
`
`ABSTRACT
`
`(21) Appl. No.: 09/246,292
`_
`_
`Feb‘ 8’ 1999
`(22) Flled'
`(51) Int. c1.7 ............................................... .. H01L 21/8242
`(52) us CL
`438/238. 438/649, 438/253
`(58) Field of
`’438 038 ’253_256
`~~~~~~~~~~~~ "
`""""""""""""" "
`43’8/648_686’
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`3/1990 Nasr
`..
`4/1996 Davies et a1. .
`9/1997 Tsai et a1. .......................... .. 438/199
`
`437/44
`
`4 912 061
`5:510:648
`5,668,024
`
`A neW method of forming selective salicide structures is
`described Whereby robust salicide structures are formed on
`exposed logic FET’s, While blocking salicide formation on
`memory FET’S- Thus, Yielding logic FET’S With robust
`salicide structures Which exhibit loW sheet rho lines and
`contacts, While blocking salicide formation on the sensitive
`memory FET’s Which operate at loW voltage and have loW
`leakage, shalloW junctions. A conformal layer of thick
`silicon nitride in conjunction With a salicide blockout mask
`forms robust selective salicide structures. These structures
`exhibit loW leakage and lack leakage problems caused by
`bridging, silicide ribbons or stringers.
`
`8 Claims, 4 Drawing Sheets
`
`12 1O
`
`3
`Logic FET
`
`6
`
`6
`
`5
`Memory FET
`
`

`

`U.S. Patent
`
`Jul. 10, 2001
`
`Sheet10f4
`
`US 6,258,648 B1
`
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`Memory FET
`Logic FET
`7B
`FIG.
`— P'riov" A'rt
`
`1
`6
`
`IPR2004-00108
`Exhibit MX027-1004, p. 2
`
`

`

`U.S. Patent
`
`Jul. 10, 2001
`
`Sheet 2 0f 4
`
`US 6,258,648 B1
`
`10 12
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`Memory FET
`
`IPR2004-00108
`Exhibit MX027-1004, p. 3
`
`

`

`U.S. Patent
`
`Jul. 10, 2001
`
`Sheet 3 0f 4
`
`US 6,258,648 B1
`
`10
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`12
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`
`IPR2004-00108
`Exhibit MX027-1004, p. 4
`
`

`

`U.S. Patent
`
`Jul. 10, 2001
`
`Sheet 4 0f 4
`
`US 6,258,648 B1
`
`3410 321234
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`12 10
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`
`FIG. 6
`
`IPR2004-00108
`Exhibit MX027-1004, p. 5
`
`

`

`US 6,258,648 B1
`
`1
`SELECTIVE SALICIDE PROCESS BY
`REFORMATION OF SILICON NITRIDE
`SIDEWALL SPACERS
`
`FIELD OF THE INVENTION
`
`This invention relates to a method of fabrication used for
`semiconductor integrated circuit devices, and more speci?
`cally to a method Whereby a selective salicide process forms
`salicide on exposed logic FET’s, While blocking salicide
`formation on memory FET’s.
`
`DESCRIPTION OF PRIOR ART
`
`In the fabrication of semiconductor integrated circuits the
`salicide process is Well documented for MOSFET and
`CMOS device formation. Methods are presented Which
`differ in the number of masking steps and processing steps
`from the present invention.
`US. Pat. No. 5,672,527 to Lee teaches a method for
`fabricating an electrostatic discharge protection circuit. The
`invention describes a process that features only one photo
`mask to form ESD protection circuit Without the salicide and
`a LDD, lightly doped drain structure.
`US. Pat. No. 5,719,079 to Yoo et al describes a salicide
`process for an embedded logic device. A method forming a
`local interconnect in an SRAM simultaneously With the
`formation of a salicide in logic devices is described.
`US. Pat. No. 5,668,024 to Tsia et al is a method to form
`CMS devices With a dual sideWall insulator spacers to
`reduce salicide bridging, as Well as, using these regions for
`pocket implantation regions. The pocket implantation
`regions are used to reduce punch-through leakage.
`US. Pat. No. 5,510,648 to Davies et al shoWs a process
`for forming salicide With a gate and insulating sideWall
`spacers of oxide, nitride. The patent teaches that the insu
`lated gate device formed is Well suited for the design of loW
`voltage circuits due to the small variations of threshold
`voltage.
`US. Pat. No. 4,912,061 to Nasr teaches a method of
`fabricating CMOS devices using salicide process using a
`disposable silicon nitride spacer, metal silicide and a single
`implant step for source, drain and gate. Dual sideWall
`spacers of oxide/nitride are described With the nitride spacer
`being removed subsequently.
`
`SUMMARY OF THE INVENTION
`
`It is a general object of the present invention to provide an
`improved method of forming an integrated circuit in Which
`a selective salicide process forms salicide on exposed logic
`FET’s, While blocking salicide forming on memory FET’s.
`Thus, yielding logic FET’s With robust salicide structures
`Which exhibit highly conductive lines and contacts, While
`blocking salicide formation on the sensitive memory FET’s
`Which operate at loW voltage and have loW leakage, shalloW
`junctions. A conformal layer of thick silicon nitride in
`conjunction With a salicide blockout mask forms robust
`selective salicide structures. These structures shoW loW
`leakage and lack the usual problems associated With con
`ventional salicide processing, such as, silicide bridging,
`“ribbons” or “stringers”.
`In accordance With the present invention, the above and
`other objectives are realiZed in the ?rst embodiment of the
`present invention by using a method of fabricating robust
`selective, salicide structures using a second thick conformal
`layer of dielectric Which is refractory and can be selectively
`etched compared With the etch rate of silicon oxide. This
`
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`2
`thick conformal layer of refractory dielectric forms a sali
`cide mask, Whereby logic FET’s receive the salicide process
`and memory FET’s are protected by the salicide mask.
`Hence, a selective salicide process is described in the present
`invention.
`The folloWing process information is provided as a back
`ground to the present invention. Prior to said second thick
`conformal layer of refractory dielectric, conventional pro
`cessing is provided. For example, a ?rst conformal silicon
`nitride layer is deposited on oxidiZed polysilicon gate struc
`tures. Anisotropically etch of the silicon nitride layer forms
`sideWall spacers on the sideWalls of said oxidiZed polysili
`con gate structures. Exposed source and drain regions are
`then ion implanted forming lightly doped source/drain
`regions underneath the sideWall structures. Rapid thermal
`annealing activates the ion implanted dopants While limiting
`diffusion. The said silicon nitride spacers are etched off
`leaving oxidiZed polysilicon gate structures With implanted
`source and drain regions. Both logic and memory FET’s are
`processed simultaneously at this stage of the process.
`In the ?rst embodiment of the present invention, the
`second thick conformal layer of refractory dielectric mate
`rial is any material Which meets the general requirements for
`the process. One of the key requirements is that it must have
`a high etch selectivity to that of silicon dioxide. In the
`second embodiment the material is listed as thick silicon
`nitride. This second conformal material protects the memory
`FET’s from salicidation.
`In the second embodiment of the present invention, the
`above and other objectives are realiZed by using the method
`of selective salicide formation by depositing a second con
`formal thick layer of silicon nitride, in the thickness range of
`approximately 500 Angstroms to approximately 1500 Ang
`stroms. Said second thick layer of silicon nitride is patterned
`by photolithography by applying a salicide blockout mask to
`the memory FET’s. Anisotropic silicon nitride RIE
`(Reactive Ion Etch) etching forms robust silicon nitride
`sideWall spacer structures on the sideWalls of the oxidiZed
`silicon nitride gate structures. Greater integrity of the side
`Wall spacer is achieved With the said thick silicon nitride
`process.
`The blockout photolithography mask is subsequently
`removed by stripping the resist. Salicide formation process
`is applied by depositing metals, such as, Ti, Ta, Mo, W, Co,
`Ni, Pd, Pt onto the substrate. LoW electrical resistance, good
`adhesion and loW mechanical stress are some of the more
`desirable properties in choosing Which metal to deposit and
`by What method to deposit the silicide metal. Silicide
`formation occurs by diffusion of silicon atoms through the
`polysilicon to the surface Where the reaction With the metal
`occurs. In some instances, a tWo stop RTA, Rapid Thermal
`Anneal, in an inert atmosphere converts the silicide from
`C49 crystal structure to the preferred C54 loW electrical
`resistance structure. Salicide formation occurs in the
`exposed polysilicon areas and at the top of the source/drain
`areas, hence it is a self-aligned process. Deleterious
`bridging, Which is silicide formation betWeen the polysilicon
`and closely spaced source/drain regions is prevented by the
`robust silicon nitride sideWall structures.
`The thick silicon nitride, the silicide protection layer and
`nitride sideWall spacers are subsequently removed by selec
`tively etching the nitride While leaving the oxide layers and
`salicide layers intact. This is one of the key aspects of the
`present invention.
`The salicide formation takes place on all the exposed
`silicon surfaces, that is, at the top of the polysilicon gate and
`
`IPR2004-00108
`Exhibit MX027-1004, p. 6
`
`

`

`US 6,258,648 B1
`
`3
`in the diffusion regions. However, the silicon nitride spacers
`that see exposure to the selective salicide processing metal
`do not react to form silicide.
`The silicon oxide loss or recess in the ?eld isolation
`region is signi?cantly greater for conventional processing.
`The reason for this is due to fact that the prior art or
`traditional process etches silicon oxide to form the salicide
`mask (self-aligned silicide mask). Therefore, the ?eld silicon
`oxide, is also etched in the traditional process etch. This
`non-selective etch results in a recess in the ?eld oxide
`region. These effects expose the silicon at the edge of the
`active source/drain regions and cause deleterious silicide
`formation to occur. This results in leakage around the
`source/drain. The present invention describes a process
`Whereby thick dielectric silicon nitride can be the refractory
`material that forms the salicide mask and it can be selec
`tively etched compared With silicon oxide. The selectively
`etch process minimiZes the leakage problem.
`In addition, after the salicide process is complete, said
`thick silicon nitride layer can be anisotropically etched to
`form sideWall spacers on the memory devices.
`
`15
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The object and other advantages of this invention are best
`described in the preferred embodiments With reference to the
`attached draWings that include:
`FIGS. 1A—1B Which in cross-sectional representation
`illustrate the prior art methods Whereby selective salicide
`formations result in leakage on the sideWall spacers and
`residual bridging, “ribbons” or “stringers” associated With
`silicide formation in undesirable regions.
`The method of the preferred embodiment of the present
`invention in cross-sectional representation is illustrated in
`starting structure in FIG. 1A and proceeding from FIGS. 2
`through to FIG. 6.
`
`25
`
`35
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`4
`covering both types of FET’s, logic FET 3 and memory FET
`5. The silicon nitride 26 is deposited by LPCVD (LoW
`Pressure Chemical Vapor Deposition). A silicide blockout
`mask 28 in FIG. 4 serves as a nitride etch protection mask
`for FET memory devices, While robust nitride sideWall
`spacers 30 in FIG. 5 are formed by an anisotropic etch using
`RIE, Reactive Ion Etching, on FET logic devices. The
`blockout mask 28 shoWn in FIG. 5 is subsequently removed
`by stripping the resist. Salicide formation process is applied
`by depositing metals, such as, Ti, Ta, Mo, W, Co, Ni, Pd, Pt
`onto the substrate. LoW electrical resistance, good adhesion
`and loW mechanical stress are some of the more desirable
`properties in choosing Which metal to deposit. Silicide
`formation occurs by diffusion of silicon atoms through the
`polysilicon to the surface. In some instances, a tWo step
`RTA, Rapid Thermal Anneal, in an inert atmosphere con
`verts the silicide from C49 crystal structure to the preferred
`C54 loW electrical resistance structure. Salicide formation
`occurs in the exposed polysilicon areas and at the top of the
`source/drain areas, hence it is a self-aligned process. Del
`eterious bridging, Which is silicide formation betWeen the
`polysilicon and closely spaced source/drain regions is pre
`vented by the robust silicon nitride sideWall structures.
`The thick silicon nitride 26 silicide protection layer and
`nitride sideWall spacers 34, as shoWn in FIG. 6 are subse
`quently removed by selectively etching the nitride While
`leaving the oxide layers and salicide layers intact. This is one
`of the key aspects of the present invention.
`In FIG. 6 selective salicide formation 32 is shoWn on all
`exposed silicon surfaces, that is, at the top of the polysilicon
`gate and in the diffusion regions. The silicon nitride spacers
`34 that see exposure to the selective salicide processing
`metal do not react to form silicide.
`Referring again to FIG. 6, sketched is the loW electrical
`leakage region 36 Which is formed as a direct result of the
`improved selective salicide process. Comparing the prior art
`structure 24 in FIG. 1B and structure 36 in FIG. 6, it can be
`plainly seen that the silicon oxide loss or recess in the ?eld
`isolation region is signi?cantly greater for structure 24. The
`reason for this effect is due to fact that the prior art or
`traditional process etches silicon oxide to form the salicide
`mask (self-aligned silicide mask). Therefore, the ?eld silicon
`oxide is also etched in the traditional process etch. This
`non-selective etch results in a recess in the ?eld oxide region
`24, FIG. 1B. These effects expose the silicon at the edge of
`the active source/drain regions Where deleterious silicide
`formation occurs. This results in junction leakage. The
`present invention describes a process Whereby silicon nitride
`can be the material that forms the salicide masking and can
`be selectively etched compared With the etch rate of silicon
`oxide. The selectively etch process minimiZes the leakage
`problem.
`In addition, after the salicide process is complete, said
`thick silicon nitride layer can be anisotropically etched to
`form sideWall spacers on the memory devices.
`While the invention has been particularly shoWn and
`described With reference to the preferred embodiments
`thereof, it Will be understood by those skilled in the art that
`various changes in form and details may be made Without
`departing from the spirit and scope of the invention.
`What is claimed is:
`1. Amethod of forming MOSFET semiconductor devices
`on a semiconductor substrate using a selective salicide
`process for logic devices and not on memory devices
`comprising:
`providing a semiconductor silicon substrate having ?eld
`oxide regions for MOSFET device isolation;
`
`Referring noW more particularly to FIG. 1A, there is
`shoWn in cross-section the starting structures of both prior
`art and the present invention. FIG. 1A sketches tWo FET
`structures, the one on the left-hand side represents a logic
`FET 3 and the one on the right-hand side represents a
`memory FET 5. The substrate 2 is a semiconductor substrate
`With implanted source and drain regions 6. Note the lightly
`doped portions of the source and drains 6 are the necked
`doWn, shalloW junctions shoWn in the ?gures. Thick ?eld
`oxide 4 electrically isolates the FET’s. Polysilicon gate
`structures 10 With gate oxide 8 and polysilicon oxide layer
`12 are sketched. Silicon nitride sideWall spacers are pro
`vided and are depicted in FIG. 1A.
`In FIG. 1B is sketched the type of FET structure that
`results from Prior Art processing using a thick oxide layer 16
`and salicide blockout mask 18. Salicide is formed selec
`tively on the logic FET 3 in exposed silicon and polysilicon
`regions 22 With silicon nitride sideWall spacers 14 and TEOS
`deposited oxide sideWall spacers 20. Electrical leakage paths
`24 due to silicide bridging tend to develop near the edges of
`the FET structure.
`The silicon nitride sideWall spacers 14 shoWn in FIG. 1A
`are removed by an etching process, such as, a Wet etch in hot
`phosphoric acid. FIG. 2 shoWs the polysilicon gate struc
`tures 10 and the polysilicon oxide 12. FIG. 3 shoWs a thick,
`layer of silicon nitride 26 ranging in thickness from approxi
`mately 500 Angstroms to approximately 1500 Angstroms,
`
`45
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`55
`
`65
`
`IPR2004-00108
`Exhibit MX027-1004, p. 7
`
`

`

`US 6,258,648 B1
`
`5
`forming gate oxide and polysilicon gate structures on both
`said logic devices and memory devices;
`thermally oxidizing said polysilicon gate structures to
`form silicon oxide on said polysilicon gate structures;
`depositing a ?rst conformal dielectric layer over said
`substrate;
`masking and anisotropically reactive ion etching (RIE)
`said dielectric layer to form gate sideWall spacers on
`said polysilicon gate structures;
`patterning source/drain regions Whereby said polysilicon
`gates are self-aligned;
`forming by implantation source/drain regions associated
`With said polysilicon gate structures;
`removing said dielectric sideWall spacers; depositing a
`second conformal dielectric layer over said substrate;
`forming a salicide blockout mask over said memory
`devices, While exposing logic FET devices using said
`second conformal dielectric layer;
`etching anisotropically said second dielectric layer to
`form second sideWall spacers on said logic devices;
`removing said salicide blockout mask;
`applying a salicide process of metal deposition and form
`ing self-aligned silicide structures on exposed said
`logic FET devices, Whereby there is formed loW elec
`trical resistance lines and contacts on polysilicon gates
`and source/drain regions, While silicide formation is
`blocked on memory FET devices, by said second
`dielectric layer.
`2. The method of claim 1, Wherein said second dielectric
`layer ranges in thickness betWeen approximately 500 Ang
`stroms to 1500 Angstroms, close in thickness to the ?rst
`dielectric layer.
`3. The method of claim 1, Wherein said blockout mask can
`be any high temperature, refractory dielectric material that
`that is capable of being anisotropically reactively ion etched,
`non-reactive to silicide formation and selectively etched to
`silicon oxide.
`4. The method of claim 1, Wherein said salicide process
`can be comprised of titanium or other suitable metals
`selected from the group consisting of Ta, Mo, W, Co, Ni, Pd
`and Pt.
`5. Amethod of forming MOSFET semiconductor devices
`on a semiconductor substrate using a selective salicide
`process for logic devices and not on memory devices
`comprising:
`
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`forming a semiconductor silicon substrate having ?eld
`oxide regions for MOSFET device isolation;
`forming for gate oxide and polysilicon gate structures on
`both said logic devices and memory devices;
`thermally oxidiZing said polysilicon gate structures to
`form silicon oxide on said polysilicon gate structures;
`depositing a ?rst conformal silicon nitride layer over said
`substrate;
`masking and anisotropically reactive ion etching (RIE)
`said silicon nitride layer to form gate sideWall spacers
`on said polysilicon gate structures;
`patterning source/drain regions Whereby said polysilicon
`gates are self-aligned;
`forming by implantation source/drain regions associated
`With said polysilicon gate and sideWall spacer struc
`tures;
`removing said silicon nitride sideWall spacers;
`depositing a second conformal silicon nitride layer over
`said substrate;
`forming a salicide blockout mask over said memory
`devices, While exposing logic FET devices using said
`second conformal silicon nitride layer;
`etching anisotropically said second silicon nitride to form
`second sideWall spacers on said logic devices;
`removing said salicide blockout mask;
`applying a salicide process of metal deposition and form
`ing self-aligned silicide structures on exposed said
`logic FET devices, Whereby there is formed loW resis
`tance lines and contacts on polysilicon gates and
`source/drain regions, While silicide formation is
`blocked on memory FET devices, by said second
`silicon nitride layer.
`6. The method of claim 5, Wherein said second silicon
`nitride layer ranges in thickness betWeen approximately 500
`Angstroms and 1500 Angstroms.
`7. The method of claim 5, Wherein said salicide process
`can be comprised of titanium or other suitable metals
`selected from the group consisting of Ta, Mo, W, Co, Ni, Pd
`and Pt.
`8. The method of claim 5, Wherein said second silicon
`nitride layer can be anisotropically reactive ion etched to
`form sideWall spacers on the memory devices.
`
`*
`
`*
`
`*
`
`*
`
`*
`
`IPR2004-00108
`Exhibit MX027-1004, p. 8
`
`