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`Office européen des brevets
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`EP 0 532 509 B1
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`EUROPEAN PATENT SPECIFICATION
`
`(45) Date of publication and mention
`of the grant of the patent:
`07.01.1999 Bulletin 1999/01
`
`(51) Int 01.6: G06F 13/00, GOGF 13/38,
`GOGF 3/06, GOGF 13/40
`
`'919072967
`b
`t'
`21 A |'
`)
`pp'ca'on “um er:
`'
`
`(
`
`(86) International application number:
`PCT/US91/01716
`
`(22) Date Of filing: 14'03'1991
`
`(87) International publication number:
`WO 91/14228 (19.09.1991 Gazette 1991/22)
`
`(54) BUFFERING SYSTEM FOR DYNAMICALLY PROVIDING DATA TO MULTIPLE STORAGE
`ELEMENTS
`
`PUFFERSYSTEM, UM DATEN DYNAMISCH AN MEHRERE SPEICHERELEMENTE
`WEITERZULEITEN
`
`SYSTEME DE TAMPONNAGE POUR UN TRANSFERT DE DONNEES DYNAMIQUE A DES
`ELEMENTS DE STOCKAGE MULTIPLES
`
`(84) Designated Contracting States:
`DE FR GB IT
`
`0 GAJJAR, Kumar
`San Jose, CA 95131 (US)
`
`(30) Priority: 14.03.1990 US 494039
`
`(43) Date of publication of application:
`24.03.1993 Bulletin 1993/12
`
`(73) Proprietor: EMC CORPORATION
`Hopkinton, MA 01748-9103 (US)
`
`(72) Inventors:
`0 Nguyen, Anh
`San Jose, CA 95136 (US)
`
`(74) Representative: Griinecker, Kinkeldey,
`Stockmair & Schwanhéusser Anwaltssozietét
`Maximilianstrasse 58
`
`80538 Mfinchen (DE)
`
`(56) References cited:
`DE-A- 3 801 547
`US-A— 4 607 348
`
`US-A— 4 672 613
`US-A- 4 860 244
`
`US-A- 4 371 928
`US-A- 4 644 463
`
`US-A- 4 843 544
`
`
`
`Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give
`notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in
`a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art.
`99(1) European Patent Convention).
`
`Printed by Jouve, 75001 PARIS (FR)
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`Description
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates generally to a method
`and system for reading and writing data to an array of
`memory storage devices.
`In a data processing system the performance of the
`central processing units (CPUs) is often limited by their
`data-storage subsystems. In particular, secondary stor-
`age devices used in such subsystems often are incapa-
`ble of transferring data at a rate that matches the speed
`with which the CPUs and the system buses are capable
`of handling the data. To improve the data transfer rate
`of the data-storage subsystems, and to enhance the
`overall data throughput of data processing systems, a
`storage subsystem architecture can be used in which
`the data is stored in an array of multiple storage devices.
`Such a storage array architecture can be imple-
`mented by coupling a high-speed data path (e.g., an in-
`put/output bus of a CPU) to an array of slower storage
`devices (e.g., tape or disk drives) via a corresponding
`array of high-speed memory elements. To write data to
`the storage devices, the provided data segments are
`transferred at high speed one after another overthe data
`path to different ones of the memory elements of the
`memory element array, which in turn hold the data seg-
`ments until the corresponding storage devices are ready
`to receive the data. The segments of data can then be
`transferred in parallel to the storage devices, such that
`the entire data may be stored in the storage device array
`in a shortertime, and with less sacrifice of CPU and sys-
`tem bus cycles, than would be required by a single stor-
`age device. The throughput of the high-speed data path
`is thus enhanced. The stored data can likewise be read
`
`from the storage devices at a high speed by transferring
`segments of data to corresponding memory elements,
`which in turn transfer one segment after another over
`the high-speed data path at a rapid rate.
`US-A-4,672,613 proposes a system for transferring
`data between a host device and a target recording me-
`dium, a buffer interface control unit includes a host direct
`memory access (DMA) unit for transferring data from the
`host unit to a buffer memory. The host DMA unit access-
`es a first set of prescribed noncontinuous buffer memory
`storage locations to store the data transferred from the
`host unit in a predetermined buffer format that includes
`additional sets of prescribed storage locations inter-
`spersed with the first set of data storage locations for
`the storage of error code characters pertaining to the
`data. The host DMA unit also transfers error correction
`
`code characters pertaining to the data to one of the ad-
`ditional sets of prescribed storage locations. The buffer
`interface control unit further includes a target DMA unit
`for transferring data from the buffer memory to a write
`interface unit. The target DMA unit accesses the buffer
`memory storage locations in a predetermined noncon-
`tinuous sequence in order to retrieve the data from the
`
`buffer memory in a format that includes open time slots
`interspersed with time slots occupied by the retrieved
`data for the insertion of error detection code characters
`
`pertaining to the data retrieved from the buffer memory.
`Generally, the known method for directing data into
`and out of a series of memory elements is to use a state
`machine sequencer implemented in hardware logic to
`control a memory element access sequence. This meth-
`od has several drawbacks. For example, the configura-
`tion in which data segments are stored in an array may
`vary from data transfer to data transfer, thus making it
`necessary that the sequence in which the data seg-
`ments are transferred between the data path interface
`and the storage device array be variable. A state ma-
`chine sequencer typically lacks sufficient flexibility to ac-
`commodate many different data storage configurations,
`and may require expensive modification to accommo-
`date even a slight change in configuration. This may limit
`the usefulness of the entire secondary storage subsys-
`tem. Known state machine sequencers also are typically
`complex and expensive.
`It is the object of the present invention to propose
`a data storage system and a respective method by
`which the selecting of memory elements can be varied
`to accommodate a wide variety of data storage config-
`urations and that can be implemented in a simple and
`inexpensive manner.
`This object is solved by the subject matter of claims
`1 and 10.
`
`Preferred embodiments of the present invention are
`the subject matter of the dependent claims.
`Preferably, each memory buffer has a temporary
`memory (typically, a static ram) for temporarily storing
`data transferred to or from the memory storage element
`(typically, a disk drive). Data paths couple the data l/O
`of the static RAM (SRAM) to the first and second inter-
`face circuits and to the disk drive through a word assem-
`bler. The word assembler converts between the 36-bit
`
`SRAM l/O path and the 9-bit disk drive l/O path. The
`particular data path to be used is controlled by trans-
`ceivers which are enabled by read/write and l/O circuitry
`under control of the local processor. Two separate
`counters are used to sequence through the addresses
`provided to the SRAM to transfer data between (1) the
`SRAM and the interface circuits, and (2) the SRAM and
`the disk drive interface, respectively. These counters
`can be preprogrammed by the local processor, which
`then selects the appropriate one to sequence through
`addresses, depending on the type of data transfer.
`A multi-function capability of each memory buffer
`allows it to transfer the same data to different memory
`buffers. This means the data can be duplicated in mul-
`tiple copies that can later be sent to different destina-
`tions.
`
`The invention will be better understood by reference
`to the following detailed description in connection with
`the accompanying drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`is a an overall block diagram of the data stor-
`1
`Fig.
`age system of the present invention;
`Fig. 2 is a block diagram of the interface circuits of
`Fig. 1;
`Fig. 3 is a block diagram of one embodiment of the
`control logic of Fig. 1;
`Fig. 4 is a block diagram of one implementation of
`the memory buffer selection FIFO circuitry of Fig. 3;
`Figs. 5(a)-5(f) illustrate the memory buffer selection
`process of the present invention using a 4-bit wide,
`16-element FIFO storage circuit having decoded
`outputs for serially sequencing 5 of 16 elements;
`Fig. 6 is a block diagram of a second embodiment
`of the data path control logic according to Fig. 1 us-
`ing two FIFO circuits; and
`Fig. 7 is a block diagram of the memory buffer of
`Fig. 1.
`
`DETAILED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS OF THE INVENTION
`
`Fig. 1 shows an overall block diagram of a data stor-
`age system 10. System 10 includes high-speed SCSI-
`2 buses 12 and 14 which are connected to an external
`
`computer system (not shown). SCSI-2 buses 12 and 14
`provide data to first and second interface circuits 16 and
`18, respectively. Interface circuit 16 provides data to a
`plurality of memory buffers 24 across a data bus 20.
`Likewise, interface circuit 18 provides data to memory
`buffers 24 across a data bus 22. Each memory buffer
`24 further provides data to a separate memory storage
`unit 26 across a 9-bit data bus 25. A local processor 28
`coupled to interface circuits 16 and 18 through a local
`bus extension 32 provides address and control signals
`to memory buffers 24 and a control logic circuit 30. Con-
`trol logic 30 is connected to each memory buffer 24 by
`a plurality of select lines 34A and 34B. Preferably, each
`SCSI-2 bus 12 and 14, data bus 20 and 22 and local
`bus extension 32 are 36 bits wide.
`
`In an overview, data can be written into and read
`from storage elements 26 by the external computer sys-
`tem. For writing operations, data enters on SCSI-2 bus
`12 (or 14) from the external computer system and is for-
`warded by interface circuit 16 (or 18) along data bus 20
`(or 22) to a selected memory buffer 24. From the select-
`ed memory buffer 24, the data is written into storage unit
`26 through data bus 25. For reading operations, data is
`retrieved from storage unit 26 through memory buffer 24
`along data bus 20 (or 22) to the appropriate interface
`circuit 16 or 18.
`
`Interface circuits 16 and 18 can operate simultane-
`ously; or, one could operate while the other is inactive.
`Data can be written into selected storage elements 26
`on data bus 20 while data is read from other selected
`
`ously, or read simultaneously, to greatly increase the da-
`ta transfer rate. Control logic 30 selects one or more of
`memory buffers 24 and enables their I/O to one of data
`buses 20 and 22 through two select lines 34A and 34B.
`Select line 34A corresponds to data bus 20 and select
`line 34B corresponds to data bus 22.
`When data is written into a memory buffer 24 for
`later transfer to a storage unit 26, an address for the
`memory buffer is provided from local processor 28. Con-
`trol logic 30 is programmed by processor 28 to select a
`particular select line 34A (or 34B) to address a desired
`memory buffer 24 for storing the data. The data is sub-
`sequently transferred to a storage unit 26.
`A read operation is similar to a write operation. An
`address is provided from local processor 28 along bus
`extension 32 to a selected memory buffer 24, for ac-
`cessing the memory in the selected memory buffer. The
`data will have previously been transferred from storage
`unit 26 to memory buffer 24. Once the desired address
`location is selected, the data is retrieved along data bus
`line 20 or 22, through the respective initiator interface
`circuit 16 or 18, then continuing along SCSI-2 bus 12 or
`14 to the external computer system. Local processor 28
`selects which interface circuit 16 or 18 (or both) is to be
`used for data transfer to a memory buffer.
`Fig. 2 shows in block diagram form interface circuits
`17 and 19 as connected to computer interface SCSI-2
`buses 12 and 14. Preferably, interface ports 12 and 14
`are small computer system interfaces (SCSI). As shown
`and described earlier, SCSI-2 buses 12 and 14 are
`36-bit data buses. Data to be stored in storage units 26
`is provided along SCSI-2 bus 12 and stored in a data-
`in register 36. A driver 38 is connected between the out-
`put of data-in register 36 and data bus 20. Data-out reg-
`ister 40 receives data retrieved from storage units 26
`along data bus 20 and is coupled to SCSI-2 bus 12
`through driver 42. The parity of each data word is
`checked by parity circuit 44, which is coupled to SCSI-
`2 bus 12. Both driver 38 and driver 42 are connected to
`
`control lines 48 and 46, respectively.
`In a write operation, driver 38 is enabled by a signal
`on control line 48 while driver 42 is disabled by a signal
`on control line 46 when data is being written into any of
`the storage units 26. Driver 42 is disabled to block any
`data coming from data-out register 40 so the data does
`not interfere with the data coming in on data bus 12
`through data-in register 36. In a read operation, the op-
`posite operation occurs. Driver 42 is enabled by a signal
`on control line 46 while driver 38 is disabled by a signal
`on line 48 when data is being read from any of storage
`units 26. Driver 38 is disabled to allow data in data-out
`
`registers 40 received from bus 20 to be outputted to SC-
`Sl-2 bus 12. This disablement of driver 38 blocks data-
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`in register 36 so that it does not interfere with the data-
`out operation of data-out register 40. Local processor
`28 selects one of driver 42 and driver 38 with control
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`storage units 26 along data bus 22 and vice versa. Also,
`interface circuits 16 and 18 can both write simultane-
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`signals on lines 46 and 48. The control signals are pro-
`vided to interface circuit 17 from local processor 28
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`along bus extension 32.
`Interface circuit 19 is identical to circuit 16 in structure
`
`and performs the same function and operation for SCSI-
`2 bus 14 and data bus 22.
`
`Fig. 3 shows one implementation of the control logic
`30 of Fig.
`1 with only data bus 20. The portion of the
`data storage system shown in Fig. 3 illustrates various
`paths along which data can be transferred in the storage
`subsystem to and from a plurality of disk drive devices
`(O-N). Data is transferred between interface circuit 16
`and memory buffers 24 over data bus 20, although data
`can also be transferred between local processor 28 and
`memory buffer 24 over bus extension 32, or from one
`memory buffer 24 to another over bus 20 or bus exten-
`sion 32 or another bus not shown.
`
`Interface circuit 16 is coupled to SCSI-2 bus 12 by
`which data is transferred between interface circuit 16
`
`and other modules of the data storage system or the
`external CPU or other components of the data process-
`ing system. SCSI-2 bus 12 may, for example, couple in-
`terface circuit 16 to a front-end interface module of the
`
`data storage system. Interface circuit 16 controls the
`flow of data on data bus 20 which couples interface cir-
`cuit 16 to a data port of each of memory buffers 24. Each
`memory buffer 24 in turn is coupled to a corresponding
`memory storage unit 26, such as a disk drive, via a data
`bus 25. The transfer of data between the memory buff-
`ers and the storage circuits over data buses 25 is con-
`trolled by local processor 28 and other control circuitry
`not forming a part of control logic 30 of the present in-
`vention.
`
`Local processor 28 also controls the overall process
`by which data is transferred between interface circuit 16
`and memory buffers O-N. The data is transferred as a
`series of data segments, typically of equal length. The
`size of the segments is defined by local processor 28
`and may, for example, equal the size of a sector on each
`of the memory storage units O-N. Each segment is trans-
`ferred between interface circuit 16 and a memory buffer
`24 as a unit.
`
`Bus extension 32 couples local processor 28 to con-
`trol registers in memory buffer 24, including a read/write
`register. Bus extension 32 also couples the local proc-
`essor to address registers in memory buffers ON and a
`holding register circuit 63 in control logic 30. Holding
`register circuit 63 is used to store a value equal to the
`number of data words or bytes in each segment of data
`to be transferred between interface circuit 16 and a
`
`memory buffer.
`A transfer (or word) counter circuit 65 is coupled to
`the output of holding register circuit 63. Transfer counter
`65 is a down counter and is loaded with the word count
`
`stored in holding register circuit 63 each time a new data
`segment is to be transferred to orfrom a memory buffer.
`Transfer counter 65 is decremented once for each data
`
`word or byte transferred. When transfer counter 65
`reaches 0, a signal is sent to zero detector circuit 68
`indicating completion of a segment transfer, and transfer
`
`counter 65 is reloaded by holding register 63 in re-
`sponse to a signal from zero detector circuit 68 on line
`69. The segment transfer completion signal also causes
`zero detector circuit 68 to provide read and load signals
`on lines 71 and 73, respectively, to sequence storage
`circuit 56.
`
`Sequence storage circuit 56 is a programmable cir-
`cuit for storing a sequence of memory buffer identifiers
`used to select the memory buffers to or from which data
`is to be transferred. The output of sequence storage cir-
`cuit 56 is coupled to selection bus 33, lines of which are
`coupled individually to select lines 34A of memory buff-
`ers O-N. Preferably, sequence storage circuit 56 is im-
`plemented using conventional first-in/first-out
`(FIFO)
`circuits to form a storage matrix in which memory buffer
`identifiers stored in the circuit are accessed in the same
`
`sequence that they are loaded, although the access se-
`quence may also be in any other repetitive order de-
`pending on the implementation and the application (e.
`g., the identifiers can be accessed in a reverse order).
`Sequence storage circuit 56 can also be implemented
`using RAM or register arrays, or a microprocessor, but
`a FIFO implementation requires the least amount of
`hardware.
`The exact manner in which identifiers are accessed
`
`from sequence storage circuit 56 depends on the par-
`ticular implementation of the circuit. Accessing an iden-
`tifier from sequence storage circuit 56 can be accom-
`plished in numerous ways. For example, it may be the
`case that a FIFO circuit is used that automatically trans-
`fers the first identifier with which it is loaded to its output
`and latches the output, such that the first identifier is im-
`mediately available on selection bus 33, and subse-
`quently loaded identifiers are accessed by providing a
`read signal to the FIFO circuit. This implementation is
`exemplified in Fig. 3. The FIFO circuit may also require
`an additional output enable signal, as shown in Fig. 4.
`"Accessing" sequence storage circuit implementations
`other than FIFO circuitry may include operations such
`as "fetch", "unload" and "nondestructive read".
`The output of sequence storage circuit 56 is also
`coupled by bus 33 to one input of a 2:1 multiplexercircuit
`52, the other input of which is coupled to bus extension
`32. At the beginning of a data transfer, local processor
`28 provides a signal on load data line 75 which causes
`multiplexer circuit 52 to couple bus extension 32 to the
`data input of sequence storage circuit 56 in order to load
`memory buffer identifiers into sequence storage circuit
`56. After the identifiers are loaded local processor 28
`releases control of multiplexer 52, and multiplexer 52
`couples the output of sequence storage circuit 56 to its
`input. Multiplexer 52 allows the output of sequence stor-
`age circuit 56 to be written back to its input each time
`an identifier stored in sequence storage circuit 56 is ac-
`cessed.
`In this manner the sequence of
`identifiers
`stored in sequence storage circuit 56 can be repeated
`as necessary to complete the transfer of data. When the
`transfer is completed, or at the initiation of a subsequent
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`transfer, the local processor 28 causes a reset control
`logic circuit 77 to clear sequence storage circuit 56.
`A parity circuit (or other validation circuitry) 79 cou-
`pled to bus 33 validates the identifiers written back into
`sequence storage circuit 56. Each identifier stored by
`local processor 28 in sequence storage circuit 56 in-
`cludes one or more parity bits. When an identifier is ac-
`cessed from sequence storage circuit 56, parity circuit
`79 generates a corresponding parity value and com-
`pares it to the parity bit or bits appended to the identifier.
`Parity circuit 79 generates an error signal if the com-
`pared parity data do not match.
`In addition, bus 33 is
`coupled between the output of sequence storage circuit
`56 and bus extension 32 to allow local processor 28 to
`read back identifiers stored in sequence storage circuit
`56 for validation and diagnostic purposes. Bus 35 cou-
`ples the output of holding register circuit 63 to bus ex-
`tension 32 to allow local processor 28 to read the con-
`tents of holding register circuit 63 for similar purposes.
`An exemplary implementation of sequence storage
`circuit 56 using an n x m FIFO circuit 300 is shown in
`Fig. 4, where n represents the bit length of the storage
`matrix (i.e., the number of bits in each memory buffer
`identifier storage location), and m represents the depth
`of the storage matrix (i.e., the number of identifier stor-
`age locations). FIFO circuit 300 can be constructed from
`any number of conventional FIFO circuit chips to create
`a matrix of the desired size. If
`it is desired that a group
`of memory buffers from an array of memory buffers be
`selectable at one time during a sequenced data transfer,
`the FIFO circuit can be implemented in a bit-significant
`format where each bit of an identifier storage location in
`the FIFO circuit corresponds to a different memory buff-
`er. In this format the identifiers stored in the FIFO circuit
`
`directly represent, as a pattern of ones and zeros, the
`selecting signals for each memory buffer of the array,
`and the bit-length of the FIFO circuit at least equals the
`number of memory buffers in the memory buffer array.
`The bit-length may be greater than the array size if parity
`bits are appended to the stored identifiers.
`If on the other hand only a single memory buffer is
`to be selected during each step of the sequenced data
`transfer, the bit-length of the FIFO circuit can be made
`less than the size of the memory buffer array by encod-
`ing the memory buffer identifiers stored in the FIFO, and
`decoding the identifiers into bit-significant patterns as
`the identifiers are read from the FIFO circuit. This stor-
`
`age format is shown in Fig. 5.
`Returning to Fig. 4, FIFO circuit 300 receives a se-
`quence of memory buffer identifiers from bus extension
`32 through multiplexer 52. The output of FIFO circuit 300
`is coupled through an enabled output circuit 302 to se-
`lection bus 33 and is written back to the input 304 of
`FIFO circuit 300 by bus 306 to permit the accessed iden-
`tifier of the sequence to be repeated. Parity checker cir-
`cuit 79 generates a parity error signal if the parity does
`not match the parity of the stored identifier.
`Data transfers over data bus 20 between interface
`
`circuit 16 and memory buffers 0-N generally take place
`as follows. Data is transferred over data bus 20 one
`
`word at a time. To write data to a selected memory buff-
`er, an external CPU or other source places a data word
`on data bus 20 and asserts a data request signal on data
`request line 41, which provides the data request signal
`to direct memory access (DMA) control circuit 61. DMA
`control circuit 61 generates a write pulse on line 39,
`which in combination with the memory buffer select sig-
`nal allows a data word to be written to the memory buffer
`or buffers selected by control logic 30. DMA control cir-
`cuit 61 asserts a data acknowledge signal on line 49.
`This data acknowledge signal informs the external CPU
`to assert another data request signal for the next word
`to be transferred. The data acknowledge signal also is
`coupled to word counter circuit 65, which decrements
`its value once for every data acknowledge signal it re-
`ceives.
`
`To conduct a data read (Le, a transfer of data from
`memory buffers 0-N to interface adaptor 16), the exter-
`nal CPU again asserts a data request signal on line 41.
`In response to the data request signal DMA control cir-
`cuit 61 generates a read pulse on line 39.
`In response
`to the read pulse a selected memory buffer places a data
`word on data bus 20. DMA control circuit 61 sends a
`
`data acknowledge signal on line 49. Word counter 65 is
`decremented once for each asserted data acknowledge
`signal. These write and read operations are repeated as
`often as necessary to complete the data transfer.
`Memory buffers are selected by sequence control
`logic 30 as follows. For purposes of illustration, it is as-
`sumed that the following memory buffer sequence is
`loaded in first in, first out order in sequence storage cir-
`cuit 56: memory buffer 0, memory buffer 5, memory buff-
`er 10 and memory buffer 12. The first identifier in se-
`quence storage circuit 56, when accessed, causes
`memory buffer 0 to be selected. The first identifier is also
`written back to the input of sequence storage circuit 56
`before a second identifier is accessed. When interface
`
`circuit 16 asserts a data request on line 41 to transfer a
`data word to memory buffer 0, the first data word placed
`on data bus 20 is read by memory buffer 0, and word
`counter 65 is decremented by 1. In response to a second
`data request signal, a second data word is read by mem-
`ory buffer 0, and word counter 65 is again decremented
`by 1. This continues until word counter 65 reaches 0.
`When word counter 65 reaches 0, zero detector cir-
`cuit 68 is activated to provide various control signals as
`follows: control signals are provided on lines 71 and 73
`to sequence storage circuit 56 to cause the second iden-
`tifier to be accessed for selecting memory buffer 5, and
`to cause the second identifier to be written back to the
`
`input of sequence storage circuit 56; and a control signal
`is provided to load word counter circuit 65 from holding
`register circuit 63.
`After the data segment is transferred to memory
`buffer 5, the process is repeated to transfer data to
`memory buffers 10 and 12. When the transferto memory
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`buffer 12 is complete, memory buffer 0 will again be se-
`lected and the sequence repeated to transfer additional
`data to each of the selected memory buffers. This proc-
`ess will continue until the data transfer from the interface
`
`circuit 16 is completed. After a desired amount of data
`has been transferred to memory buffers 0,5, 10 and 12,
`a data transfer will begin from memory buffers O, 5, 10
`and 12 to their corresponding data bus 25 to complete
`the data transfer to storage units 26.
`Figs. 5(a)-(f) show an example of the steps by which
`a typical FIFO circuit 400 selects a repeating sequence
`of memory buffers. The FIFO is configured to select a
`sequence of 5 memory buffers in single order from an
`array of 16 buffers. The sequence in the order is 0,5, 8,
`14 and 2. The FIFO is implemented as 16 addresses
`deep (although only 5 are necessary for this example)
`by 4 bits wide. The addresses are encoded and a 4-to-
`16 decoder circuit 402 is used to select one buffer at a
`
`In Figs. 5(a)-(f) a solid line signal path indicates
`time.
`that the signal path is active; a dotted line signal path
`indicates that the path is inactive.
`In Fig. 5(a), bus extension 32 is shown activated
`(solid line) to load FIFO circuit 400 with addresses of the
`selected buffers in sequence. In this figure buffers O, 5,
`8, 14 and 2 are loaded in first-in/first-out order. Buffer O
`is loaded first. The decoder 402 output is either not en-
`abled or is ignored at this time.
`Fig. 5(b) shows the FIFO circuit 400 during data
`transfer with buffer 0 selected. Bus extension 32 is in-
`
`active (dotted line) during this time, as is feedback 404.
`Fig. 5(c) shows the end of data transfer to buffer 0.
`The address of buffer 0 is written back into the FIFO
`circuit 400 after the FIFO circuit is accessed via write-
`
`back path 404, and there is a shift of the FIFO contents
`to put 5 at the output.
`Fig. 5(d) shows FIFO circuit 400 during data trans-
`fer with buffer 5 selected. The write-back path 404 is
`inactive.
`
`Fig. 5(e) shows the end of data transfer to buffer 5.
`The address of buffer 5 is written back into FIFO circuit
`400 after the FIFO circuit is accessed via write-back
`
`path 404, and another FIFO shift is done.
`Fig. 5(f) shows FIFO circuit 400 during data transfer
`with buffer 8 selected. Write-back 404 is again inactive.
`Buffers 14 and 2 are accessed in the same way as
`the previous buffers. These accesses are not shown in
`Fig. 5. This sequence will be repeated until the data
`transfer for all buffers is completed as discussed previ-
`ously.
`Fig. 6 shows in block diagram a further implemen-
`tation of the control logic 30 found in Fig.
`1 and Fig. 3.
`This implementation includes a second set of sequence
`storage circuits, holding register circuits, and transfer
`counters and controls, as well as a buffer compare logic
`60, whose function is described below. Addresses are
`provided to control logic 30 through bus extension 32.
`A receiver 50 is connected to bus extension 32. Receiv-
`
`er 50 has its output coupled to a first 2:1 multiplexer 52
`
`and a second 2:1 multiplexer 54. Each multiplexer 52
`and 54 is further coupled to a sequence storage circuit
`56 and 58, respectively. Preferably, each sequence stor-
`age circuit is a first-in/first-out (FIFO) device that pro-
`vides a 64x15-bit word array. Thirteen bits of each word
`are used for selecting one or more of select lines BLO -
`BL12, with the remaining two bits being parity bits. The
`output of sequence storage circuit 56 corresponds to se-
`lect lines 34A for selecting any one of memory buffers
`24 while data is provided on data bus 20. Similarly, the
`output of sequence storage circuit 58 corresponds to se-
`lect lines 34B for selecting any one of memory buffers
`24 while data is provided on data bus 22. Buffer com-
`pare logic 60 has inputs connected one each to select
`lines 34A and 34B and an output coupled to local proc-
`essor 28 by output line 62. When buffer compare logic
`60 receives signals from both select lines 34A and 34B
`for the same buffer 24, this indicates that both data bus-
`es 20 and 22 are trying to access the same memory buff-
`er 24 simultaneously. When such occurs, buffer com-
`pare logic 60 generates an error signal to local proces-
`sor 28 on output line 62.
`In a general overview of operation, an address pat-
`tern is Ioaded into the 64x15-bit word array of FIFO 56
`from bus extension 32. Each word in the address pattern
`has one or more active bits that, when selected, enables
`a particular select line 34A coupled to a specific memory
`buffer 24. The word output from FIFO 56 selects a spe-
`cific line 34A to access a specific memory buffer 24 with
`data either written to or read from that memory buffer 24
`along data bus 20. In addition, a word output from FIFO
`58 selects a specific select line 34B to access a specific
`memory buffer 24 to read or write data along data bus
`line 22. The outputs of FIFOs 56 and 58 are coupled
`back to their inputs through multiplexers 52 and 54, re-
`spectively.
`Status register 70 is used to provide the local proc-
`essor with the status of the memory buffer (i.e., interrupt
`status, mask status and other status, such as FIFO full,
`etc.). Interrupt mask register 83 is used to mask an in-
`terrupt from one or more of the memory buffers. An in-
`terrupt is generated upon the completion of a datatrans-
`fer. The control Iogic 30 in Fig. 6 is essentially identical
`in operation to that found in Fig. 3 and includes the sec-
`ond sequence storage circuit with accompanying regis-
`ter, counters and controls.
`Register 49 and counter and control circuit 53 corre-
`spond to the holding register and counter and control
`circuitry of Fig. 3 for FIFO 56. Register 51 and counter
`and control circuitry 55 perform the same function for
`FIFO 58. The buffer compare logic is added to this em-
`bodiment in order to detect an error of selecting the
`same memory buffer for the simultaneous write and
`read operations as described earlier.
`Fig. 7 is a block diagram showing one of the mem-
`ory buffers 24 shown in Fig. 1. Data transferred on 32-bit
`data bus 20 comes into memory buffer 24 much faster
`than the data transferred can be provided to storage el-
`
`10
`
`15
`
`20
`
`25
`
`3