United States Patent
`Caiati et al.
`
`[191
`
`[54] SOLID STATE CRASH RECORDER
`[75] Inventors: Frank P. Caiati, Bloom?eld Hills;
`David C. Wight, Romeo, both of
`Mich.
`[73] Assignee: General Motors Corporation,
`Detroit, Mich.
`Nov. 20, 1972
`[22] Filed:
`[2l] Appl. No.: 308,005
`Related US. Application Data
`(63] Continuation-impart of Ser. No. 249,918, May 3,
`i972.
`
`{52] US. Cl ............. .. 340/1715, 340/22, 346/33 R,
`307/22] R
`[51] Int. Cl. .......................................... .. Gllc 19/00
`[58] Field of Search ................... .. 340/l72.5, 173 R,
`340/22; 307/9, 10, 221 R; 346/33 EC, 44;
`235/92 SH
`
`[56}
`
`References Cited
`UNITED STATES PATENTS
`3,683,403
`8/1972 Okino ........................... .. 346/33 EC
`3,710,081
`l/l973
`Apitz ....................... .7 235/l50.24 X
`Primary Examiner-Paul J. Henonon
`Assistant Examiner--Mark Edward Nusbaum
`Attorney-C. R. Meland et al.
`
`3,781,824
`[11}
`[451 Dec.25, 1973
`
`ABSTRACT
`[57]
`A solid state crash recorder in which various vehicle
`conditions such as acceleration and speed are continu
`ally monitored and converted into digital form with
`the magnitude of the conditions monitored being cy
`clically stored in a plurality of registers. Upon the
`sensing of a crash, the contents of a portion of the reg
`isters corresponding to certain vehicle conditions,
`such as speed and low level acceleration, are main
`tained so as to provide information relating to pre
`crash conditions while information relating to other
`conditions, such as high acceleration, are continually
`fed to the remaining registers with the output thereof
`being routed, when a crash is sensed, to a memory cir
`cuit. [n this manner, pre and post crash information
`relating to those conditions are memorized. Subse
`quently, the contents of the registers containing only
`. precrash information are routed to the memory circuit
`which memorizes the precrash conditions represented
`thereby. When the contents of all the registers have
`been memorized in the memory circuit, the power
`supplied to the system is disabled so as to prevent fur
`ther inputs to the crash recorder.
`
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`

`1
`SOLID STATE CRASH RECORDER
`
`3,781,824
`
`2
`the input ofa high gain ampli?er 18. The output of the
`accelerometer 12, which also is analog in nature, is am
`pli?ed by an ampli?er 20 whose output is coupled to
`the input of a low gain ampli?er 22 and to the input of
`a high gain ampli?er 24.
`The outputs of the low gain ampli?ers 16 and 22 pro
`vide useful information relating to high G forces as
`sensed by the accelerometers l0 and 12, respectively,
`and the high gain ampli?ers l8 and 24 provide informa
`tion useful with respect to low G forces as sensed by the
`accelerometers l0 and 12, respectively. The outputs of
`the ampli?ers l6, 18, 22 and 24 are supplied to an ana
`log multiplexer 30 which can be comprised of either
`solid state or electromechanical switches.
`Vehicle velocity information is obtained through a
`vehicle wheel speed pickup coil 26 which is a portion
`of a conventional speed transducer whose output is an
`alternating signal having a frequency directly related to
`wheel speed and consequently vehicle speed. The out
`put of the pickup coil 26 is applied to the input of a
`square wave ampli?er 28 whose output is a square
`wave signal WSP having a frequency directly related to
`vehicle speed.
`A power supply 32 supplies power to all the remain
`ing portions of the crash recorder through power lines
`(not shown) and generates a power reset signal PRST
`which is supplied to a timing state generator 34 and a
`system decoder and control signal generator 36 to es
`tablish initial conditions therein each time the power
`supply 32 is energized.
`The timing state generator 34 generates and supplies
`to the system decoder and control signal generator 36
`a series of timing signals TSILEZ, T53, E4, T_S_S_, and
`TS6 and their inverse T87, T82, T53, T54, T55 and
`m. The timing state generator 34 also generates a
`timing signal TS7, a strobe signal WS and an oscillator
`signal OSC and supplies their inverse W, W—S and
`mm the system decoder and control signal genera
`tor 36 along with a clock signal CLK, its inverse ER,
`and a timing state carryout signal TSCO. In addition,
`the timing signal T53 is supplied to an analog-to-digital
`converter 40.
`The system decoder and control signal generator 36
`is responsive to the signals supplied thereto from the
`timing stage generator 34 to generate a plurality of
`channel select signals CS0, CS1, CS2 and CS3 which
`are sequentially supplied to the analog multiplexer 30
`which is sequenced thereby to sequentially couple the
`outputs of the ampli?ers 16, 18, 22 and 24, respec~
`tively, to a sample and hold circuit 41. The sample and
`hold circuit 41 is operative to hold the signal supplied
`thereto until the analog multiplexer 30 supplies another
`signal in response to one of the channel select signals
`CS0, CS1, CS2 or CS3, which signal is then held by the
`sample and hold circuit 41. The output of the sample
`and hold circuit 41 is supplied to the analog-to-digital
`converter 40 and consists of a sequence of signals rep
`resenting the outputs of the amplifiers l6, 18, 22 and
`24.
`The system decoder and control signal generator 36
`generates an analog-to-digital clock signal ADC com
`prised of a series of pulses which are supplied to the
`analog-to-digital converter 40 which is responsive
`thereto and to the timing signal T53 to convert the out
`put of the sample and hold circuit 41 to a digital indica
`tion of the magnitude thereof upon each occurrence of
`the timing signal TS3. This indication is a serial output
`
`20
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`35
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`40
`
`This is a continuation-in-part of application Ser. No.
`249,918, filed May 3, 1972, and assigned to the as
`signee of this invention.
`This invention relates to a solid state crash recorder
`for memorizing pre and post crash conditions of a vehi
`cle. Known crash recorders use systems whereby a re
`cording medium is moved upon which information is
`recorded. In this manner, information existing prior to
`and during a crash, for example, may be memorized for
`subsequent review. It is the general object of this inven
`tion to provide for a vehicle crash recorder which does
`not utilize any moving parts.
`It is another object of this invention to provide for an
`all solid state crash recorder for monitoring pre and
`post crash conditions of a vehicle.
`The invention may be best understood by reference
`to the following description of a preferred embodiment
`and the drawings in which:
`FIG. I is a block diagram of the preferred embodi
`ment of the invention;
`FIG. 2 is a schematic of the power supply of FIG. 1;
`FIG. 3 is a schematic of the timing state generator of
`25
`FIG. 1;
`FIG. 4 is a logic diagram for generating the channel
`select signals SCO, CS1, CS2 and CS4;
`FIR. 5 is a logic diagram for generating the analog-to
`digital clock pulses ADC;
`FIG. 6 is a logic diagram for generating the register
`clock pulses RC1;
`FIG. 7 is a logic diagram for generating the register
`clock pulses RC2;
`FIG. 8 is a schematic of the digital input-output cir
`cuit of FIG. 1;
`FIG. 9 is a logic diagram for generating the velocity
`time interval signal V'I‘l, data shift signal DS, velocity
`enable signal VE and the register clock pulses RC3;
`FIG. 10 is a logic diagram for generating the write en
`able signal WE;
`FIG. II is a logic diagram for generating the read en
`able signals REl, REZ and RE3;
`FIG. 12 is a logic diagram for generating the memory
`address clock pulses MAC;
`FIG. 13 is a schematic diagram of the memory ad
`dress counter and decoder of FIG. 1;
`FIG. 14 is a logic diagram for generating the data re
`cord complete signals DRCl and DRCZ; and
`FIG. 15 is a logic diagram for generating the system
`destruct signal SDE.
`Referring to FIG. 1, there is shown a solid state crash
`recorder for memorizing pre and post crash informa
`tion relating to acceleration rates of the vehicle and for
`memorizing precrash information relating to the veloc
`ity of the vehicle. It will be obvious to one skilled in the
`art that although the preferred embodiment refers to
`memorizing acceleration and velocity, other types of
`information may be recorded.
`Vehicle acceleration is monitored by an accelerom
`eter 10 which is positioned in the vehicle so as to moni
`tor acceleration along the longitudinal axis thereof and
`a similar accelerometer 12 which is positioned on the
`vehicle so as to monitor the acceleration thereof along
`its lateral axis. The output of the accelerometer 10,
`which is of the known variety whose output is analog
`in nature, is amplified by an amplifier 14 whose output
`is applied to the input ofa low gain ampli?er l6 and to
`
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`OWNER Ex. 2027, page 7
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`3
`comprised of a certain number of bits representing a
`digital word which in turn represents the magnitude of
`acceleration being sampled. The analog-to-digital con
`verter 40 for performing the aforementioned function
`is well known in the art and will not be described in
`greater detail.
`The output of the analog-to-digital converter 40 is
`coupled to a shift register 42 and a shift register 44.
`When clocking pulses are supplied to the shaft register
`42 or 44 in synchronism with the bits in the serial out
`put of the analog-to-digital converter 40, the bits are
`serially shifted into and through the respective register
`42 or 44 and are retained thereby until shifted out of
`the last stage therein.
`When the sample and hold circuit 41 has sampled the
`input thereto from the analog multiplexer 30 as deter
`mined by the system decoder and control signal genera
`tor 36. the system decoder and control signal generator
`36 supplies the analog-to-digital clock signal ADC to
`the analog-to-digital converter 40 during the timing sig
`nal T53. The analog-to-digital converter 40 is enabled
`thereby to supply the digital serial output representing
`the digital word corresponding to the magnitude of G
`level sampled by the sample and hold circuit 41 to the
`shift registers 42 and 44. Simultaneously therewith, the
`system decoder and control signal generator 36
`supplies synchronized clocking pulses to either the shift
`register 42 or the shift register 44 into which the bits
`are shifted representing the G level sampled. If the
`input to the sample and hold circuit 41 from the analog
`multiplexer 30 were from the ampli?er 16 or the ampli
`fier 22 whose outputs provide useful information relat
`ing to high G levels of acceleration. the system decoder
`and control signal generator 36 generates and supplies
`register clock pulses RCl in synchronism with the ana
`log-to-digital clock signal ADC to the shift register 42
`into which the serial output of the analog-to-digital
`converter 40 is shifted. Conversely, if the input to the
`sample and hold circuit 41 were from the amplifiers 18
`or 24 which provide useful information relating to low
`0 levels of acceleration, the system decoder and con
`trol signal generator 36 generates and supplies register
`clock pulses RC2 in synchronism with the analog-to
`digital clock signal ADC to the shift register 44 into
`which the serial output of the analog-to-digital con
`verter 40 is shifted. As it may not be desired to read the
`low G information into the register 44 as frequently as
`high 0 information is read into the shift register 42, the
`register clock pulses RC2 are not supplied to the shift
`register 44 each time the serial output of the analog-to
`digital converter 40 represents low G information.
`Consequently, the period between the sets of register
`clock pulses RC2 is greater than the period between
`the sets of register clock pulses RC1.
`As can be seen, as the system decoder and control
`signal generator 36 sequences the analog multiplexer
`30, information relating to acceleration is periodically
`supplied to the shift registers 42 and 44 which store the
`information supplied thereto for a time period repre
`senting the most recent history of acceleration. The
`number of stages in the shift registers 42 and 44 are
`such that a plurality of words are contained therein at
`any given instant corresponding to the length of time of
`desired recent history that precrash information relat
`ing to high G and low G information, respectively, is to
`be stored.
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`From the foregoing description, it can be seen that
`digital words derived from the outputs of the amplifiers
`l6 and 22 are alternately read into the shift register 42
`and that words derived from the outputs of the ampli?
`ers 18 and 24 are alternately read into the shift register
`44. Consequently, each of the shift registers 42 and 44
`contain acceleration data from both of the accelerom
`eters l0 and 12. it will be readily seen by one skilled in
`the art that a shift register could be provided for each
`of the ampli?ers l6, i8, 22 and 24.
`The output signal WSP of the square wave ampli?er
`28 is supplied to a digital input-output circuit 46 which
`also receives a velocity time interval signal VTl, a data
`shift signal DS, a velocity enable signal VB and register
`clock pulses RC3 which are generated by and supplied
`thereto from the system decoder and control signal
`generator 36. In response to the aforementioned sig
`nals, the digital input-output circuit 46 supplies a serial
`output comprised ofa certain number of bits represent
`ing a digital word which in turn represents vehicle
`speed to a shift register 48, which is similar to the shift
`registers 42 and 44. The bits in the serial train supplied
`to the shift register 48 occur simultaneously with each
`pulse of the register clock pulses RC3. The register
`clock pulses RC3 are simultaneously supplied to the
`shift register 48 into which the serial output from the
`digital input'output circuit 46 is shifted. The vehicle ve
`locity is periodically sampled in the foregoing manner.
`The shift register 48 contains a number of stages such
`that a number of words representing the desired length
`of time of most recent history of precrash information
`are contained therein.
`In the absence ofa vehicle crash, the aforementioned
`procedure is periodically repeated so that the contents
`of the shift registers 42, 44 and 48 are continually up
`dated so as to represent the most recent history of ac
`celeration and velocity.
`The outputs of the ampli?ers l6 and 22 are supplied
`to a G level detector 50. The G level detector 50 may
`take the form of any one of the well known threshold
`detectors which are responsive to an input signal of a
`predetermined magnitude or to an input signal of a cer
`tain magnitude for a specified period oftime for gener
`ating an output signal. In the event that the G level de
`tector 50 senses an output from either ofthe ampli?ers
`16 or 22 having a magnitude representing a vehicle
`crash, a G level enable signal GLE is generated thereby
`and supplied to the system decoder and control signal
`generator 36. Upon receipt of the G level enable signal
`GLE, the system decoder and control signal generator
`36 generates a write enable signal WE when the output
`of the amplifier 16 is ?rst sampled after the detection
`of a crash. The write enable signal WE is effective to
`prevent further inputs from being memorized by the
`shift registers 44 and 48 by inhibiting the generation of
`further register clock pulses RC2 and RC3 and which
`initiates the post-crash procedure. In this manner, the
`precrash information contained within the shift regis
`ters 44 and 48 is retained. The system decoder and con
`trol signal generator 36 continues to sequence the ana
`log multiplexer 30 in the manner previously described.
`When the write enable signal WE is generated, the sys
`tem decoder and control signal generator 36 and a
`memory address counter and decoder 51 cooperate to
`supply the information to a memory system 52.
`Upon the generation of the write enable signal WE,
`the system decoder and control signal generator 36
`
`OWNER Ex. 2027, page 8
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`

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`3,781,824
`
`25
`
`5
`generates a read enable signal RE! which is supplied to
`a switch 53 which is closed thereby to couple the out
`put of the last stage of the shift register 42 to the mem
`ory system 52. The contents of the shift register 42 are
`supplied in serial form to the memory system 52 as ad
`ditional information is read into said shift register 42
`from the analog-to-digital converter 40. Simulta
`neously with the serial input to the memory system 52,
`the system decoder and control signal generator 36
`supplies memory address clock pulses MAC to the
`memory address counter and decoder 51 synchronized
`with the serial input to the memory system 52. The
`memory address counter and recorder 51 is responsive
`to the memory address clock pulses MAC to select the
`address in the memory system 52 at which each bit
`input thereto is memorized The serial output first sup
`plied from the shift register 42 and which passes
`through the switch 53 represents the information
`stored within the shift register 42 at the time of the
`crash as detected by the 0 level detector 50 and come
`quently represents the precrash acceleration levels
`from the outputs of the ampli?ers l6 and 22. Informa
`tion is continually read into and out of the shift register
`42 until all of the precrash information contained
`therein is memorized in the memory system 52 and a
`predetermined period of post-crash information is read
`therefrom and memorized in the memory system 52.
`After the memory system 52 has stored the predeter
`mined number of bits from the output of the register
`42, as determined by a predetermined number of mem
`my address clock pulses MAC supplied to the memory
`address counter and decoder 51, the memory address
`counter and decoder 51 supplies a data record com
`plete signal DRCl to the system decoder and control
`signal generator 36 to effect the disabling of the switch
`53 to prevent additional information from being sup
`plied to the memory system 52 from the shift register
`42.
`The system decoder and control signal generator 36
`40
`is responsive to the data record complete signal DRCl
`for generating and supplying a read enable signal RE2
`to a switch 58 which couples the output of the last stage
`in the shift register 44 to the memory system 52. Also
`simultaneously therewith, the system decoder and con
`trol signal generator again supplies the register clock
`pulses RC2 to the shift register 44 at a frequency equal
`to the frequency of the clock signal CLK so as to read
`the contents therein into the memory system 52 in the
`same manner as the shift register 42. Again, the system
`decoder and control signal generator 36 supplies the
`memory address clock pulses MAC at the frequency of
`the clock signal CLK and synchronized with the regis
`ter clock pulses RC2 to the memory address counter
`and decoder 51 which addresses the memory system
`52.
`After the contents of the shift register 44 have been
`read into the memory system 52, as determined by a
`predetermined number of memory address clock pulses
`MAC supplied to the memory address counter and de
`coder circuit 51, the memory address counter and de
`coder circuit 51 supplies a data record complete signal
`DRC2 to the system decoder and control signal genera
`tor 36 which is responsive thereto to disable the switch
`58 and to generate a read enable signal RE3. The read
`enable signal RE3 is supplied to a switch 60 which is
`enabled thereby to couple the output of the last stage
`ofthe shift register 48 to the memory system 52. Simul
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`6
`taneously, the system decoder and control signal gener
`ator 36 supplies the register clock signal RC3 to the
`shift register 48 at the same frequency as the clock sig
`nal CLK and the memory address clock signal MAC at
`the same frequency to the memory address counter and
`the decoder 51 to read the contents of the shift register
`48 into the memory system 52 in the same manner as
`the shift registers 42 and 44. When the contents of the
`shift register 48 have been read into the memory sys
`tem 52, as determined by a predetermined number of
`memory address clock pulses MAC supplied to the
`memory address clock counter and decoder 51, the
`memory address counter and decoder 51 supplies a
`shutdown enable signal SDE to the power supply 32
`which is disabled thereby to prevent any further infor
`mation from being monitored by the solid state crash
`recorder.
`Referring to FIG. 2, the power supply 32 is com
`prised of a DC voltage source 54 which may be, for ex
`ample, the vehicle battery whose output is coupled to
`the remaining portions of the solid state crash recorder
`through a vehicle ignition switch 56, a fuse 58 and a
`conventional voltage regulator 59. The power supply
`32 generates the power reset signal PRST by means of
`a timing circuit including a resistor 60 series connected
`with a capacitor 62, the series circuit being coupled in
`parallel with the DC voltage source 54, the vehicle igni
`tion switch 56 and the fuse 58. The junction between
`the resistor 60 and the capacitor 62 is coupled to an in
`verter 64.
`Upon the energization of the power supply 32 by the
`closure of the vehicle ignition switch 56, the input to
`the inverter 64 is at ground potential. Consequently, its
`output is a positive voltage level. When the capacitor
`62 has charged to the switching level of the inverter 64,
`the output thereof switches to ground potential. This
`positive voltage pulse constitutes the power reset signal
`PRST which is coupled to the timing state generator 34
`and the system decoder and control signal generator 36
`to establish initial conditions therein each time the
`power supply 32 is energized by the closure of the vehi
`cle ignition switch 56.
`As previously indicated with reference to FIG. 1,
`after the detection of a vehicle crash and the memory
`system 52 has memorized the desired information relat
`ing to acceleration and vehicle velocity, the shutdown
`enable signal SDE is supplied by the memory address
`counter and decoder 51 to the power supply 32 which
`is disabled thereby‘ This is accomplished by means of
`an SCR 66 which is series coupled with a small resistor
`68 with the fuse 58, the vehicle ignition switch 56 and
`the DC voltage source 54. The shutdown enable signal
`SDE is coupled across a voltage divider comprised of
`a resistor 70 and a resistor 72, the output thereof being
`coupled to the control electrode of the SCR 66. When
`the shutdown enable signal SDE is generated, the SCR
`66 is gated on to short the battery to ground through
`the fuse 58. The current through the fuse 58 is suff
`cient to cause it to open the circuit from the DC voltage
`source 54. Consequently, the solid state crash recorder
`is thereafter disabled.
`Referring to H0. 3, the timing state generator 34 is
`comprised of an oscillator 74 which generates the oscil
`lator signal OSC which is coupled to the input of an in
`verter 76 and to the respective clock inputs of a pair of
`JK flip-flops 78 and 80. The output of the inverter 76
`is the inverse oscillator signal 63C which is supplied to
`
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`OWNER Ex. 2027, page 9
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`the system decoder and control signal generator 36.
`The 6 output of the flip-?op 78 is coupled to the K
`input of the ?ip-?op 8t) and its 0 output is coupled to
`the J input of the ?ip-?op 80. The O output of the ?ip
`flop 80 is coupled to the J input of the ?ip-?op 78 and
`the Q output thereof, which constitutes the strobe sig
`nal W5, is coupled to the input of an inverter 82. T_h§
`output of the inverter 82 is the inverse strobe signal W5
`which is supplied to the system decoder and control sig
`nal generator and is coupled to the clock input of a
`three-stage counter 84, the outputs of each stage of
`which are coupled to respective inputs ofa NAND gate
`86. The output of th_e_NAND gate 86 constitutes the in
`verse clock signal CLK which is coupled to the input of
`an inverter 88 and to the clock input of an eight-stage
`counter 90. The output of the inverter 88 constitutes
`the Lock signal CLK which, with the inverse clock sig
`nal CLK, is supplied to the system decoder and control
`signal generator 36.
`The output of the first stage of the eight-stage
`counter 90 constitutes a timing signal T50 and the out
`puts of the remaining stages of the eight-stage counter
`constitutes the timing signals T51 through TS7, respec
`tively. The timing signals TS! through T57 are coupled
`to respective inverters 92, 94, 96, 98, 100, 102 andlQj
`whose outputs constitute the inverse timing signals T51
`through T57. The timing signals T50 through T57 are
`coupled to respective inputs of a NAND gate 106. The
`output of the NAND gate 106 constitutes the timing
`stage carry-out signal TSCI] which occurs once for each
`cycle of the eight-stage counter 90. The timing state
`signals TSl thorugh T56 and their inverse along with
`the inverse of the timing signal T57 are supplied to the
`system decoder and control signal generator 36.
`The power reset signal PRST from the power supply
`32 is coupled to the reset inputs of the counter 84 and
`the counter 90, which are reset each time the ignition
`switch 56 in FIG. 2 is closed so as to establish initial
`conditions within the timing stage generator 34 each
`time the power supply 32 is energized.
`Referring to FIG. 4, the system decoder and control
`signal generator 36 generates the channel select signals
`CS0, CS1, CS2 and CS3 for sequencing the analog mul
`tiplexer 30 by means of respective NOR gates 110, 112,
`114 and 116. The NOR gate 110 receives at respective
`inputs the timing stage signals T53, T54, T55 and T56
`from the timing state generator 34 and supplies the
`channel select signal CSO at its output. The NOR gate
`112 receives at respective inputs the timing state sig
`nals T53, T55, T56 and the inverse timing signal T54
`and supplies at its output the channel select signal SC].
`The NOR gate 114 receives at respective inputs thereof
`the timing signals T53, T54, T56 and the inverse timing
`signal T55 and supplies at its output the channel select
`signal CS2. The NOR gate 116 receives at respective
`inputs the timing signals T53, T56, the inverse timing
`signals W and T5 and supplies at its output the chan
`nel select signal CS3. As indicated with reference to
`FIG. 1, the channel select signals CSO through CS3 are
`effective to sequentially couple the outputs of the re
`spective amplifiers 16, 18, 22 and 24 through the ana
`log multiplexer 30 to the input of the sample and hold
`circuit 41.
`Referring to FIG. 5, the system decoder and control
`signal generator 36 generates the analog-to-digital
`clock signal ADC by means of a NOR gate 118, a
`NAND gate 120 and an inverter 122. The NOR gate
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`118 recles at its respective inputs the inverse timing
`signal T53, the inverse clock signal CLK and the in
`verse strobe signal \TS and supplies its output to one
`input of the N_A_ND gate 120 which receives the inverse
`timing signal T56 at a second input thereof. The output
`of the NAND gate 120 is supplied to the inverter 122
`whose output constitutes the analog-to~digital clock
`signal ADC.
`As indicated with reference to FIG. 1, the analog-to
`digital clock signal ADC and the timing signal T53 are
`supplied to the analog~to~digital converter 40 which is
`responsive thereto to convert the output of the sample
`and hold circuit 41 to a digital indication in serial form
`of the magnitude thereof upon each occurrence of the
`timing signal T53. This signal is coupled to the input of
`the shift register 42 and the shift register 44.
`Referring to FIG. 6, the system decoder and control
`signal generator 36 generates the register clock pulses
`RC1 in synchronism with the analog-to-digital clock
`signal ADC so as to shift information into the shift reg
`ister 42 by means of a NOR gate 124, a NAND gate
`126, and a NOR gate 128. The NOR gate 124 receives
`at its respective inputs the inverse timing signals W
`and T'S—2 and supplies its output to an input of the NOR
`GATE 128. The NAND gate 126 receives at its respec
`tive inputs the timing signal T53 and the inverse timing
`signals T54 and T56 and supplies its output to another
`input of the NOR gate 128. The NOR gate 128 also re
`ceives at a third input, the inverse clock signal CLK.
`The output of the NOR gate 128 constitutes the regis
`ter clock pulses RC1 which are in synchronism with the
`analog-to-digital clock signal ADC when the output of
`the analogto-digital converter 40 represents informa
`tion supplied to the sample and hold circuit 41 by the
`ampli?ers 16 or 22. The register clock pulses RC1 are
`continually supplied to the shift register 42 of FIG. 1
`even in the event ofa crash so that post'crash informa
`tion relating to acceleration is continually shifted into
`the shift register 42 until the desired quantity of post
`crash information is memorized by the memory system
`52 as previously described with reference to FIG. 1.
`Referring to FIG. 7, the system decoder and control
`signal generator 36 generates the register clock pulses
`RC2 when the output of the analog-to-digital converter
`40 represents information supplied to the sample and
`hold circuit 41 from either the ampli?er 18 or the am
`pli?er 24 by means of a NAND gate 130, a NAND gate
`132, a NOR gate 134 and a NOR gate 136. The NOR
`gate 134 has supplied to respective inputs thereof the
`timing signal T52 and the inverse timing signals T—53
`and T54. The output of the NOR gate 134 is coupled
`to an input of the NAND gate 132. The NOR gate 136
`has suppliedgespective inputs thereof the inverse
`clock signal CLK, the write enable signal WE and the
`output of an inverter 138. The output of the NOR gate
`136 is supplied to a second input of the NAND gate
`132 whose output is supplied to one input of the NAND