CompactPCP
`
`Hot Swap
`Specification
`
`- -
`PICMG 2.1 R1.0
`
`May 1,1998
`
`HP-ACCP-1277596
`
`

`
`© Copyright 1997, 1998, PCI Industrial Computer Manufacturers Group.
`
`PICMG ® disclaims all warranties and liability for the use of this document and
`--~the-informa-tion-eontained herein-and-assumes no responsibility-for-any errors-or~---' - - (cid:173)
`omissions that may appear in this document, nor is PICMG ® responsible for any
`incidental or consequential damages resulting from the use of any data contained
`in this document, nor does PICMG ® assume any responsibility to update or
`correct any information in the publication.
`
`specification does not absolve manufacturers of
`Compliance with this
`Com actPCI ® Hot SwaR egui ment,
`from the reguirements of
`safetY'---,=,a,-,-,n-,,--d
`regulatory agencies (UL, CSA, FCC, IEC, etc.).
`
`_
`
`PICMG®, CompactPCI®, and the PICMG® and CompactPCI® logos are
`trademarks of the PCI Industrial Computer Manufacturers Group.
`
`All other brand or product names may be trademarks or registered trademarks of
`their respective holders.
`
`CompactPCf Hot Swap Specification, R1.0
`
`HP-ACCP-1277597
`
`

`
`Contents
`
`1
`
`INTRODUCTION
`
`1.1
`1.2
`1.3
`1.4
`1.5
`
`Ob'ectives of the Com aclPCI ® Hot Swa S ecification
`Applicable Documents
`Administration
`Name And Logo Usage
`Acronyms
`
`_______2__--'-O_V_E_RVIEW
`
`Hot Swap Terminology
`2.1
`2.1.1 Hot Swap Processes
`2.1.2 Hot Swap Components
`2.1.3 System Models
`2.1.4 Additional Terms
`2-:-2-Hot Swap System Al'Cllil'~rc
`2.2.1 System Models
`2.2.2 Basic Hot Swap System Model
`2.2.3 Full Hot Swap System Model
`2.2.4 High Availability System Model
`2.3
`Controlling the Connection Processes
`--------J)~.1-Hardware C-onnectiun-euntral~
`2.3.1.1
`Board Slot Control
`2.3.1.2
`Board Healthy
`2.3.1.3
`Platform Reset
`2.3.2 Software Connection Control
`2.3.2.1
`ENUM#
`2.3.2.2
`Handle Switch
`2.3.2.3
`Status LED
`2.3.2.4
`Hot Swap Control and Status Bits
`The Connection Processes
`2.4
`2.4.1 Physical Connection Process
`2.4.1.1
`Insertion Process
`:::-
`2.4.1 :2-Extractlon Process
`2.4.2 Hardware Connection Process
`2.4.2.1
`Hardware Connection States
`
`CompaclPCJ® Hot Swap Specification, R1.0
`
`1
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`HP-ACCP-1277598
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`

`
`Power Bus Isolation
`2.4.2.2
`CompactPCI @ Bus Isolation
`2.4.2.3
`2.4.3 Software Connection Process
`2.4.3.1
`Software Connection States
`2.4.3.2
`Initiation of Connection or Disconnection Processes
`2A.3-:3-Saftware-Cunnectron4"ransitilm
`2.4.3.4
`Software Disconnection Transitions
`2.4.3.5
`Completing the Connection or Disconnection Processes
`Interoperability
`2.5
`2.5.1 Platforms
`2.5.2 Boards
`2-:-5"":"3-----Sysmm-Confi-guratfuns
`
`34
`35
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`38
`8 ' - - - - - - -
`39
`40
`41
`41
`41
`42
`
`3
`
`CompactPC/@ BOARD REQUIREMENTS
`
`.45
`
`Electrical Requirements
`3.1
`3.1.1 Hot Swap Board Model
`3.1.2 CompactPC/@ Buffer VII Requirements
`--3-;1-:-3-Preeharge-Requirements
`Considerations for Selection of V PSOURCE, and Rp
`3.1.3.1
`3.1.3.2
`Special Signals
`3.1.4 CompactPC/@ Bus Isolation Requirements
`3.1.5 Early Power Usage
`3.1.6 Power Isolation
`---3r1.+----@4-Bit-lr-li.tiali.za.tiQn-.•.-~......_.·..·n·
`-~.-•... .. 70
`3.1.8 Resources for Software Connection Control
`3.1.8.1
`Hot Swap Control and Status Bit Definitions
`3.1.8.2
`EN UM#
`3.1.8.3
`Blue LED
`3.1.8.4
`Handle Switch
`3.1.8.5
`Implementation Requirements
`Mechanical Requirements
`3.2
`3.2.1 ESD Protection
`3.2.2 Protective Cover
`3.2.3 Mechanical Resources for Software Connection Control
`
`,
`
`4
`
`PLATFORM REQUiREMENTS
`
`Electrical Requirements
`4.1
`4.1.1 Clock Routing
`
`45
`46
`49
`58 - - - - -
`51
`52
`53
`54
`57
`S.9------
`60
`60
`61
`62
`62
`63
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`65
`65
`67
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`CompactPC~ Hot Swap Specification, R1.0
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`HP-ACCP-1277599
`
`

`
`70
`4.1.2 ENUM#
`70
`4.1.3 Power Distribution and Decoupling
`71
`4.1.4 Platform Termination of 64EN#
`71
`4.1.5 System Host Pullups
`71
`4.1.6 Hot Swap Platforms - Hardware Connection Control
`---------,4:1~7__rtigh--p.vailability Platforms--=-Hardware Connection-eontrol-..- -..-..- -..---'i.M - - - - -
`
`Mechanical Requirements
`4.2
`4.2.1 P1/P2 Pin Staging
`4.2.2 ESD Clips
`4.2.3 Other Considerations
`
`72
`72
`73
`73
`
`REAR-PANEL I/O TRANSITION BOARD SUPPORT
`5
`- - - - - - - - - -
`6
`SOFlWARE REQUIREMENTS
`
`- - - - -
`
`75
`
`77
`
`Overall Concepts
`6.1
`6.1.1 Relationship to PCI Hot-Plug Specification
`6.1.2 Levels of Compliance
`6.1.3 Layered Requirements for Different System Models
`- - - - - - - - -
`6.2
`General Use Compliance for Basic Hot Swap Systems
`6.2.1 System Software Requirements
`6.2.1.1
`[1.3.3] Programmatic Access to the Hot-Plug Service
`6.2.1.2
`[4.1.1] Items Specified by Operating System Vendor
`6.2.1.3
`[4.1.2] Quiescing Board Activity
`6.2.1.4
`[4.1.3] Initializing the Configuration Space Header
`- - - - - - - - - - -= -6.2.1.5
`[4.1.4] Board Option ROMs
`6.2.1.6
`[4.1.5] Device Driver Requirements
`6.2.1.7
`[4.1.6 & 3.1.1] Attention Indicator
`6.2.1.8
`[4.1.7] Hot-Plug Service
`6.2.1.9
`[4.1.8] Slot Identification
`6.2.1.10 Platform Resource Release Routine
`6.2.2 Platform-specific Software Requirements
`6.2.2.1
`[4.2.1] Hot-Plug System Driver
`6.2.2.2
`[4.2.2] Hot-Plug Primitives
`6.2.2.3
`[4.2.2.1] Querying the Hot-Plug System Driver
`6.2.2.4
`[4.2.2.2] Setting Slot Status
`6.2.2.5
`[4.2.2.3] Querying Slot Status
`--...--....--:-r6
`[4.2.2Af, synchronous Notification of Sio status Gl1ange
`6.3
`General Use Compliance for Full Hot Swap Systems
`
`77
`77
`77
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`80
`80
`80
`81
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`-..8.,.,.6r---
`87
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`
`iii
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`HP-ACCP-1277600
`
`

`
`6.3.1 Hot-Plug Service
`6.3.2 Hot-Plug System Driver
`6.3.3 Asynchronous Notification of Slot Status Change Primitive
`6.3.4 Setting Slot Status Primitive
`6.3.5 Querying Slot Status Primitive
`e-:3:6-lmp-lications for Inserfrorrand Extraction State-t>ragrams-of
`Section [3.1.8]
`General Use Compliance for High Availability Systems
`Hot-Plug Relationship Summary for General Use
`Software Requirements for Specific Use Compliance
`Cross-Platform Portability of Hot Swap Support Software
`
`6.4
`6.5
`6.6
`6.7
`
`7
`
`HOT SWAP SiLiCON
`
`Hot Swap Capable
`7.1
`7.1.1 PCI Specification 2.1 Compliant..
`7.1.2 Tolerate VCC from Early Power.
`7.1.3 Asynchronous Reset
`7.1.4 ToleratePrecfiarge 'Voltage
`7.1.5 I/O Buffers Must Meet Modified V/I Requirements
`7.1.6 Limited I/O Pin Leakage at Precharge Voltage
`7.2
`Hot Swap Friendly
`7.2.1 Hot Swap Control and Status Register
`7.2.2 Extended Capabilities Pointer
`7.2.3 -Remaining SOftware Connec Ion ControrResources
`7.3
`Hot Swap Ready
`7.3.1 Bias Voltage Support
`7.3.2 Early Power Support
`7.3.3 64 Bit Initialization
`
`APPENDIX A, IMPLEMENTATION EXAMPLES
`
`A.1
`A,2
`
`64-bit Peripheral Board Initialization
`Sample Circuit Implementation
`
`APPENDIX B. REVISION HISTORY
`
`88
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`iv
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`CompactPC~ Hot Swap Specification, R1.0
`
`HP-ACCP-1277601
`
`

`
`1 Introduction
`
`1 INTRODUCTION
`
`This specification applies to 33MHz and 5V operation only. Operation at 3.3V
`and other frequencies are not precluded. These configurations haven't been
`validated at the time of this release of the specification.
`
`In this specification the following key words (In bo -text) will be used:
`
`may:
`
`indicates flexibility of choice with no implied preference.
`
`should:
`
`indicates flexibility of choice with a strongly preferred implementation.
`
`implement such
`indicates a mandatory requirement. Designers shall
`shall:
`____m_an---,-d_a_to_1Y reguirements to ensure interchan eability and to claim
`conformance with this specification.
`
`1.1 Objectives of the CompactPCI ® Hot Swap Specification
`
`The primary objective of this specification is to extend CompaclPCI ® to Hot
`Swap applications. Hot Swap defines a process for installing and removing
`boards without adversely effecting a running system.
`
`CompaclPCI ® Hot Swap allows board vendors and platform vendors to add
`functionality and cost incrementally to a system. CompactPCI ® Hot Swap
`can be simple and inexpensive to implement.
`
`It is the intent of this document to do the following:
`
`_________------'1...:...._S::-,,-,e:....:c:..:..cify what board vendors must do to enable a board to be Hot
`Swappable and interoperable across the full range of systems including
`hot swap and non-hot swap systems.
`
`_
`
`2. Specify the required features for Hot Swap Systems so operating system
`vendors can be assured of a minimum feature set.
`
`3. Establish a framework for terminology and overall architecture of a Hot
`Swap system. The responsibilities of the platform vendor, operating
`system vendor, and board vendor are assigned based on this framework.
`
`4. Specify the required features for silicon vendors to develop hot swap
`silicon.
`
`It is a goal of the Hot Swap Specification to be compatible with the PCI Hot(cid:173)
`Plug Specification whenever possible, especially as it pertains to Hot-Plug
`-------------=-capable drivers ana as software supponng pcrHot-Plug.
`-----~-
`
`CompactPCf® Hot Swap Specification, R1.0
`
`1
`
`HP-ACCP-1277606
`
`

`
`1 Introduction
`
`It is not the intent of this specification to:
`
`1. Specify a detailed implementation for Hot Swap CompactPCI ® Systems.
`The
`greatest
`latitude
`possible
`has
`been
`allowed
`for
`product
`differentiation, and still maintain interoperability.
`
`------2-..-Speeify-tl:le-implementation-fm-l=Iot---Swap oftware....rolJtines.-------Concept,::>------(cid:173)
`and features are presented, but implementation is strictly determined by
`the individual operating system requirements.
`
`1.2 Applicable Documents
`
`industry
`This CompactPCI ® Hot Swap Specification builds on several
`standards. You should reference the following list of publications while
`-------:=re=-ca=m:::-:g=---·II:~ls::--=specification .
`
`• PICMG 2.0, CompactPCI ® Specification, Revision 2.1,
`PCI Industrial Computer Manufacturers Group (PICMG),
`301 Edgewater Place, Suite 220, Wakefield, MA 01880 USA,
`Tel: 781.224.1100, Fax: 781.224.1239, www.picmg.org
`
`------,.-P-ICMG 2.5, CompaGtP-G/~Gomputer Telephony..SpeGifiGatien,
`PCI Industrial Computer Manufacturers Group (PICMG),
`301 Edgewater Place, Suite 220, Wakefield, MA 01880 USA,
`Tel: 781.224.1100, Fax: 781.224.1239, www.picmg.org
`
`• PICMG 2.7, CompactPCI ® 6U Dual System Slot Specification,
`PCI Industrial Computer Manufacturers Group (PICMG),
`301 Edgewater Place, Suite 220, Wakefield, MA 01880 USA,
`-------...........-eI:781.224.1100, Fax: 78;rZ24~l239, www.plcmg.org------------
`
`• PCI Local Bus Specification, Revision 2.1
`PCI Special Interest Group,
`5200 N. E. Elam Young Parkway, Hillsboro, Oregon, USA, 97124-6497,
`(503) 696-2000, www.pcisig.com
`
`• PCI Hot-Plug Specification, Revision 1.0
`PCI Special Interest Group,
`5200 N. E. Elam Young Parkway, Hillsboro, Oregon, USA, 97124-6497,
`(503) 696-2000, www.pcisig.com
`
`• PCI Power Management Interface Specification, Rev. 1.0, June 30, 1997
`PCI Special Interest Group,
`5200 N. E. Elam Young Parkway, Hillsboro, Oregon, USA, 97124-6497,
`(503) 696-2000, www.pclsig.com
`
`2
`
`CompactPC~ Hot Swap Specification, R1.0
`
`HP-ACCP-1277607
`
`

`
`2 Overview
`
`2 OVERVIEW
`
`The basic purpose of the Hot Swap additions to CompactPCI ® is to allow the
`orderlv insertion and extraction of boards without adversely affecting system
`operation. This is done for repair of faulty boards or reconfiguration of a system.
`
`Additionally, Hot Swap provides programmatic access to Hot Swap services
`allowing system reconfiguration and fault recovery to take place with no system
`down time and minimum operator interaction.
`
`Finally, for High Availability applications, Hot Swap allows the system to isolate
`faulty boards so a system can continue operation (possibly with reduced
`capability) in the event of a failure.
`
`the terms used to describe the
`This overview begins with definitions for
`components and processes of Hot Swap. Then, a top down description of a
`CompactPCI ® Hot Swap system's architecture is presented. The architecture
`defines system models that differ in behavior due to different sets of features.
`
`The architecture for Hot Swap is layered. From a system standpoint, a minimum
`set of Hot Swap capabilities is defined. Additional capabilities can be added if
`the application warrants the additional hardware and software. By layering the·----(cid:173)
`capabilities, a wide range of applications can be addressed with minimal
`interoperability problems.
`
`The overview then moves into more detail about the Hot Swap processes and
`the control mechanisms for those processes. The layering of these control
`mechanisms determines the system's features.
`At
`the conclusion of
`the
`o.vervlew-is asummary-oUbe-various_platfor:m_andho.ard_cornbinations.
`
`CompactPC~ Hot Swap Specification, R1.0
`
`7
`
`HP-ACCP-1277612
`
`

`
`2 Overview
`
`2.1 Hot Swap Terminology
`
`2.1.1 Hot Swap Processes
`
`Hot Swap can be described in terms of three processes:
`
`--------,--12Ry-siGal-CQr:meGtion P-rocess - desGribes-tRe--aGts--Qf~:- - - - - - - - - - - - -
`
`Hot Insertion - by which a board is installed in a live system.
`
`Hot Extraction - by which a board is removed from a live system.
`
`• Hardware Connection Process - describes the electrical connection
`(and disconnection) of the hardware layer to the system.
`
`• Software Connection Process - describes the connection (and
`disconnection) of the software layer(s) to the system.
`
`These processes can be described further as a group of states. These
`states are codependent, but represent different
`layers of the overall
`system. For example:
`If the physical connection does not exist,
`the
`hardware layer cannot make electrical conn..ection.
`If the board is active
`in a system, and is extracted, the software and hardware connections
`cease to exist. The figure below illustrates these relationships:
`
`HARDWARE
`PHYSICAL
`CONNECTION CONNECTION STATES
`STATES
`_0
`0
`PO - - P1
`HO
`
`a
`0
`H1
`
`H1F
`
`SOFTWARE
`CONNECTION
`STATES
`
`a
`
`S1
`
`0
`
`S2
`
`S2Q
`
`0
`
`S3
`
`S3Q
`
`H2
`so
`
`Figure 1: Hot Swap States
`
`PO - The board is physically separate from the system.
`
`P1 / HO - The board is fully seated, but not powered, and not active
`on the PCI bus.
`
`•
`
`•
`
`Note that at this point,
`_____l.ay_eJ:lsjJl_:.I::J'O~.
`_
`
`the physical
`
`layer is in "P1", the hardware
`
`• H1 - The board has powered up and is sufficiently initialized to
`connect to the PCI bus.
`
`8
`
`CompactPC~ Hot Swap Specification, R1.0
`
`HP-ACCP-1277613
`
`

`
`2 Overview
`
`• H1F - The board has been commanded to power up and initialize and
`has failed, or the board has detected an error and disconnected itself
`from the PCI bus. The board is not suitable for connection to the PCI
`bus.
`
`• H2 / SO - The board is powered, and enabled for access by the PCI
`- - - - - - - - - - - - Ibu s in--configuratioM'-space-only:-Ttle board!s--configuration-space-is
`not yet initialized.
`
`Here, the hardware layer is in "H2" and the software layer is in "SO".
`
`• S1 - The board is configured by the system.
`
`• S2 - The necessary supporting software (drivers, etc.) are loaded.
`fie Doara is reaClyor use by theOS----aridlor ApplicatiOn-;- bOCn"'o..-----(cid:173)
`operations involving the board are active.
`
`• S2Q - This state is the same as state S2, but no new operations are
`allowed to start. The board is quiesced.
`
`• S3 - The board is engaged in software operations.
`
`• S3Q - The software is completing current operations, but
`allowed to start new ones.
`
`is not
`
`2.1.2 Hot Swap Components
`
`Board (PCI SIG uses add-in board or adapter card) - Any circuit board in
`the system. CompaclPCI ® differs from other PCI based systems in that
`------------t:he-system host is-also-a-removable-boarct-Hot S-wap-is-not limitecHn--(cid:173)
`adapter (non-host) boards, but at this time this specification does not
`address swapping the system host.
`
`System Host - The central resource that provides configuration of the
`CompaclPCI ® bus.
`It typically also provides central services like clocks
`and arbitration for the CompaclPCI ® bus. The system host plays a
`central role in the "Dynamic Configuration" of a system.
`
`Platform - The platform provides the infrastructure for the boards. This
`includes (but
`is not
`limited to) backplane, system host, cooling, and
`power supplies.
`
`For the purposes of defining the required features for components of a
`Hot Swap system, a "board" is any board other than the system host.
`---------I--he capabilities-of-a platform-rnclude the-feature
`'ncluded-in--the(cid:173)
`backplane and the system host board,
`
`CompactpcJ® Hot Swap Specification, R1.0
`
`9
`
`HP-ACCP-1277614
`
`

`
`2 Overview
`
`2.4 The Connection Processes
`
`The "Process" of Hot Swap can be broken down into three smaller
`processes: Physical, Hardware, and Software. Previous sections describe
`these processes in general
`terms. This section defines these processes.
`These processes remain the same for all system models. Only the control of
`these-pracesse
`changes-.-The-diagrams-tJetow-provide-
`"real time"-------(cid:173)
`illustration for some of the signals involved in the insertion and extraction
`processes.
`
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`
`26
`
`CompactPCfl Hot Swap Specification, R1.0
`
`HP-ACCP-1277631
`
`

`
`f'
`
`HEA(THY#
`,
`
`,
`
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`
`HardWare Connection
`
`•
`
`Physi6a1 Connecllo
`
`Figure 20: ,Board Extraction !Example
`
`Early~ower_
`It
`B ""'~~-"P ·1 , ~
`·ower
`.acl\ I0OI"1:1
`II
`~J;; .'
`1
`BD_SEL#
`I~
`~ Interface C IPl!
`,.
`--------~ -, ...
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`

`
`2 Overview
`
`2.4.1 Physical Connection Process
`
`The Physical Connection Process operates the same regardless of the
`The
`the Hardware and Software Connection Processes.
`state of
`physical connection process begins with the introduction of a board to
`It ends with the mating of the short pin BD_SEL#. Physical
`the platform.
`-------BiseenFleetien is nearly-tRe-r-evers .
`
`The physical connection process is defined by the motion of a board in or
`out of the system and the various staging of contacts in the system.
`It is
`crucial
`to understand that this is a mechanical process with unstable
`events and variable durations.
`
`MOTION DURING INSERTION
`- - - - - -
`,-----,1 c:::::J "'-1- - - - - - - - - - . ,1 ESD CARD GU IDE
`
`.---------." EARLY VOLTAGES
`
`L"'> 'I ALL BUS PINS
`
`IIji
`
`- (cid:173)
`
`I -
`
`VW"- - Example
`Mechanical Bounce
`
`TIME
`
`Figure 21: Mechanical Insertion
`The 10fl§est-eenlaet-in the systeFfl-is-tl=le-ESD -Board-§l:liEle,-R-efer to-tAe-------(cid:173)
`mechanical section of the CompactPC/@ Specification for details. Full
`implementation of the ESD protection is required for Hot Swap. See
`sections 3.2 and 4.2 for the specific requirements.
`
`to
`taken any ESD precautions prior
`the operator has not
`If
`Note:
`insertion or extraction, the board, like any electronic component, could
`be damaged.
`Normal ESD protection should be used when hot
`swapping boards.
`
`levels
`The backplane pin staging (see Section 4.2.1) provides additional
`of connection. Two of each of the +5V, +3.3V, via pins, and several
`GND pins, are the longest (first to make, last to break). Any or all of
`these voltages may be used to provide Early Power to the hardware
`connection layer prior to the bus pins mating. Current drawn at this
`--~·ta~e-h-as--a-stated maximtlm-that must be observeft-.--
`
`There is no guaranteed order for these early voltages (including ground).
`Designers using Early Power must be aware of the potential for sneak
`
`28
`
`CompactPC{& Hot Swap Specification, R1.0
`
`HP-ACCP-1277633
`
`

`
`2 Overview
`
`current paths which might exist between Early Power Potentials, signals,
`It is recommended that only one
`etc. in the absence of a stable ground.
`of the early potentials be used to minimize this possibility.
`
`All the PCI bus and other signals are medium length. Precharge is used
`to minimize the capacitive effects of the board as it contacts the bus.
`
`BD_SEL# is a short pin. When this pin mates the physical connection
`process is finished.
`
`The following chronology of the board insertion and extraction process
`walks the reader through the events that take place when a board is
`inserted and extracted.
`
`nsert;on-Process~--------------
`
`1. The board is in "PO" state (not installed).
`
`2. The Physical Connection Process begins.
`
`3. The operator picks up a board in order to install it in the system.
`
`4:-Tneooard enters me cara-glliae.
`
`5. The board front panel
`bleed resistor.
`
`is discharged to chassis ground through a
`
`6. The board logic ground is discharged to chassis ground through a
`bleed resistor.
`
`cassis groun
`
`oglc
`
`8. The front panel makes low resistance contact with chassis
`ground through the card guide.
`
`9. The board contacts long pins on backplane, and begins to
`contact ground, +5, +3.3V, and via pins.
`
`10.The board is in an unstable state while pins are first mated. This
`duration is not specified and can potentially be infinite if the board
`is just marginally connecting the longest pins.
`
`11. Enough pins are connected that a stable Early Power can be
`achieved.
`
`• CompaclPCI ® bus interface logic is powered up, and
`decoupling capacitors attached to Early Power are charged.
`
`CompaclPCJ® Hot Swap Specification, R1.0
`
`29
`
`HP-ACCP-1277634
`
`

`
`2 Overview
`
`is driven active.
`• The board's LOCAL_PCI_RESET# signal
`The LOCAL_PCI_RESET# remains asserted throughout the
`physical connection process. The PCI chip asynchronously 3(cid:173)
`states all PCI signals as required by the PCI Local Bus
`Specification.
`
`----------.-E-ar~y_Pewer--Aas-stabili-zeEl--alf-ef-the-CompaetPGI!L-el:l~------­
`signals to the signal precharge potential (-1V).
`
`• Hardware puts the Hot Swap (blue) LED in the ON state.
`
`12. The board contacts the medium length pins on the backplane.
`These pins will make contact in a random manner.
`
`--------;•..--''flTe"'lariol1SCc:JmpactPC,-@1)us-pinsmaRe-firsteontactwith
`the bus. Disturbance to active bus signals does not cause
`logic thresholds to be violated.
`• The board's CompactPCI ® pins begin to track the levels on
`the PCI bus. The board is now receiving the PCI clock.
`
`• Medium length power pins contact and short out the current
`----------------------------------------------------timiting-r-esisters-:--~nptJt_pewer--to-the_power-isolatiofl-eiretJit-ry----------------------------­
`is available (Back-End power is still turned off at this point.)
`13.The board contacts the short BD_SEL# pin. This pin is grounded
`on the backplane (or controlled for HA platforms) and pulled high
`Its assertion indicates that the
`by a pullup resistor on the board.
`board has been fully inserted into the backplane.
`
`----------lL-IPrecharge potel=ltial-is-optionally removed-tr-om-each sigrJElI,~.- - - (cid:173)
`
`• The board enters "P1" state (installed).
`
`2.4.1.2
`
`Extraction Process
`
`Extracting a board in some other state than SO may crash the
`system for other reasons, but
`the physical disconnection will not
`disrupt the CompactPCI ® bus.
`
`1. The board is in the "P1" state (installed).
`
`2. The operator starts to withdraw the board.
`
`The hardware transitions
`3. The BD_SEL# pin disconnects.
`immediately to HO and the software is assumed to be in state SO
`- i f it-has-tr!-t
`-IreaEly-made -tha-t-tr-Bflsitiofl-as part- (;)f--a'fl-orEler~y­
`process.
`
`30
`
`Compactpcf& Hot Swap Specification, R1.0
`
`HP-ACCP-1277635
`
`

`
`2 Overview
`
`•
`
`LOCAL_PCI_RESET# is activated for the peripheral logic if it
`has not already been activated as part of a High Availability
`Extraction or failed insertion. The PCI chip asynchronously 3(cid:173)
`states all PCI signals as required by the PCI Local Bus
`Specification.
`
`-------------.-----f-he-Hardware-6onn-eetion-!::ayer-turns-on-the-blue !::E&-if-it----(cid:173)
`hasn't already been turned on by software.
`
`• Precharge power is reapplied if it had been removed as part
`of the insertion process.
`
`• Back-end power is turned off if it has not already been turned
`off as part of a High Availability Extraction or failed insertion.
`- - - - - -
`- - - - - - - - - - - - - - -
`•
`If
`the board has developed hazardous potentials during
`those potentials must be discharged before the
`operation,
`operator can make unintentional contact with them.
`
`• Board logic should be stabilized at this point such that any re-
`insertion will not cause bus or power subsystem faults due to
`---,deeaying-perif}Meral---powefj---paftfaHy-valid-memory-leeatie1lS,-------(cid:173)
`etc.
`
`4. Medium length CompactPCI ® pins disengage.
`
`5. Long length CompactPCI ® pins disengage.
`
`• Early power goes away.
`- - - - - - - - - - - - - -
`- - - - - - - - - - - - -
`• Board is in an unstable state while pins are first disconnecting.
`This duration is not specified and can potentially be infinite if
`the board is just marginally connecting the longest pins.
`
`6. Board logic ground is connected to chassis ground through a
`bleed resistor.
`
`7. The board front panel
`bleed resistor.
`
`is connected to chassis ground through
`
`8. Board leaves the ESD card guide.
`
`9. The board is in the "PO" state (not installed).
`
`CompactpcJ® Hot Swap Specification, R1.0
`
`31
`
`HP-ACCP-1277636
`
`

`
`2 Overview
`
`2.4.2 Hardware Connection Process
`
`Hardware Connection is facilitated by the Hardware Connection Layer.
`The hardware connection layer consists of two essential components:
`
`Power Bus Conditioning provides protection for the system power bus,
`- - - - - - --and-allo-wsJoLpmper initialization-oUbe_board. - - - - - -
`
`CompactPCI ® Bus Conditioning allows for orderly connection and
`disconnection from the CompactPCI ® bus.
`
`The operation of the hardware connection layer is controlled by the
`platform. All boards must implement this control process:
`
`---------2;-4.2.1,
`
`Hardware-Gonnection State~-----------
`
`Hardware Connection begins when the board has reached the HO
`state.
`It ends with either
`the H2 state or
`the H1 F state.
`Disconnection is the reverse process.
`
`the HSC being high
`• HO - is distinguished by the output of
`the
`impedance and the BD_SEL# signal being pulled up- b
`board. The HO state is exited when BD_SEL# is driven active.
`(In systems that ground BD_SEL# on the backplane, this state is
`transitory).
`
`• H1 - is distinguished by BD_SEL# driven active, and HEALTHY#
`driven active.
`
`--------~,. H1F--~s-Q~stin9blished-by-g~R_#_aGtive_and Me-A-'=-T-Fl-Y-#-r-'lQt.-----(cid:173)
`being driven.
`
`• H2 - occurs when the board has reached the H1 state and
`PCI RST# is inactive.
`
`32
`
`CompactpcJ® Hot Swap Specification, R1.0
`
`HP-ACCP-1277637
`
`

`
`Note: HO, H1 F
`PCI_RST# = HI L
`
`2 Overview
`
`r..-------······H"o"..,,-··,,"-····..··-....-·l
`I
`ILOCAL PCI RST# =TRUE I
`IHEALTHY# = Hi Z
`.._._,
`."........_ ...... _7._....-=
`
`BD_SEL# = TRUE (LOW) &
`Power Good = TRUE
`
`["·..--..-_ ·..····_-_·....·_···-··..·..·····_..·1
`,
`H1
`;
`IHEALTHY# = TRUE (LOW) I
`L~g~~..~.....~5?L. RS!tt.:-_.-.....-.._-1_- - - - -
`
`PCI_RST# = TRUE
`
`__ PCI_RST# = FALSE &
`Power Good = TRUE
`
`r···......--···....··..·..·..···--_··-_..·..·..··.._·_-_··-
`H2
`1
`i
`iHEALTHY# =TRUE
`; LOCAL_PCI_RST# =
`
`r __••••••••••••__
`
`_
`
`__ ~••_._
`
`I
`
`11
`
`..
`
`BD_SEL# = TRUE (LOW)
`Power Fault = TRUE
`r..·..·····__··..··..·..__··..···""·"··,,·..,,·,,,,····,,···..·····""""'1
`H1F
`!
`!
`!
`iHEALTHY# = Hi Z
`i LOCAL PCI RST# = TRUE!
`
`;\
`
`/,,,/
`\/...
`BD_SEL# =Hi
`
`l-,..._..__.._"':::
`
`.._.=::._.•.._..•. ,.~....•.._.....
`
`t
`
`Power Fault = TRUE
`
`PCI_RST# = TRUE +
`Power Good =FALSE &
`Power Fault = FALSE
`......----....-.....-
`\ - - - - - ...,,,
`
`Note:
`Power Good =BD_SEL# TRUE
`& Voltages in tolerance
`
`PCI_RST# =FALSE
`& Power Good =
`Power Fault = BD_SEL# TRUE
`--&-Ve!tages eut ef-teleranee----------\.---1-T-RlJ
`& Time to stabilize has expired
`Figure 22: Hardware Connection States
`
`Some notes about the states:
`
`There is a period of time when a board is neither in the H1 state nor
`Internal to the board,
`the power controller should
`the H1 F state.
`assert a Power Good indication or a Fault indication (these are not
`necessarily the same signal) to determine the appropriate state.
`
`The outward indication of this condition and the H1 F condition is the
`same (HEALTHY# FALSE).
`Systems controlling the Hardware
`Connection Process must allow time from the assertion of BD SEL#
`to the assumption of H1F.
`
`is by
`Loss of HEALTHY#, once H1 or H2 has been established,
`definition H1F.
`If a latch is used in the board's hardware to retain the
`H1 F state, it must be reset with the removal of BD_SEL# (HO).
`
`CompactPC~ Hot Swap Specification, R1.0
`
`33
`
`HP-ACCP-1277638
`
`

`
`2 Overview
`
`The hardware connection logic will
`except H2.
`
`illuminate the LED in all states
`
`HEALTHY# may be expanded to include more information than just
`the power supplies are good. As an example: HEALTHY# may be
`tied to a watch dog timer
`refreshed by a back end processor.
`--------HEAb-T-Fl¥--#-may bE7-Flr-edieateEl- by Gsmpleti0R-ef-tAE7-sear-El.!.s-euilt.--l'A--- - - - - (cid:173)
`self test. Any implementation of HEALTHY# must follow these rules:
`
`• HEALTHY# must always include the power good function.
`
`•
`
`•
`
`LOCAL_PCI_RESET# will not be released until HEALTHY# is
`TRUE.
`If
`that reset
`is used to reset
`the entire board,
`the
`assertion of HEALTHY# must not be locked out by this reset.
`
`LOCAL_PCI_RESET# will be asserted immediately with the loss
`of HEALTHY#,
`
`2.4.2.2
`
`Power Bus Isolation
`
`The power isolation circuitry powers a board up and down without
`__--'causjng the system s_upplie-s_to...exceed theiL(egulatiDn spe..cifications ..
`The required attributes of the power isolation scheme are:
`
`_
`
`• Controlled turn on and off of power to the back end logic
`
`• Current Limit
`
`• Voltage monitoring and sequencing
`
`Controlled turn on and off is necessary to limit the current transient
`felt by the system supplies. Also, boards and IC's may not initialize
`properly without a clean power ramp from the supplies.
`
`Current limit is essential to protect the system. The CompactPCI ®
`Bus provides a certain number of pins to each slot for power, A
`board can not exceed the rating for those pins as it will damage the
`system.
`It is also a good idea to protect the board from serious
`damage should a component fail.
`
`Voltage monitoring and sequencing is a requirement. A board must
`not be allowed to connect itself to the bus if the Back End Power is
`in some
`not fully within specification. Sequencing is also critical
`applications. Many IC's use multiple voltages.
`If a failure occurs in
`- - - - - -one voltage.,the-Qther--vGlt-ages must be-sl:llJt-Qff-as-well-.-
`
`34
`
`CompactPC~ Hot Swap Specification, R1.0
`
`HP-ACCP-1277639
`
`

`
`2 Overview
`
`2.4.2.3
`
`CompactPCI @ Bus Isolation
`
`A CompactPCI ® Hot Swap board will be inserted and extracted from
`It is essential that
`a live bus that can be in any stage of a bus cycle.
`Hot Swap boards have a benign effect during all states from HO to
`H2.
`
`All CompactPCI ® Bus connections must remain high impedance
`until the H2 state. When H1 is reached, the board may loca