United States Patent [191
`Bartol
`
`[54] SYSTEM FOR COMPUTER PERIPHERAL
`BUS FOR ALLOWING HOT EXTRACI‘ION
`ON INSERTION WITHOUT DISRUPTING
`ADJACENT DEVICES
`[75] Inventor: Thomas M. Bartol, Hillsborough,
`N.C.
`[73] Assignee: International Business Machines
`cm'l’mtmn’ Ammk’ N-Y-
`[21] Appl. No.: 957,746
`.
`_
`[22] Flled.
`
`Oct. 7, 1992
`
`[63]
`
`Related US. Application Data
`.
`.
`glgrné‘rjnuatlon of Ser. No. 364,742, Jun. 9, 1989, aban-
`'
`[51] Int. Cl.5 ............................................ .. G06F 13/00
`[52] us. c1. .................................. .. 395/500; 364/514;
`364/DIG. 2; 395/325; 395/800
`[58] Field Of Search ..................... .. 395/500, 325, 800;
`'
`354/132, 514; 439/56, 59; 361/407, 41-3
`References Cited
`U'S‘ PATENT DOCUMENTS
`3,691,432 9/1972 Edfors er al. ..................... .. 317/100
`12;
`gbeilssa? - - ~ - - - - ~ -
`- -
`
`[56]
`
`lllllllllllllllllIllllllllllllilllllllllllllllllllllIllllllllllllllllllllll
`[111
`5,210,855
`[45]
`May 11, 1993
`
`US005210855A
`Patent Number:
`Date of Patent:
`
`4,750,136 6/1988
`4,778,398 10/1988
`4,819,149 4/1989
`$33313? 1311333
`4,897,055 1/1990
`4,999,787 3/1991
`OTHER PUBLICATIONS
`Small Computer Interface (SCSI), ANSI, Dec. 1989,
`pp. 1.1, 22-25.
`Small Computer Interface-2 (SCSI-2) ANSI, Mar.
`1989, 5 n O I, H1942).
`
`Primary Examiner-Thomas C. Lee
`Assistant Examiner-L. Donaghue
`Attorney, Agent’ or Fim__win?eld J‘ Brown’ Jr’; John
`C. Black
`
`ABSTRACT
`[57]
`A method and apparatus for rapid interconnection (hot
`plugging) periphgral device interface circuits {0 a com
`pu'ter bus is disclosed. The interconnections are com
`pleted using thrice sets of tc_;ondu;:1to1t;s in tl‘ije Csequence:
`common groun 5, power romt e 11s an
`ata mes.
`The time period between the interconnections is deter
`mined by the relative set back lengths of the conductors
`from the card edge and allows for stabilization of volt
`
`,
`
`1
`
`4,479,692 10/1984 Greenwood
`4,510,553 4/1985 Faultersack
`
`on omme
`
`.... .. 339/99 R fa 31nd esiatilhsh?m .°f a statblenhlgh. lmgedggfe “3:8
`.. 351/413
`°t .cpenp .m “we con ‘0 e‘ mm” 5
`ore 6
`
`-
`
`.
`
`.
`
`4,582,381 4/1986 Bisczat . . . . . . . . . . . .
`
`. . . . .. 339/82
`
`dam lmes are lmerconnected
`
`439/426
`4,678,257 7/1987 Ahronl .................. ..
`4,747,783 5/1988 Bellamy et al. ..................... .. 439/59
`
`>
`6 Claims, 5 Drawing Sheets
`
`L
`
`L
`
`/7
`
`.._........._........ To
`_.._____---_ T 1
`
`UUUUUUUUU
`
`CIRCUIT BOARD
`
`28
`
`

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`U.S. Patent
`
`May 11, 1993
`
`Sheet 1 of 5
`
`5,210,855
`
`10
`
`H H
`
`COMPUTER HOST ADAPTER \
`
`'12
`
`14
`
`MAG. DISK
`\E-S-JBUS CONTROLLER
`
`(
`<5
`
`(5
`
`S
`
`5
`
`S
`
`16
`
`19
`
`2 1
`
`23
`
`1.8
`f
`OPTICAL DISK
`
`CONTROLLER
`
`20
`r
`MAG. TAPE
`
`CONTROLLER
`22
`/
`PRINTER ,
`CONTROLLER
`
`24
`
`OTHER DASD
`
`CONTROLLER
`
`5 5
`
`25
`
`FIG. 1
`PRIOR ART
`
`

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`US. Patent
`
`May 11, 1993
`
`Sheet 2 of 5
`
`5,210,855
`
`CONTROLLER
`LOGIC
`CIRCUITS
`
`FIG. 2
`PRIOR ART
`
`

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`US. Patent
`
`May 11, 1993
`
`Sheet 3 of 5
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`5,210,855
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`B.-___
`C.
`
`OUTPUT
`
`H
`
`I
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`48
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`UFIG.3A
`
`TRI-ST
`
`OUTPUT
`
`

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`US. Patent
`
`May 11, 1993
`
`Sheet 4 of 5
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`5,210,855
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`

`
`US. Patent
`
`May 11, 1993
`
`Sheet 5 of 5
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`5,210,855
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`L2 L1 62
`60
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`
`

`
`1
`
`SYSTEM FOR COMPUTER PERIPHERAL BUS
`FOR ALLOWING HOT EXTRACTION ON
`INSERTION WITHOUT DISRUPTING ADJACENT
`DEVICES
`
`This is a continuation of copending application Ser.
`No. 07/364,742, ?led on Jun. 9, 1989, now abandoned.
`
`20
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`5,210,855
`2
`peripheral devices such as rigid or ?exible disks, mag
`netic tape drives, printers, optical disks and other direct
`access storage devices (DASD). Such devices will here
`after be referred to as either SCSI compatible devices or
`more generally as peripheral devices. The primary ob
`jective is to provide host computers with device inde
`pendence within a class of devices of SCSI to enable a
`variety of different devices to be added to host comput
`ers without requiring modi?cations to generic system
`hardware or software.
`Several draft speci?cation proposals were presented
`by the American National Standards for Information
`Systems, including those dated Dec. 16, 1985 and Mar.
`16, 1989. In Section 4.4 of the SCSI speci?cation, there
`is presented the electrical description for the SCSI bus.
`The speci?cation allows for the use of TTL technology
`for the device controllers so that either open collector
`or tri-state driver devices may be used for interconnect
`ing to the SCSI bus. There are considerable differences
`in the two types of driver devices since tri-state devices
`are considerably faster at coming up to operational
`logic voltage levels than are open collector devices.
`However, there are many advantages to expanding the
`types of TTL logic devices which may be connected to
`the SCSI computer bus. The inclusion of both open
`collector and tri-state devices for interconnection by a
`hot plugging method, as will be described later, was
`discovered to cause operational problems on the SCSI
`bus. With the widening use of SCSI buses and SCSI
`compatible devices an attempt was made to use hot
`plugging techniques on SCSI compatible devices in a
`fault tolerant environment. The use of SCSI compatible
`devices in a hot plugging mode would greatly enhance
`the availability of these devices for fault tolerant opera
`tion. However, it was discovered that while many such
`devices worked with the usual hot plugging technique,
`some types of SCSI compatible devices disrupted ongo
`ing transfers on the data bus when they were connected.
`Thus the problem of hot plugging permitted devices
`to a SCSI bus has not been encountered before and the
`prior art methods and apparatus of providing ground
`contact prior to connecting power and signal to trans
`mit or receive data can in many instances cause disrup
`tion of the two-way data flow on the SCSI bus. While
`the problems were discovered with respect to the two
`types of TTL devices permitted by the SCSI speci?ca
`tion, the problems also exist for hot plugging of NMOs
`and CMOS implemented peripheral devices, for exam
`ple, onto a computer bus. There must be a sufficient
`delay for all peripheral devices to assume a stable high
`impedance state before data bus connection can begin. '
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to computer buses and
`particularly to a method and apparatus for facilitating
`the rapid interconnection of peripheral device interface
`circuits to a computer bus to establish both power and
`two-way data transfer. The interconnection is done in a
`“hot plug” mode in that neither power nor the data
`transfer are interrupted during the interconnection of a
`new peripheral device.
`2. Description of the Prior Art
`Various methods and apparatus for the rapid inter
`connection of peripheral device interfaces or control
`circuits to computer buses are known in the art. In an
`effort to minimize the impact of plugging into a bus, the
`normal procedure has been to shut down the bus so that
`new devices would not disrupt data flow on the bus. In
`contrast the hot plugging concept provides both power
`and data transfer interconnections without causing in
`terruption of ongoing data transfers on the bus. Hot
`plugging is found in fault tolerant systems which nor
`mally include device or ?eld replaceable unit redun
`dancy coupled through operational comparison and
`checking logic to ensure correct operation. When a
`fault is detected an indication of the failing device is
`provided to service personnel. The failing device is then
`simply removed from the bus and a replacement device
`connected. The removal of the failing device and the
`replacement of a new device are performed without
`regard to ongoing bus activity. Both the bus architec
`ture and the control device electronics must be care
`fully designed to achieve this “hot plugging” capability.
`The normal control circuits contain electronic micro
`chips mounted on printed circuit (pc) boards. A voltage
`regulator is included on the p.c. board and circuit inter
`connections to the bus and for power and data transfer
`are made via edge connectors. ‘Edge connectors are
`mounted on a printed circuit board which is plugged
`into a corresponding receptacle for connection to the
`bus. Plugging in the board makes electrical contact
`between the edge connectors and the corresponding bus
`receptacle and thus provides both power to the elec
`tronic components on the pc board and interconnects it
`with the bus in one operation. For hot plugging, the
`normal method of interconnection is to increase the
`length of at least the ground contact on the edge con
`nector, so that a ground contact can be completed prior
`to the electrical connection of the other contacts for the
`application of power and the transfer of data signals.
`Because of the control of the design parameters of the
`bus architecture and control circuits, hot plugging such
`circuits into a computer bus ordinarily causes no disrup
`tion in the two—way transfer of information on the bus.
`Of particular interest is the widening use of the stan
`dardized (Small Computer System Interface (SCSI))
`bus. The standard de?nes the mechanical, electrical,
`and functional requirements for a small computer input
`/output bus and command protocols to enable attaching
`small computers with each other and with intelligent
`
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`OBJECTS OF THE INVENTION
`It is an object of the invention to provide a method
`and apparatus for the rapid interconnection of periph~
`eral devices to and a computer data bus without disrupt
`ing the transfer of data on an active bus.
`It is a further object of the present invention to pro
`vide a method and apparatus to enable the hot plugging
`of any speci?ed peripheral direct access storage device
`to a standardized Small Computer System Interface
`(SCSI) bus without disrupting the ongoing transfers of
`data on an active bus.
`
`65
`
`SUMMARY OF THE INVENTION
`A method of rapid interconnection by means of a
`multi-conductor connector for-connecting peripheral
`device controller circuits to a computer bus, which bus
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 shows in block diagram form the interconnec
`tion of several peripheral devices and controllers to a
`SCSI bus for a single computer.
`FIG. 2 shows an edge connector mounted on a con
`troller logic circuit PC board and a corresponding mat
`ing connector for interconnection with a computer data
`bus.
`FIGS. 3A and 3B show examples of the electrical
`schematics for open collector and tri-state TTL type
`controller circuits for computer peripheral devices.
`FIGS. 4A and 4B show respectively the voltage ver
`sus time traces for the voltage regulator on a typical
`controller circuit and the voltage trace at the data out
`put terminals of a controller circuit mating with a com
`puter bus.
`FIG. 5 shows the electrical conductor tab arrange
`ment for an edge connector for a controller circuit
`employing the present invention and also shows sche
`matically the corresponding interconnection times.
`
`5,210,855
`3
`4
`provides both power and input/output data transfer,
`the SCSI compatible devices via the appropriate con
`without disrupting ongoing data transfers on an active
`trollers to either store or retrieve information from the
`storage device.
`bus is described as comprising in sequence: intercon
`necting the ground terminals for power and data input
`FIG. 1 will be recognized by those skilled in the art as
`/output transfer; interconnecting power to the control
`the ordinary interconnection of a generalized computer
`interface bus with appropriate peripheral storage de
`ler circuit; waiting a period of time for voltage on the
`vices and the environment in which the present inven
`controller circuit to stabilize and for the controller cir
`tion may be utilized. The problem presented is one of
`cuit to establish a stable high impedance state; and inter
`connecting'the data input/output terminals of the con
`providing a method and apparatus to enable the hot
`plugging of compatible interface or controller circuits
`troller circuit to the data bus.
`An apparatus for the rapid interconnection by means
`for computer peripheral devices to a generalized com
`of a multi-conductor connector for connecting a periph
`~ puter bus and more speci?cally to a SCSI bus.
`FIG. 2 shows a printed circuit board 28 supporting
`eral device controller circuit to a computer bus, which
`peripheral device controller logic circuits (not shown)
`bus provides both power and input/output data trans
`fer, without disrupting ongoing data transferson an
`having an edge connector portion 30 which comprises a
`series of parallel electrical conductors 32 and 34 which
`active bus is described as comprising: means for inter
`connecting the ground terminals for power and data
`may be mounted on either or both sides of the printed
`input/output; means for interconnecting power to the
`circuit board. The terms pc board and pc card with be
`used interchangeably. Adjacent to the edge connector
`controller circuit subsequent to the interconnection of
`the grounds; means for delaying for a predetermined
`portion 30 of the printed circuit card 28 is a correspond
`20
`ing or mating connector 36 coupling the individual
`time further interconnections until stabilization of volt
`age on the controller circuit and for the controller cir
`parallel electrical connectors 32 and 34 on the card to
`cuit to establish a stable high impedance state; and
`the appropriate interconnections 40 and 41 on the com
`means for interconnecting data input/output terminals
`puter data bus. FIG. 2 is an example of the interconnec
`of the controller circuit to the data bus after the prede
`tion of controller cards for many such computer bus
`termined time.
`devices and is clearly well known to those skilled in the
`art. The insertion of the card into the appropriate or
`mating connector slot 38 which is coupled to a com
`puter bus, e.g. a SCSI bus, causes the electrical inter
`connection of all of the controller logic circuit conduc
`tors on the printed circuit card with the SCSI bus.
`These normally include power, data and ground con
`nections for the controller circuit. It is thus‘ the pre
`ferred way of interconnecting controller cards for pe
`ripheral devices to computer buses.
`Unlike specially designed computer interface buses
`which permit the hot plugging of ?eld replaceable units,
`such as direct access storage devices and their appropri
`ate controller circuits, the SCSI bus permits the use of
`two types of TTL devices, which have substantially
`different electrical characteristics. Thus, it has been
`discovered that in an effort to provide a standardized
`interface bus, the SCSI bus includes provisions for types
`of transistor to transistor logic which would ordinarily
`prevent a hot plugging capability from being imple
`mented with the SCSI bus. In section 4.4. of the SCSI
`speci?cation, more than one type of TTL logic has been
`speci?ed for utilization with the SCSI interface bus. In
`an effort to understand the background for this prob
`lem, a review of the two types of transistor to transistor
`logic types, namely open collector and tri-state devices
`is included.
`In general, there are only two steady state output
`conditions on a TTL gate. The output low state is
`within a few tenths of a volt of ground and it is called a
`“positive logic 0”. In this state the output is capable of
`sinking a considerable current. The output high state is
`above 2.4 volts and it is called a “positive logic 1”. The
`output high state is well below the standard 5 volt posi
`tive supply of voltage. When a TTL gate is provided
`with an open collector output, it is referred to as open
`collector logic device. These gates may be connected to
`other open collector output gates to perform additional
`logic. Both FIGS. 3A and 3B, and the corresponding
`attributes and limitations of normal operation are well
`known to those skilled in the art. The two device types
`are presented here to show the'diversity of TTL logic
`circuits which may interface with a SCSI bus.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`FIG. 1 shows in block diagram form the interconnec
`tion of several peripheral devices via a SCSI bus to a
`single computer. In particular, a computer 10 with host
`adapter 11 is shown to be interconnected with a SCSI
`bus designated 12. Also, coupled to bus 12 is a magnetic
`disk controller 14 and a plurality of magnetic disk de
`vices generally designated as 16. In a similar manner,
`optical disk controller 18 and a plurality of optical disks
`19 are shown coupled to the bus along with magnetic
`tape controller 20 and a plurality of magnetic tape
`drives 21, printer controller 22 and a plurality of print
`ers 23, and other direct access storage device (DASD)
`controller 24 along with a plurality of DASD devices
`25. Each of the controller devices may have one or
`more storage devices coupled to them. In general, based
`upon a requirement of computer 10 during it’s normal
`course of operation under control by an application
`program, information and requests go on the bus 12 to
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`5,210,855
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`FIG. 3A shows four NAND gates designated 42, 44,
`46 and 48 having common outputs coupled together to
`a terminal labeled output and through a 2.2K resistor to
`a source of +5 volt. The TTL gates arranged in the
`manner shown form an open collector logic circuit. The
`system speed can suffer as inclusion of a pull-up resistor
`at the output does slow the output rise time. Such open
`collector devices tend‘to show a sensitivity to an input
`noise problem and because of the pull-up resistor cannot
`hope to be as fast as a device operating as an individual
`gate. In addition, with such a logic arrangement there is
`no easy way to ?nd a faulty part without removing or
`separating devices since the outputs are tied together.
`By contrast, FIG. 3B shows four AND gates desig
`nated 50, 52, 54, and 56 arranged in the manner shown
`to form a tri-state device. Each AND gate has two
`distinct input terminals and their outputs are all coupled
`together to a common output. In addition, each of the
`AND gates has a select or enable input terminal coupled
`to the device. Tri-state or three state logic has been
`20
`suggested to overcome some of the speed limitations of
`open collector devices,>but at a somewhat higher price.
`Operationally tri-state devices come up to output levels
`after power is applied many times faster than do open
`collector devices. The third state of tri-state logic is an
`open circuit. Any tri-state device has an output enable
`control which when activated causes the output to
`behave as an ordinary TTL gate, with either an active
`pull-up for logic one or a current sinking pull down for
`a logic 0. In the third state the internal circuitry is essen
`tially disconnected from the output which is then al
`lowed to assume a high impedance state, thus making
`the circuit essentially transparent to anything connected
`to the output.
`-
`Each peripheral device controller card is provided
`with suitable electronic logic circuits to interface the
`peripheral device with the computer bus and engage in
`transfers of data and other information. To insure
`proper voltage at the logic circuits the controller card
`contains a power regulator which interconnects with
`the power connections of the computer bus to provide
`regulated voltage for the logic on the card. The hot
`plugging of controller cards not only involves the speed
`with which the TTL logic devices become operational
`after the application of power, but also the normal volt
`age rise time for the card mounted regulator to assume
`a nominal voltage. By contrast, the rise time of the logic
`is a function of the type of TTL logic employed. In a
`similar manner, the time required to achieve a stable
`high impedance state would also be a function of an
`NMOS or CMOS circuit implementation for the pe
`ripheral device.
`'
`Hot plugging requires a non-interference with the
`active or ongoing data transfer that exists on the bus
`when a device is plugged in or unplugged. The design
`ers of a total data bus system can ensure that a particular
`bus will meet the design criteria by restricting the de
`vice controllers that are allowed on the bus such as by
`permitting only open collector type TTL devices. This
`is not possible on the SCSI bus and indeed the SCSI
`speci?cation allows different manufacturers of SCSI
`compatible devices to use different logic devices with
`different characteristic impedances. The hot plugging
`problem that has been observed is that false signal levels
`can be impressed on the bus especially during the pow
`er-on phase for TTL devices. This is the time when it
`was discovered that the controller circuit voltage is not
`fully regulated and the switching levels of the devices
`
`6
`are such that output lines may start to oscillate between
`high and low TTL levels until the voltage is stabilized.
`If these devices were connected to an active data bus,
`errors would be injected onto the bus.
`FIG. 4A shows the voltage versus time traces for a
`standard voltage regulator normally mounted on the
`device controller card. At time T0 the ground intercon
`nections are made. Upon power connection to the com
`puter bus the voltage regulator for the controller circuit
`comes into regulation in a well known manner. When
`the power is applied to the controller logic circuits at
`time T1 the voltage for the logic circuits begins to rise
`from a 0 voltage level. The trace shows four principal
`ordinate values, 0 volts, 0.7 volts, 2.5 volts, and 5 volts.
`Voltages at the output terminals of the logic circuits
`between 0 and 0.7 volts will be determined as a “logic
`0” and voltage levels at output terminals between 2.5
`and 5 volts will be determined to be a “logic 1”. The
`region between 0.7 volts and 2.5 volts is an unde?ned
`band gap region for which voltages will not be treated
`as either logic l’s or 0's. It is thus a logic indeterminate
`region. Continuing with the description of the trace, at
`time T1 when voltage is applied from the bus, the volt
`age output of the voltage regulator on the controller
`circuit begins to increase as a function of time. The trace
`shows the voltage output for the regulator on a control
`card continues to increase until approximately 0.015
`sec. from application of power from the bus, the regula
`tor has achieved its nominal 5 volts output preferably to
`within 10% of nominal value. This is a function of the
`electronics of the regulator which is standard and nor
`mally provided for either open collector or tri-state
`devices controller cards. If voltage from the on card
`regulator were supplied to the logic circuits at time T2
`the voltage would be more stabilized preferably to
`within 1% of its 5 v nominal value and the logic circuits
`would have achieved a stable high impedance state.
`FIG. 4B shows the voltage verses time trace for the
`output data lines of a tri-state controller logic circuit.
`The same four principal ordinate values of voltage are
`shown but now the band gap region from 0.7 v to 2.5
`volts is shown cross hatched for emphasis. At T1, when
`power is applied from the bus, the voltage regulator
`responds as shown in FIG. 4A and so do the tri-state
`output data lines as shown in FIG. 48. During the time
`interval from T1 to T1+0.0l5 sec. there is a ringing
`phenomenon observed especially for the tri-state output
`devices. This produces short term spurious signals on
`the bus which are variously in the “logic 0”, band gap
`and “logic 1” ranges. None of these impressed output
`values is valid and results only from the propagation of
`transients through the tri-state controller card logic
`circuits. Thus, during hot plugging, ongoing data trans
`fers on an active bus can be totally disrupted by the hot
`plug connection of a new tri-state implemented SCSI
`compatible device. Subsequent to time T1+0.0l5 sec.
`when the voltage output lines will have stabilized, in
`this case the levels are shown to be at logic 1 and there
`is a very small probability that disruptions would be
`caused on the bus. If the time to enable the activationv of
`data lines was delayed until T2, the point at which the
`voltage regulator was within 1% of its nominal value,
`then there would be no problem with the completion of
`the hot plugging.
`The normal method for hot plugging controller cards
`in a fault tolerant environment using TTL logic is to
`utilize the practice of increasing the length of the
`ground connectors so that when a controller card is
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`plugged in, ground connections are made first and then
`the base line of the ground conductors 60 and conduc
`all other connections to apply power to the regulator
`tors 64 are utilized for the controller data line intercon
`and activate the logic circuits. The circuit designer has
`nections and are positioned at a distance, L2 from the
`complete control over the design of the fault tolerant
`base line of ground conductors 60. The relative lengths
`computer bus being implemented and can select or
`are chosen so that for a reasonable insertion force, suffi
`reject logic devices accordingly. But with a standard
`cient time elapses between the interconnection of con
`ized bus, such as the SCSI bus, the designer is limited in
`ductors 62 and the subsequent interconnection of con
`which types of logic circuits for peripheral devices he
`Iductors 64, to eliminate all transients and establish a
`can select or reject. Assurance must also be provided so
`stable high impedance state.
`that the design does not interfere with ongoing bus
`As shown in FIG. 5 the ground conductors 60 inter
`operations during hot plugging.
`connect with the bus at time T0; the power conductors
`The ?rst attempt at a solution following normal fault
`62 at time T1 and the data line conductors at a time
`tolerant techniques, was to allow ground interconnec
`greater than T1. As for normal fault tolerant intercon
`tions to occur ?rst and to adjust and voltage/power
`nections the time between T1 and T0 is not critical but
`connections so that they occur simultaneously. How
`should be sufficient to assure all ground lines in the
`ever, this causes disruption in the power level on the bus
`logic circuits have reached the computer ground. For
`because of excessive loading and subsequently causes
`the TTL logic system, a minimum of 0.015 sec. has been
`data errors on the bus. Signal levels on the bus can be
`found to be acceptable for the difference between T1
`lowered to a point that other devices may be com
`and T2 but a time difference of 0.090 is preferred. The
`pletely disengaged from the bus, thus completely dis
`lengths for conductors 60, 62 and 64 are chosen to estab
`rupting data transfer and further causing start up rise
`lish interconnections at times T0, T1 and T2 respec
`time disruption when they try to come back on line.
`tively. In the preferred embodiment the lengths are L1:
`The second attempt at a solution was to adjust the
`1.78 mm (0.070 in) and L2: 2.54 mm (0.100 in) relative to
`data connections so that the ground and data intercon
`the ground conductors 60 base line.
`nections occur simultaneously. This causes excessive
`Thus, regardless of which of the allowable types of
`loading and disruption of the data transfer on the bus
`logic circuitry are used for the device interface control
`immediately. Applying power subsequently cannot re
`ler, the conductive contacts are arranged to permit the
`solve the problem since the damage has already been
`grounds to be connected ?rst then, power to voltage
`done.
`regulator on the controller card, and after a suitable
`The solution has been found to be sequentially con
`time for the settling of transients as shown in FIG. 4B,
`necting the grounds, power and data lines for controller
`the data input and output connection: to the SCSI bus
`cards exhibiting the delay of 0.015 sec. as indicated in
`are connected. In this way no transient signals from the
`the discussion for FIG. 4B. Thus as shown in FIGS. 4A
`electronic circuitry for the controller card will be im
`and 48, T0: would correspond to the ground intercon
`pressed on the data bus nor can there be an inordinate
`nection; T1: the application of voltage from the bus;
`electrical loading provided to the bus. This provides a
`T1+0.015 sec. would correspond to voltage regulation
`simple yet elegant solution to the problem of providing
`to within 10% of nominal value; T2: would correspond
`a hot plugging capability of devices which are compati
`to voltage regulation to within 1% of nominal value;
`ble with a SCSI bus. While the preferred embodiment
`and the interval T2-T1 would preferably be 0.090 sec.
`has shown the implementation for two types of TTL
`or approximately 6 times the 0.015 sec. interval. This is
`logic it will be clear to those skilled in the art that the
`most easily implemented electronically by placing logic
`invention may be used for other implementations in
`transmission gates or other suitable switches at all of the
`cluding differences in NMO and CMOS implemented
`control circuit data line connections and delaying the
`peripheral devices which also exhibit the phenomena of
`enabling of those transmission gates until the voltage
`having different times to come up to full voltage, and
`regulator has reached its steady state value and assumed
`the possibility of excessive loading on a bus and clear
`a high impedance level. A time delay device controlling
`transient signals during power on.
`the switches would have to work properly during the
`What is claimed is:
`entire power up operation, which could be to either the
`1. A data processing system comprising
`10% or 1% nominal values. However, considerable real
`a computer having an SCSI bus; '
`estate on the controller circuit board would be required
`a plurality of peripheral device controllers coupled to
`to implement this solution. It may also cause difficulty
`the computer by the bus, each controller including
`in identifying and isolating the fault source in fault toler
`control logic circuits and a voltage regulator for
`ant designs. A considerably simpler solution has been
`applying voltage to said logic circuits and having
`achieved by the careful utilization of the differential
`no delay, reset or degating circuits interposed be
`length connectors of the type used to implement normal
`tween the logic circuits and the bus, said logic
`hot plugging of peripheral devices with a fault tolerant
`circuits selected from a class of devices having
`bus.
`differing electrical characteristics but complying
`FIG. 5 shows the preferred embodiment for the pres
`with the requirements of a de?ned speci?cation for
`ent invention. It comprises an apparatus which in con
`said class;
`junction with a method for interconnecting SCSI com
`patible devices to allow for hot plugging in any envi
`said bus providing both power to and data transfer
`with the voltage regulator and logic circuits of
`ronment especially a fault tolerant one. The connector
`portion 30 of a PC controller card is shown with three
`each controller; and
`.
`sets of conductive strips having different lengths. Con
`apparatus for the hot plugging of each peripheral
`ductors 60 are utilized for the ground interconnections,
`device controller to the SCSI computer bus with
`and form the base line from which length measurements
`out disrupting data transfers on an active bus and
`are made. Conductors 62 are utilized for the power
`without the use of delay, reset or degating circuits
`in the controller, comprising:
`interconnections and are spaced at a distance L1 from
`
`50
`
`55
`
`65
`
`25
`
`35
`
`45
`
`

`
`5
`
`45
`
`edge connector means attached to the bus for inter
`connection of the bus with a corresponding recep
`tacle in a respective controller having parallel ar
`rangement of plural conductors, of three different
`lengths, for establishing predetermined sequential
`electrical interconnections with the applications of
`a reasonable insertion force;
`at least one longest length of conductor being cou
`pled to voltage regulator and logic circuit ground
`terminals of the respective controller for providing
`a ?rst electrical interconnection;
`at le