111111111111111111111111111111111111111111111111111111111111111111111111111
`US006157974A
`Patent Number:
`Date of Patent:
`
`[11]
`
`[45]
`
`6,157,974
`Dec. 5, 2000
`
`United States Patent
`Gasparik
`
`[19]
`
`[54] HOT PLUGGING SYSTEM WHICH
`PRECHARGING DATA SIGNAL PINS TO
`THE REFERENCE VOLTAGE THAT WAS
`GENERATED FROM VOLTAGE DETECTED
`ON THE OPERATING MODE SIGNAL
`CONDUCTOR IN THE BUS
`
`[75]
`
`Inventor: Frank Gasparik, Monument, Colo.
`
`[73]
`
`[21]
`
`[22]
`
`[51]
`[52]
`[58]
`
`[56]
`
`Assignee: LSI Logic Corporation, Milpitas,
`Calif.
`
`Appl. No.: 08/996,841
`
`Filed:
`
`Dec. 23, 1997
`
`Int. CI?
`U.S. Cl.
`Field of Search
`
`G06F 13/00
`710/103; 710/102
`712/1; 710/103,
`710/102
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5/1993 Bartol
`5,210,855
`5,268,592 12/1993 Bellany et al.
`5,432,916
`7/1995 Hahn et al.
`5,473,499
`12/1995 Weir
`5,515,515
`5/1996 Kennedy et al.
`5,530,810
`6/1996 Bowman
`5,568,610 10/1996 Brown
`5,572,395
`11/1996 Rasums et al.
`5,579,491
`11/1996 Jeffries et al.
`5,604,873
`2/1997 Fite et al.
`4/1997 Kimura
`5,625,593
`5,634,132
`5/1997 Pearce et al.
`5,668,770
`9/1997 Itoh et al.
`5,726,592
`3/1998 Schulte et al.
`5,784,576
`7/1998 Guthrie et al.
`
`395/500
`307/43
`710/103
`361/58
`395/283
`710/103
`714/48
`361/58
`395/283
`395/283
`365/189.05
`326/80
`365/227
`327/65
`710/103
`
`FOREIGN PATENT DOCUMENTS
`
`OTHER PUBLICATIONS
`
`XP 000586553-Author(s)-Filliter et al.
`
`Primary Examiner-Meng-Ai T. An
`Assistant Examiner-Macldy Monestime
`
`[57]
`
`ABSTRACT
`
`Data signal pins for a peripheral device are adaptively
`precharged during hot plugging to a voltage level depending
`on both the mode of operation (low voltage differential, high
`voltage differential, or single ended) and the actual signal
`voltages being employed for a particular mode. An active
`terminator bus provides an operating mode sensing signal,
`from which the operating mode of the bus and the actual
`signal voltage levels being employed may be determined.
`Signal pins on an edge connector for
`the device are
`connected, in sequence, to the corresponding ground, power
`supply, operating mode sensing signal, and data signal
`conductors of the bus. During the gap in time between
`connection of non-data signal pins (ground, power supply,
`and operating mode sensing pins) of the edge connector to
`the corresponding bus conductors and connection of the data
`signal pins while hot plugging, the precharge voltage level
`is generated on-board the peripheral device from the actual
`signal voltage levels being employed on the bus, and the
`data signal pins are precharged. The precharge voltage level
`is centered between the differential signal voltage levels for
`differential operating modes and centered between the hys(cid:173)
`teresis trip points for single ended operation modes. By
`precharging the parasitic capacitances of the data signal pins
`on the device to this voltage level, signal voltage levels on
`bus conductors are drawn toward this voltage level without
`changing the polarity of a differential signal or crossing a
`hysteresis trip point for a single ended signal.
`
`WO 99/24908
`
`5/1999 WIPO.
`
`27 Claims, 2 Drawing Sheets
`
`\2
`
`04
`
`204b
`
`208
`
`r- --- -,
`+
`-
`I
`I
`I
`I
`I
`I
`I
`I
`J
`
`L_r
`202
`I CORE LOGIC
`
`-
`
`UNIVERSAL
`TRANSCEIVER
`
`CORE LOGIC
`
`UNIVERSAL
`TRANSCEIVER
`
`DIFFSENS o-.,.-'W'.----,-------,---1
`
`HVD
`
`LVD
`
`SE
`
`

`
`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 1 of 2
`
`6,157,974
`
`10
`
`10
`
`116
`
`2, PROCESSOR
`I
`4, L2 CACHE
`I
`
`I
`SCSI BUS
`BRIDGE
`I
`
`12 -./
`
`I
`HARD
`..../ DISK
`FIG.
`
`~100
`
`GRAPHICS v- 11O
`ADAPTER
`I
`
`I
`SYSTEM
`MEMORY
`
`'"'--108
`
`106
`)
`
`114
`)
`
`::-
`
`208
`
`+ -
`
`CORE LOGIC
`
`UNIVERSAL
`TRANSCEIVER
`
`FIG. 2
`
`DISK
`DRIVE
`
`V 118a
`DISK
`,/ DRIVE
`118n
`
`000
`
`RAID
`DEVICE
`ill
`
`1
`
`204b
`
`1\
`
`"I
`I
`II
`
`\
`204
`
`2040
`
`::-
`
`208
`
`114/
`
`I
`I
`I
`I
`
`I
`I
`I
`I
`
`r- --- -,
`+
`-
`
`L_r - ___ J
`202
`I CORE LOGIC
`UNIVERSAL
`TRANSCEIVER
`
`REFERENCE
`(1.9 TO 2.2 V)
`
`D1FFSENS
`
`FIG. 2A
`
`REFERENCE
`(0.6 TO 0.7 V)
`
`HVD
`
`LVD
`
`SE
`
`

`
`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 2 of 2
`
`6,157,974
`
`L2
`
`L1
`
`FIG.
`
`(?
`
`----------------1----
`L3
`
`DDDDDDD~
`
`302
`
`v
`310
`
`'=v=:'
`308
`
`'=v=:'
`306
`
`'=v=:'
`304
`
`402
`J,
`
`III
`
`_...J
`
`r-
`I
`
`+
`
`VRE1 En ~I---_-_U-_-_-_U_-----I~ -
`
`- --i
`
`------ -.,I
`------ -.,
`-- -- -------------- -- -- -~
`PIN
`PIN
`PIN
`PIN
`PIN
`PIN
`PIN
`1b
`20
`2b
`260
`26b
`270
`27b
`
`I
`-~
`
`I
`
`000
`
`-=
`
`FIG.
`
`r -
`I
`406/-1L.._
`r(cid:173)
`404~
`L_
`PIN
`10
`
`4
`
`VREF - ----
`
`VREF -- ---
`
`VREF = +1.25V
`IVN - vAl ~ 400mV
`
`FIG. 5
`
`VREF = +1.25V
`IVN - vAl ~ 400mV
`
`FIG. 6
`(PRIOR ART)
`
`

`
`6,157,974
`
`1
`HOT PLUGGING SYSTEM WHICH
`PRECHARGING DATA SIGNAL PINS TO
`THE REFERENCE VOLTAGE THAT WAS
`GENERATED FROM VOLTAGE DETECTED
`ON THE OPERATING MODE SIGNAL
`CONDUCTOR IN THE BUS
`
`BACKGROUND OF THE INVENTION
`
`2
`instance, the actual reference voltage VREF around which the
`data signals VN and VA are centered may vary from 0.7 V to
`1.8 V, with the typical value being 1.25 V. The tolerance for
`the reference voltage VREF is thus more than twice the
`5 magnitude of the differential signal IVA'VAI ~ 400 mV. Any
`predefined precharge voltage having a constant or fixed
`value will not necessarily prevent changes in the differential
`signal which may being interpreted by a receiver as a data
`transition.
`Additionally, some devices are designed to selectively
`operate in more than one transmission mode. A single
`device, such as the Symbios Model 53C895 Universal
`Transceiver available from Symbios, Inc. of Fort Collins,
`Colo., may be configured to operate in either the LVD SCSI
`15 mode, the high voltage differential SCSI mode, or the single
`ended (SE) SCSI mode, depending on the transmission
`mode of the bus to which the device is connected. The
`different transmission modes employ different voltages and
`voltage ranges. For example, LVD SCSI employs a differ-
`20 ential signal centered on a reference signal somewhere in the
`range of 0.7 V to 1.8 V, as noted above, which SE SCSI
`employs a voltage swing of 0 V to 3.3 V.
`Even the single ended SCSI transmission mode is sensi(cid:173)
`tive to data signal fluctuations during hot-plugging. SE SCSI
`25 signals swing from V55 to VTERM' as defined by the external
`terminator and loaded bus. To improve noise immunity, the
`front-end of an SE SCSI receiver may be implemented in the
`form of a Schmitt Trigger with hysteresis centered around
`the TTL trip point of 1.4 V. Thus, for a typical hysteresis
`30 window of about ±150 mY, the trip point is 1.55 V for the
`positive signal transition and 1.25 V for the negative signal
`transition. Fluctuations of the data signal conductor voltages
`during hot-plugging may cross these trip points. The hys(cid:173)
`teresis may also be variable. Therefore, a fixed precharge
`35 voltage will not suffice to preserve data integrity.
`It would be desirable,
`therefore,
`to provide adaptable
`precharging of data signal pins based on actual operating
`voltages for preservation of data integrity. It would further
`40 be advantageous for the adaptable precharging to automati(cid:173)
`cally accommodate any of several selectable transmission
`modes.
`
`1. Technical Field
`The present invention relates generally to hot plugging of 10
`peripheral devices and in particular to hot plugging periph(cid:173)
`eral devices to a bus operating selectively in low voltage
`differential mode, high voltage differential mode, or single(cid:173)
`ended mode. Still more particularly, the present invention
`relates to preserving the integrity of data signals through
`adaptable precharging when hot plugging a peripheral
`device to a bus operating in a selectable transmission mode.
`2. Description of the Related Art
`Many modern data processing employ buses conforming
`to the small computer system interface (SCSI) standard to
`connect disk drives or redundant array of inexpensive disk
`(RAID) devices to a system bus. The replacement of periph(cid:173)
`eral devices, such as disk drives in personal computers or
`RAID boxes, connected to a SCSI bus during a data transfer
`on that bus is called "hot plugging." Since the device being
`connected to the bus is normally without power, external
`pins in the device represent discharged capacitors. At the
`instant when the pin comes in contact with a transmission
`line within the bus (a bus conductor), the pin capacitor will
`act as an ideal short to ground. This will disrupt the signal
`level at the instant of connection, which may cause an
`interruption of the data transfer.
`An example of the problem caused by hot plugging
`peripheral devices to a SCSI bus is depicted in FIG. 6. The
`example depicted relates to low voltage differential (LVD)
`transmission in a SCSI environment, in which a differential
`signal between a pair of cable wires carrying two signals VN
`and VA' centered around a reference voltage VREF of
`approximately 1.25 V, has a magnitude which is typically
`about 400 mVpp (millivolts, peak-to-peak). At a time t1 , a
`peripheral device pin makes contact with the cable connec-
`tor and pulls the signal level to ground. The differential
`signal VN-VA changes polarity, which may be interpreted by
`the receiver as an ordinary data transition, resulting in a data 45
`transfer error.
`The prior art typically addresses the problems associated
`with hot plugging after the fact, by re-transmission of data
`after the interruption. However, the standard SCSI connector
`SCA-2 provides a mechanical means, through pins of dif- 50
`ferent lengths, for connecting the ground and power supply
`bus conductors to the corresponding signal pins on the SCSI
`board or other peripheral device before the data signal
`conductors are connected to the corresponding data signal
`pins. This mechanism may be employed, as suggested in the 55
`prior art, to precharge the signal pins on a SCSI card during
`hot plugging. Typically, however, such precharging is con(cid:173)
`cerned with power surges during hot plugging and not with
`preserving data integrity. Therefore, most conventional pre(cid:173)
`charging schemes propose precharging the pins to a fixed,
`predefined voltage to limit current and power consumption
`during hot plugging.
`Precharging pins to a fixed, predefined voltage may limit
`current consumption during hot-plugging but does not nec(cid:173)
`essarily preserve data integrity since actual signal voltages 65
`during operation are not fixed and may vary across a wide
`range defined tolerances. In the case of LVD SCSI, for
`
`60
`
`SUMMARY OF THE INVENTION
`
`Data signal pins for a peripheral device are adaptively
`precharged during hot plugging to a voltage level depending
`on both the mode of operation (low voltage differential, high
`voltage differential, or single ended) and the actual signal
`voltages being employed for a particular mode of operation.
`An active terminator on the bus provides an operating mode
`sensing signal from which the operating mode of the bus
`may be determined. The operating mode sensing signal also
`provides an indication of the actual signal voltage levels
`being employed, from which the voltage level for precharg(cid:173)
`ing of data signal pins on the peripheral device may be
`generated. Signal pins on an edge connector for the device
`are connected, in sequence, to the corresponding ground,
`power supply, operating mode sensing signal, and data
`signal conductors of the bus. During the gap in time between
`connection of ground, power supply, and operating mode
`sensing pins of the edge connector to the corresponding bus
`conductors and connection of the data signal pins while hot
`plugging, the voltage level to be employed for precharging
`is generated on-board the peripheral device and the data
`signal pins are precharged. The precharge voltage level is
`centered between the differential signal voltage levels for
`differential operating modes and centered between the hys-
`
`

`
`6,157,974
`
`3
`teresis trip points for single ended operation modes. By
`precharging the parasitic capacitances of the data signal pins
`on the device to this voltage level, signal voltage levels on
`bus conductors are drawn toward this voltage level without
`changing the polarity of a differential signal or crossing a
`hysteresis trip point for a single ended signal. Data integrity
`is thus preserved during hot plugging.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The novel features believed characteristic of the invention
`are set forth in the appended claims. The invention itself,
`however, as well as a preferred mode of use, further objec(cid:173)
`tives and advantages thereof, will best be understood by
`reference to the following detailed description of an illus(cid:173)
`trative embodiment when read in conjunction with the
`accompanying drawings, wherein:
`FIG. 1 depicts a block diagram of a data processing
`system in which a preferred embodiment of the present
`invention may be implemented;
`FIG. 2 is a circuit diagram of a SCSI bus employing
`adaptive precharging in accordance with a preferred
`embodiment of the present invention;
`FIG. 3 depicts a pictorial representation of an edge
`connector for device which employs adaptive precharging of
`data signal pins during hot plugging in accordance with a
`preferred embodiment of the present invention;
`FIG. 4 is a circuit diagram for a circuit providing adaptive
`precharging of data signal pins on a SCSI bus connector in
`accordance with a preferred embodiment of the present
`invention;
`FIG. 5 is a timing diagram for hot plugging a device
`within a low voltage differential (LVD) SCSI bus employing
`adaptive precharging of data signal pins in accordance with
`a preferred embodiment of the present invention; and
`FIG. 6 is a timing diagram of hot plugging a device within
`an LVD SCSI bus without precharging.
`
`DETAILED DESCRIPTION
`With reference now to the figures, and in particular with
`reference to FIG. 1, a block diagram of a data processing
`system in which a preferred embodiment of the present
`invention may be implemented is depicted. Data processing
`system 100 includes a processor 102 connected to a level
`two (L2) cache 104, which is connected in turn to a system
`bus 106. Memory 108 in the depicted example is also
`connected to system bus 106, as is memory-mapped graph(cid:173)
`ics adapter 110, which is further connected to a display
`device (not shown).
`Also connected to system bus 106 is a SCSI bus bridge
`112 providing a connection between system bus 106 and
`SCSI bus 114. SCSI bus 112 is connected to hard disk drive
`116 and to RAID device 118 including a plurality of disk
`drives 118a-118n in accordance with the known art. The
`embodiment depicted in FIG. 1 is presented merely for the
`purposes of explaining the invention and is not intended to
`imply architectural limitations. Those skilled in the art will
`recognize that many variants of the embodiment depicted
`may be utilized in connection with the present invention.
`However, devices connected to SCSI bus 114 include a
`mechanism for adaptive precharging of data signal pins
`during hot plugging as described in greater detail below.
`Referring to FIG. 2, a circuit diagram of a SCSI bus
`employing adaptive precharging in accordance with a pre(cid:173)
`ferred embodiment of the present invention is illustrated.
`Driver 202 drives SCSI cable 204 to transmit signals to
`
`4
`receiver 206. SCSI cable 204 in the depicted embodiment
`includes two conductors 204a and 204b carrying comple(cid:173)
`mentary portions of the differential signal. SCSI cable 204
`is terminated with an active terminators 208, such as a
`5 Unitrode model UC5630 27-line SCSI Source/Sink Regu(cid:173)
`lator.
`Active terminator 208 provides an operating mode sens(cid:173)
`ing signal DIFFSENS (not shown) indicating the mode of
`operation. For LVD SCSI operation, the DIFFSENS voltage
`10 is from 0.7 V to 1.9 V; for HVD SCSI operation,
`the
`DIFFSENS voltage is from 2.4 V to VDD+0.3 V (greater
`than 2.4 V); and for SE SCSI operation, the DIFFSENS
`voltage is from Vss-0.3 V to 0.5 V (less than 0.5 V). The
`actual DIFFSENS voltage may vary within the defined
`15 ranges, depending on the actual operating voltages. The
`value of the actual DIFFSENS signal and the three voltage
`ranges defined for different modes of operation are
`employed during hot plugging of a peripheral device to
`recognize the SCSI mode of operation and to generate the
`20 data signal precharge voltage, as described below. A simple
`circuit for determining the operating mode of a SCSI bus
`during hot-plugging is shown in FIG. 2A.
`With reference now to FIG. 3, a pictorial representation of
`an edge connector for device which employs adaptive pre-
`25 charging of data signal pins during hot plugging in accor(cid:173)
`dance with a preferred embodiment of the present invention
`is illustrated. The edge connector 302 of a peripheral device
`supporting hot plugging includes a signal pins of varying
`lengths. The longest are ground pins 304, followed by power
`30 pins 306, DIFFSENS signal pins 308, and data signal pins
`310. This allows for sequential connection of grounds pins
`304, power pins 306, DIFFSENS signal pins 308, and data
`signal pins 310, in that order, during hot plugging. During
`the period of time between connection of non-data signal
`35 pins (including ground pins 304, power pins 306, and
`DIFFSENS signal pins 308) to the bus and connection of
`data signal pins 310 to the bus, data signal pins 310 are
`precharged as described in further detail below. DIFFSENS
`pins 308 are driven like power pins 306, with low impedance
`40 voltage source and capable of tolerating hot plugging of a
`0.1 ,uF filter capacitor, as compared to a maximum capaci(cid:173)
`tance of 20 pF for data signal pins 310.
`Referring to FIG. 4, a circuit diagram for a circuit
`45 providing adaptive precharging of data signal pins on a SCSI
`bus connector in accordance with a preferred embodiment of
`the present
`invention is depicted. A voltage VREF is
`provided, adaptively generated from the DIFFSENS voltage
`supplied by the active terminator. For LVD mode buses,
`50 V should be approximately 1.25 V. For SE mode buses,
`should be approximately 1.4 V. A multiplexer-type
`V
`d;~ce (not shown) may be employed to select a voltage
`source having the appropriate voltage level for the operating
`mode determined from the DIFFSENS voltage, with the
`55 DIFFSENS voltage level being employed to adjust
`the
`output voltage of the selected voltage source to the actual
`voltage level being employed.
`A plurality of MOS switches 402 connect voltage VREF to
`the data signal pins 404 of the peripheral device being
`60 connected to the bus. All pins on the peripheral device other
`than the ground, power supply, and DIFFSENS pins are
`connected to VREF by MOS switches 402. Resistors 406,
`having a resistance of approximately 1 KQ or an other
`suitable value for specific implementations, are connected
`65 between the MOS switches and the pin connections.
`Switches 402 are controlled by enable signal En, which
`may be derived from the power-on-reset signal of the
`
`REF
`
`

`
`6,157,974
`
`5
`peripheral device connected to the bus by hot plugging.
`Once asserted, enable signal En may be maintained in an
`asserted state for a predefined period corresponding to the
`time required to complete insertion. Alternatively, enable
`signal En may be deasserted as a result of detecting data 5
`signals from the bus through one or more of the data signal
`pins on the peripheral device, indicating that the peripheral
`device is completely connected to the bus.
`With reference now to FIG. 5, a timing diagram for hot
`plugging a device within an LVD SCSI bus employing 10
`adaptive precharging of data signal pins in accordance with
`a preferred embodiment of the present invention is illus(cid:173)
`trated. During hot plugging of a peripheral device,
`the
`connection of ground, power supply, and operating mode
`sensing pins of the device to the corresponding bus conduc- 15
`tors is employed to precharge the data signal pins. The
`power supply voltage is employed to generate a voltage
`level on-board the peripheral device equal
`to the actual
`reference voltage being employed by the bus. Each data
`signal pin is connected to this voltage level for a period of 20
`time needed to charge the parasitic capacitance associated
`with these data signal pins. For differential modes of
`operation, the data signal pins are precharged to a reference
`voltage VREF centered between the actual voltages being
`employed for differential signals VN and VA' For the single 25
`ended mode of operation, the data signal pins are precharged
`to the reference voltage VREF centered between the hyster(cid:173)
`esis trip points.
`As a result of precharging the data signal pins to the
`reference voltage, during hot plugging both the VN and VA 30
`signals on the data signal bus conductors will be pulled
`toward the reference voltage VREF at the time of connection
`of the data signal pins. The variations of VN and VA when
`precharged data signal pins are connected to corresponding
`bus conductors will be in opposite directions but similar 35
`magnitudes. The magnitudes of variations in VN and VA will
`be less than the full differential voltage range of the oper(cid:173)
`ating mode, preventing any receiving device from interpret(cid:173)
`ing the variations as a change in polarity or a data transition
`and preserving data integrity.
`Due to differences in device speeds, these variations in VN
`and VA may occur at different times t1 and t2 as depicted.
`However, even in the worst case where the variations occur
`at times t1 and t2 spaced far apart, a polarity change of the
`differential signal will not occur.
`The present invention provides adaptive precharging of
`data signal pins on a peripheral device during hot plugging
`depending both on the bus operating mode and the actual
`signal voltage levels being employed within the defined
`tolerances of a particular operating mode. An operating 50
`mode sensing signal provided by an active terminator on the
`bus is utilized to generate the voltage level to which the data
`signal pins are precharged.
`Signal pins on an edge connector for the peripheral device
`are connected, in sequence, to the corresponding ground, 55
`power supply, operating mode sensing signal, and data
`signal conductors of the bus. During the gap in time between
`connection of ground, power supply, and operating mode
`sensing pins of the edge connector to the corresponding bus
`conductors and connection of the data signal pins while hot 60
`plugging, the voltage level to be employed for precharging
`is generated on-board the peripheral device and the data
`signal pins are precharged for a period of time required to
`charge the associated parasitic capacitance. The precharge
`voltage is centered between the differential signal voltage 65
`levels for differential operating modes and centered between
`the hysteresis trip points for single ended operation modes.
`
`6
`By precharging the parasltlc capacitances of the data
`signal pins on the peripheral device to this voltage level
`during hot plugging, signal voltage levels on bus conductors
`are drawn toward this voltage level without changing the
`polarity of a differential signal or crossing a hysteresis trip
`point for a single ended signal. Such changes in polarity or
`crossing of hysteresis trip points may be mistakenly inter(cid:173)
`preted as ordinary data transitions by a receiving device,
`particularly for high speed buses. Thus, adaptive precharg(cid:173)
`ing in accordance with the present invention preserves data
`integrity during hot plugging.
`The description of the preferred embodiment of the
`present invention has been presented for purposes of illus(cid:173)
`tration and description, but is not intended to be exhaustive
`or limit the invention in the form disclosed. Many modifi(cid:173)
`cations and variations will be apparent to those of ordinary
`skill in the art. The embodiment was chosen and described
`in order to best explain the principles of the invention and
`the practical application to enable others of ordinary skill in
`the art to understand the invention for various embodiments
`with various modifications as are suited to the particular use
`contemplated.
`What is claimed is:
`1. A method of preserving data integrity while hot plug(cid:173)
`ging a peripheral device, comprising:
`connecting ground, power supply, and operating mode
`signal pins on the peripheral device to corresponding
`ground, power supply, and operating mode signal con(cid:173)
`ductors in a bus;
`generating a reference voltage from a voltage detected on
`the operating mode signal conductor in the bus; and
`precharging data signal pins on the peripheral device to
`the reference voltage before connecting the data signal
`pins to corresponding data signal conductors in the bus.
`2. The method of claim 1, wherein the step of connecting
`ground, power supply, and operating mode signal pins on the
`peripheral device to corresponding ground, power supply,
`and operating mode signal conductors in a bus further
`40 comprises:
`sequentially connecting the ground pin to the ground
`conductor, the power supply pin to the power supply
`conductor, and the operating mode signal pin to the
`operating mode signal conductor.
`3. The method of claim 1, wherein the step of precharging
`data signal pins on the peripheral device to the reference
`voltage before connecting the data signal pins to correspond(cid:173)
`ing data signal conductors in the bus further comprises:
`connecting the data signal pins on the peripheral device to
`the reference voltage for a period of time sufficient to
`charge a capacitance associated with the data signal
`pins; and
`connecting the charged data signal pins to the correspond(cid:173)
`ing data signal conductors in the bus.
`4. A method of preserving data integrity while hot plug(cid:173)
`ging a peripheral device, comprising:
`connecting ground, power supply, and operating mode
`signal pins on the peripheral device to corresponding
`ground, power supply and operating mode signal con(cid:173)
`ductors in a bus; and
`generating a reference voltage from a voltage detected on
`the operating mode signal conductor in the bus;
`precharging data signal pins on the peripheral device to
`the reference voltage before connecting the data signal
`pins to corresponding data signal conductors in the bus,
`wherein the step of generating a reference voltage from
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`a voltage detected on the operating mode signal con(cid:173)
`ductor in the bus further comprises:
`determining an operating mode of the bus from the
`voltage detected on the operating mode signal conduc(cid:173)
`tor; and
`selecting a voltage level corresponding to the detected
`operating mode for the reference voltage.
`5. The method of claim 4, wherein the step of generating
`a reference voltage from a voltage detected on the operating
`mode signal conductor in the bus further comprises:
`adjusting the selected voltage level to a level which is
`substantially equal an actual voltage level detected on
`a bus conductor.
`6. The method of claim 4, wherein the step of selecting a
`voltage level corresponding to the detected operating mode
`for the reference voltage further comprises:
`responsive to detecting a low voltage differential mode of
`operation on the bus, selecting a first voltage source
`having a first voltage output level;
`responsive to detecting a high voltage differential mode of 20
`operation on the bus, selecting a second voltage source
`having a second voltage output level different from the
`first voltage output level; and
`responsive to detecting a single ended mode of operation
`on the bus, selecting a third voltage source having a 25
`third voltage output level different from the first and
`second voltage output levels.
`7. A method of adaptively precharging signal pins for hot
`plugging a peripheral device without disrupting a data
`transfer on a bus, comprising:
`connecting ground and power supply pins on the periph(cid:173)
`eral device to corresponding ground and power supply
`bus conductors;
`generating a precharge voltage from an actual voltage 35
`detected on a bus conductor;
`connecting data signal pins on the peripheral device to the
`precharge voltage for a period of time sufficient to
`charge a capacitance associated with the data signal
`pins; and
`connecting the charged data signal pins to corresponding
`data signal conductors in the bus.
`8. The method of claim 7, wherein the precharge voltage
`is a voltage centered between signal voltages for a differ(cid:173)
`ential signal.
`9. The method of claim 7, wherein the precharge voltage
`is approximately 1.25 V.
`10. The method of claim 7, wherein the precharge voltage
`is a voltage centered between hysteresis trip points for a
`single ended signal.
`11. The method of claim 7, wherein the precharge voltage
`is approximately 1.4 V.
`12. An peripheral device suitable for hot plugging, com(cid:173)
`prising:
`an edge connector having a ground pin, a power supply 55
`pin, an operating mode signal pin, and at least one data
`signal pin, wherein the ground, power supply, and
`operating mode signal pins extend closer to an edge of
`the edge connector than the at least one data signal pin,
`wherein the ground, power supply, and operating mode 60
`signal pins contact corresponding ground, power
`supply, and operating mode signal conductors for a bus
`before the at
`least one data signal pin contacts a
`corresponding data signal conductor for the bus during
`insertion of the edge connector into a slot for the bus; 65
`a reference voltage generated from a voltage detected on
`the operating mode signal conductor for the bus; and
`
`8
`a precharge circuit connecting the at least one data signal
`pin on the peripheral device to the reference voltage
`before connecting the at least one data signal pin to the
`corresponding data signal conductor for the bus.
`13. The peripheral device of claim 12, wherein the ground
`pin extends closer to the edge of the edge connector than the
`power supply pin and the power supply pin extends closer to
`the edge of the edge connector than the operating mode
`signal pin, and wherein the ground, power supply and
`10 operating mode signal pins are sequentially connected to the
`corresponding ground, power supply, and operating mode
`signal conductors for the bus during insertion of the periph(cid:173)
`eral device into the slot for the bus.
`14. The peripheral device of claim 12, wherein the pre(cid:173)
`15 charge circuit further comprises:
`switches connecting the data signal pins on the peripheral
`device to the reference voltage for a period of time
`sufficient to charge a capacitance associated with the
`data signal pins.
`15. A peripheral device suitable for hot plugging com(cid:173)
`prising:
`an edge connector having a ground pin, a power supply
`pin, an operating mode signal pin, and at least one data
`signal pin, wherein the ground, power supply, and
`operating mode signal pins extend closer to an edge of
`the edge connector than the at least one data signal pin,
`wherein the ground, power supply, and operating mode
`signal conductors for a bus before the at least one data
`signal pin contacts a corresponding data signal conduc(cid:173)
`tor for the bus during insertion of the edge connector
`into a slot for the bus;
`a reference voltage generated from a voltage detected on
`the operating mode signal conductor for the bus; and
`a precharge circuit connecting the at least one data signal
`pin on the peripheral device to the reference voltage
`before connecting the at least one data signal pin to the
`corresponding data signal conductor
`for
`the bus,
`wherein the reference voltage is selected to correspond
`to an operating mode of the bus determined from a
`voltage detected on the operating mode signal conduc(cid:173)
`tor.
`16. The peripheral device of claim 15, wherein the ref(cid:173)
`erence voltage is substantially equal to an actual voltage
`45 detected on a bus conductor.
`17. The peripheral device of claim 15, wherein the ref(cid:173)
`erence voltage further comprises:
`a first voltage level selected if a low voltage differential
`mode of operation is detected on the bus;
`a second voltage level different from the first voltage level
`selected if a high voltage differential mode of operation
`is detected on the bus; and
`a third voltage level different from the first and second
`voltage levels selected if a single ended mode of
`operation is detected on the bus.
`18. An apparatus for adaptively precharging signal pins
`while hot plugging a peripheral device, comprising:
`means for connecting ground and power supply pins on
`the peripheral device to corresponding ground and
`power supply bus conductors;
`means for generating a precharge voltage from an actual
`voltage detected on a bus conductor;
`means for connecting data signal pins on the peripheral
`device to the precharge voltage for a period of time
`sufficient to charge a capacitance associated with the
`data signal pins; and
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`9
`means for connecting the charged data signal pins to
`corresponding data signal conductors in the bus.
`19. The apparatus of claim 18, wherein the precharge
`voltage is a voltage centered between signal voltages for a
`differential signal.
`20. The apparatus of claim 18, wherein the precharge
`voltage is appr