(12) United States Patent
`US 6,962,835 B2
`(10) Patent N0.:
`
`(45) Date of Patent: Nov. 8, 2005
`Tong et al.
`
`US006962835B2
`
`(54) METHOD FOR ROOM TEMPERATURE
`METAL DIRECT BONDING
`
`(75)
`
`Inventors: Qin-Yi Tong; Durham, NC (US); Paul
`M. Enquist; Cary; NC (US); Anthony
`Scot Rose, Cary; NC (US)
`
`(73) Assignee: Ziptronix, Inc.; Morrisville; NC (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 10/359,608
`
`(22)
`
`Filed:
`
`Feb. 7, 2003
`
`(65)
`
`Prior Publication Data
`
`US 2004/0157407 A1 Aug. 12, 2004
`
`(51)
`
`Int. Cl.7 ......................... H01L 21/44; H01L 21/48;
`H01L 21/50
`
`(52) US. Cl.
`
`....................... 438/108; 438/115; 438/118;
`438/666
`
`(58) Field of Search ................................. 438/108; 115;
`438/118; 666; 156/60; 257/753
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.................... 438/108
`4/1989 Rai et al.
`4,818,728 A *
`2/1990 Beecher et al.
`.
`.. 156/272.2
`4,904,328 A *
`
`10/1996 Ramm et al.
`.............. 438/15
`5,563,084 A
`
`
`6,322,600 B1 * 11/2001 Brewer et al.
`......
`51/308
`2002/0113241 A1 *
`8/2002 Kubota et al.
`................ 257/79
`
`OTHER PUBLICATIONS
`
`International Search Report, Mar. 1, 2005 (13 pages).
`T. Shimatsu et al. “Metal Bonding During Sputter Film
`Deposition”, J. Vac. Sci. Technol. A 16(4), 2125 (1998).
`E. Yablnovitch et al., Pd layer as a Bonding Layer on GaAs
`Wafers for Bonding GaAs/GaAs at 200° C, Appl. Phys. Lett.
`59, 3159 (1991).
`
`B. Aspar et al., “The Smart—Cut Process: Status and Devel-
`opments”, Proc. Electrochem. Soc. vol. 99—53, pp. 48
`(1999).
`A. Iida et al., “The Study of Initial Mechanism for Al—Au
`Solid Phase Diffusion Flip—Chip Bonding”, Jpn. J. Appl.
`Phys. 36, 3655 (1997).
`M. Hizukuri et al., “Flip—Chip Bonding of Au Pump (100
`um diameter) to 0.1 pm ThickAl Pad with the Aid of 60 kHz
`Ultrasonic Vibration and 100 gf/fump of Compressive
`Load”, Jpn. J. Appl. Phys. 40, 3044 (2001).
`Y.A. Li et al., “Low Temperature Copper to Copper Direct
`Bonding”, Jpn. J. Appl. Phys. 37, pp. L1068 (1998).
`A. Fan et al., “Copper Wafer Bonding”, Electrochem. and
`Solid—State Lett. 2, 534 (1999).
`CH. Tsau et al., “Fabrication Process and Plasticity of
`gold—Gold Thermocompression Bonds”, Mater. Soc. Symp.
`Proc. 605, 171 (1999).
`Y. Hayashi et al., VLSI Tech. Dig. 95 (1990).
`MA. Schmidt, Proc. IEEE, vol. 86, No. 8, 1575 (1998).
`
`(Continued)
`
`Primary Examiner—William Brewster
`(74) Attorney, Agent, or Firm—Oblon, Spivak, McClelland,
`Maier & Neustadt, PC.
`
`(57)
`
`ABSTRACT
`
`Abonded device structure including a first substrate having
`a first set of metallic bonding pads, preferably connected to
`a device or circuit, and having a first non-metallic region
`adjacent to the metallic bonding pads on the first substrate,
`a second substrate having a second set of metallic bonding
`pads aligned with the first set of metallic bonding pads,
`preferably connected to a device or circuit, and having a
`second non-metallic region adjacent to the metallic bonding
`pads on the second substrate, and a contact-bonded interface
`between the first and second set of metallic bonding pads
`formed by contact bonding of the first non-metallic region to
`the second non-metallic region. At least one of the first and
`second substrates may be elastically deformed.
`
`176 Claims, 9 Drawing Sheets
`
`17
`
`10
`
`13
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`WAFER 1 SUBSTRATE
`
`
`
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`WAFER 2 SUBSTRATE
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`Page 2
`
`OTHER PUBLICATIONS
`.
`nd
`.
`Intl. Symposmm 0n Semicon-
`T. Suga et al., Proc. The 2
`ductor Wafer Bonding, The Electrochemical Soc. Proc. VOl.
`93—29, p. 71 (1993).
`T. Shimatsu et al., IEEE Tran. Magnet. 33, 3495 (1997).
`
`U. Goesele et al., Proc. The 2nd Intl. Symposium on Semi-
`conductor Wafer Bonding, The Electrochemical Soc. Proc.
`VOl. 93_29, p. 395 (1993).
`“Handbook of Thin Film Technology”, Maissel and Glang,
`1983 Reissue, pp. 12—24.
`* cited by examiner
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`U.S. Patent
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`Nov. 8, 2005
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`Sheet 1 0f 9
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`US 6,962,835 B2
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`10
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`WAFER 1 SUBSTRATE
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`FIG. 7a
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`12
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`15
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`13
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`WAFER 1 SUBSTRATE
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`Sheet 2 0f 9
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`FIG. 2a
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`US 6,962,835 B2
`
`1
`METHOD FOR ROOM TEMPERATURE
`METAL DIRECT BONDING
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is related to application Ser. Nos. 09/410,
`054, 09/505,283 and 09/532,886,
`the entire contents of
`which are incorporated herein by reference.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to the field of direct wafer
`bonding, preferably at room temperature, and more particu-
`larly to the bonding of substrates to be utilized in semicon-
`ductor device and integrated circuit fabrication.
`2. Description of the Related Art
`As the physical limits of conventional CMOS device are
`being approached and the demands for high performance
`electronic systems are imminent, system-on-a chip (SOC) is
`becoming a natural solution of the semiconductor industry.
`For system-on-a chip preparation, a variety of functions are
`required on a chip. While silicon technology is the mainstay
`technology for processing a large number devices, many of
`the desired circuit and optoelectronic functions can now best
`be obtained from individual devices and/or circuits fabri-
`cated in materials other than silicon. Hence, hybrid systems
`which integrate non-silicon based devices with silicon based
`devices offer the potential to provide unique SOC functions
`not available from pure silicon or pure non-silicon devices
`alone.
`
`One method for heterogeneous device integration has
`been the hetero-epitaxial growth of dissimilar materials on
`silicon. To date, such hetero-epitaxial growth has realized a
`high density of defects in the hetero-epitaxial grown films,
`largely due to the mismatches in lattice constants between
`the non-silicon films and the substrate.
`
`Another approach to heterogeneous device integration has
`been wafer bonding technology. However, wafer bonding of
`dissimilar materials having different
`thermal expansion
`coefficients at elevated temperature introduces thermal
`stresses that lead to dislocation generation, debonding, or
`cracking. Thus, low temperature bonding is desired. Low
`temperature bonding is also crucial for the bonding of
`dissimilar materials if the dissimilar materials include mate-
`
`rials with low decomposition temperatures or temperature
`sensitive devices such as for example an InP heterojunction
`bipolar transistor or a processed Si device with ultrashallow
`source and drain profiles.
`The design of processes needed to produce different
`functions on the same chip containing different materials is
`difficult and hard to optimize. Indeed, many of the resultant
`SOC chips (especially those at larger integration size) show
`a low yield. One approach has been to interconnect fully
`processed ICs by wafer adhesive bonding and layer transfer.
`See for example Y. Hayashi, S. Wada, K. Kajiyana, K.
`Oyama, R. Koh, S Takahashi and T. Kunio, Symp. VLSI
`Tech. Dig. 95 (1990) and U.S. Pat. No. 5,563,084, the entire
`contents of both references are incorporated herein by
`reference. However, wafer adhesive bonding usually oper-
`ates at elevated temperatures and suffers from thermal stress,
`out-gassing, bubble formation and instability of the
`adhesive, leading to reduced yield in the process and poor
`reliability over time. Moreover, adhesive bond is usually not
`hermetic.
`
`Wafer direct bonding is a technology that allows wafers to
`be bonded at room temperature without using any adhesive.
`
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`The room temperature direct wafer bond is typically her-
`metic. It is not prone to introduce stress and inhomogeneity
`as in the adhesive bonding. Further, if the low temperature
`bonded wafer pairs can withstand a thinning process, when
`one wafer of a bonded pair is thinned to a thickness less than
`the respective critical value for the specific materials
`combination,
`the generation of misfit dislocations in the
`layer and sliding or cracking of the bonded pairs during
`subsequent thermal processing steps are avoided. See for
`example Q.-Y. Tong and U. Gosele, Semiconductor Wafer
`Bonding: Science and Technology, John Wiley & Sons, New
`York, (1999), the entire contents of which are incorporated
`herein by reference.
`Moreover, wafer direct bonding and layer transfer is a
`VLSI (Very Large Scale Integration) compatible, highly
`flexible and manufacturable technology, using that to form
`stacking three-dimensional system-on-a chip (3-D SOC) is
`highly preferable. The 3-D SOC approach can be seen as the
`integration of existing integrated circuits to form a system
`on a chip.
`Moreover, as the integration complexity grows, so do the
`demands on the integration process to robustly unify diverse
`circuits at low temperature, preferably at room temperature
`resulting in lower or non additional stress and more reliable
`circuits.
`
`Low or room temperature direct wafer bonding of metal
`between wafers or die being bonded is desirable for 3D-SOC
`preparation because this can be used in conjunction with
`direct wafer bonding of non-metal between wafers or die to
`result in electrical interconnection between wafers or die
`
`being bonded when they are mechanically bonded and thus
`eliminate the need to for post-bond processing, like substrate
`thinning, via etching, and interconnect metalization,
`to
`achieve an electrical
`interconnection between bonded
`
`wafers or die. Very small bonding metal pads can be used
`resulting in very low parasitics and resulting reduced power
`and increased bandwidth capability.
`Bonding of metals with clean surfaces is well-known
`phenomenon. For example, thermocompression wire bond-
`ing has been applied to wafer-level bonding. Temperature,
`pressure and low hardness metals are typically employed
`and usually results in residual stresses. For example, see
`example, M. A. Schmidt, Proc. IEEE, Vol. 86, No. 8, 1575
`(1998), Y. Li, R. W. Bower, I. Bencuya, Jpn. J. Appl. Phys.
`Vol. 37, L1068 (1988). Direct bonding of Pd metal layer
`covered silicon or III V compound wafers at 250—350° C.
`has been reported by B. Aspar, E. Jalaguier, A. Mas, C.
`Locatelli, O. Rayssac, H. Moricean, S. Pocas, A. Papon, J.
`Michasud and M. Bruel, Electon. Lett., 35, 12 (1999).
`However, actually Pd2Si silicide or Pd-III V alloys, not
`metal Pd, are formed and bonded. Bonding of Au and A1 at
`room temperature has been achieved by using ultrasonic and
`compressive load at flip chip bonding, see example, M.
`Hizukuri, N. Watanabe and T. Asano, Jpn. J. Appl. Phys. Vol.
`40, 3044 (2001). Room temperature metal bonding at wafer
`level has been realized in ultrahigh vacuum (UHV) systems
`with a base pressure lower than 3><10'8 mbar. Usually an ion
`argon sputtering or fast atom-beam is used to clean the
`bonding surfaces followed by application of an external
`pressure to the bonding substrates. See for example, T. Suga,
`Proc. The 2nd Intl. Symposium on semiconductor wafer
`bonding, the Electrochemical Soc. Proc. Vol. 93—29, p.71
`(1993). Room temperature bonding between two Si sub-
`strates with thin sputtered Ti, Pt and Au films has also been
`accomplished using applied force after thin film sputter
`deposition at 4—40 nbar of Ar pressure in a UHV system with
`base pressure less than 3><10'8 mbar. See for example, T.
`
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`3
`Shimatsu, R. H. Mollema, D. Monsma, E. G. Keim and J. C.
`Lodder, J. Vac. Sci. Technol. A 16(4), 2125 (1998).
`SUMMARY OF THE INVENTION
`
`invention is thus to obtain
`An object of the present
`mechanical and electrical contact between wafers and die
`with a single bonding step
`Another object of the present invention is to provide a low
`or room temperature bonding method by which metallic
`bonding between wafers or die of semiconductor circuits can
`be formed in ambient without using external pressure.
`An additional object of the present invention is to provide
`a low or room temperature bonding method by which
`metallic bonding of layers of any metal between wafers or
`die of semiconductor circuits can be formed at room tem-
`perature at wafer level in ambient without using external
`pressure by covering metal layers with a thin film of gold or
`copper or palladium.
`Still another object of the present invention is to provide
`a room temperature bonding method at wafer level
`in
`ambient without using external pressure by which metallic
`as well as covalent bonds are formed simultaneously at room
`temperature on bonding surfaces of wafers or die comprised
`of semiconductor circuits where metal and other non-metal
`layers co-exist.
`Another object is to provide a room temperature bonding
`method by which different substrates or different materials
`on different substrates with different
`thermal expansion
`coefficients can be bonded together without generation of
`catastrophic stresses between the different substrates or
`different materials on different substrates.
`
`Still another object of the present invention is a room
`temperature bonding method by which the bond strength
`between substrates approaches the mechanical fracture
`strength of the substrates.
`Another object of the present invention is to provide a
`bonded device structure including devices fabricated indi-
`vidually on separate substrates and bonded on a common
`substrate.
`
`A still further object of the present invention is to provide
`a method and device whereby a reliable mechanical bond
`can be formed at or near room temperature and a reliable
`electrical contact can be subsequently formed with a simple
`low temperature anneal.
`invention are
`These and other objects of the present
`achieved by a bonded method and device structure including
`a first substrate having a first plurality of metallic bonding
`pads, preferably connected to a device or circuit, and having
`a first non-metallic region adjacent to the metallic bonding
`pads on the first substrate, a second substrate having a
`second plurality of metallic bonding pads, preferably con-
`nected to a second device or circuit, aligned or alignable
`with the first plurality of metallic bonding pads and having
`a second non-metallic region adjacent to the metallic bond-
`ing pads on the second substrate, and a contact-bonded
`interface between the first and second set of metallic bond-
`
`ing pads formed by either elastic deformation of elements
`within the first substrate and the second substrate that is a
`
`direct result of forces generated by direct wafer bonding of
`the first non-metallic region to the second non-metallic
`region, or by refiow of metal in the vicinity of the first and
`second sets of metallic bonding pads after direct wafer
`bonding of the first non-metallic region to the second
`non-metallic region.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`4
`obtained as the same becomes better understood by refer-
`ence to the following detailed description when considered
`in connection with the accompanying drawings, wherein:
`FIG. 1A is a schematic depiction of a pair of unbonded
`substrates having aligned metal bonding pads;
`FIG. 1B is a schematic depiction of a pair of unbonded
`substrates having the aligned metal bonding pads contacted;
`FIG. 1C is a schematic depiction of a pair of contacted
`substrates, according to the present invention, bonded in a
`non-metal region away from the metal bonding pads;
`FIG. 1D is a schematic depiction of a pair of contacted
`substrates, according to the present invention, bonded across
`the non-metal regions except for a small unbonded ring area
`near the metal bonding pads;
`FIGS. 2A—2C are schematic diagrams illustrating bonding
`substrates with multiple bonding pads;
`invention
`FIG. 2D is graph, according to the present
`showing the width of an unbonded ring area W as a function
`of the metal pad thickness 2 h separating the semiconductor
`dies as shown in the insert;
`FIG. 3A is a schematic depiction of semiconductor die or
`wafer after surface planarization;
`FIG. 3B is a schematic depiction of semiconductor die or
`wafer in which second metal layer are formed and pla-
`narized with contact windows opened on metal pads;
`FIG. 3C is a schematic depiction of second semiconductor
`die or wafer with a second metal layer.
`FIG. 3D is a schematic depiction of an aligned metal
`bonding of two dies or wafers, according to the present
`invention;
`FIG. 4A is a schematic depiction of a part of a substrate
`showing imbedded metal pads in an oxide coating;
`FIG. 4B is a schematic depiction of a pair of unbonded
`substrates, according to the present invention, having recip-
`rocal metal bonding pads;
`FIG. 4C is a schematic depiction of a pair of bonded
`substrates, according to the present invention, showing the
`reciprocal metal bonding pads contacted by the forces
`generated when the non-metal regions contacted and
`bonded;
`FIG. 4D is a schematic depiction of a pair of smaller
`substrates bonded to a larger substrate;
`FIG. 5A is a schematic diagram of an embodiment of the
`invention having a deformable material or void beneath the
`metal pad;
`FIG. 5B is a schematic diagram of an embodiment of the
`invention having a deformable material beneath the metal
`pad;
`FIG. 5C is a schematic diagram of two devices as shown
`in FIG. 5A bonded together.
`FIG. 6A is a schematic diagram of an embodiment of the
`invention having refiowable metal material exposed to the
`surface on two devices prior to direct wafer bonding of the
`non-metal surfaces.
`
`FIG. 6B is a schematic diagram of an embodiment of the
`invention having refiowable metal material sealed by after
`direct wafer bonding of the non-metal surfaces.
`FIG. 6C is a schematic diagram of an embodiment of the
`invention having refiowable metal refiowed after direct
`wafer bonding of non-metal surfaces sealed the refiowable
`metal.
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`A more complete appreciation of the present invention
`and many attendant advantages thereof will be readily
`
`FIG. 7A is a schematic diagram of an embodiment of the
`invention having refiowable metal material exposed to the
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`TSMC1009
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`IPR of U.S. Pat. No. 7,485,968
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`TSMC1009
`IPR of U.S. Pat. No. 7,485,968
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`

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`US 6,962,835 B2
`
`5
`surface on two devices prior to direct wafer bonding of the
`non-metal surfaces.
`
`FIG. 7B is a schematic diagram of an embodiment of the
`invention having refiowable metal material sealed by after
`direct wafer bonding of the non-metal surfaces.
`FIG. 7C is a schematic diagram of an embodiment of the
`invention having refiowable metal refiowed after direct
`wafer bonding of non-metal surfaces sealed the refiowable
`metal.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`Referring now to the drawings, wherein like reference
`numerals designate like or corresponding parts throughout
`the several views, and more particularly to FIGS. 1A—1D
`and 2 illustrating a first embodiment of the bonding process
`of the present invention. In the first embodiment of the
`present invention, direct metal-metal bonding is generated
`when metal contact regions on separate wafers upon align-
`ment are contact pressure bonded by the intrinsic forces
`generated when non-metallic regions peripheral
`to the
`metallic regions undergo room-temperature chemical bond-
`ing. Chemical bonding as used throughout this specification
`is defined as a bond strength developed when surface bonds
`on the surface of one wafer react with the surface bonds on
`
`the surface of an opposing wafer to form direct bonds across
`the surface elements, such as a covalent bond. Chemical
`bonds are manifest by their high bond strengths, approach-
`ing for instance the fracture strength of the wafer materials,
`and thus are differentiated for example from mere Van der
`Waals bonding. Examples of chemical bond strengths
`achieved by the methods of the present invention are dis-
`cussed below. In the chemical bonding process, substantial
`forces are developed. These forces can be sufficiently great
`to elastically deform the metallic regions as the chemical
`bond propagates between the opposed non-metallic regions.
`FIG. 1A shows two wafers 10, 13 with respective oppos-
`ing wafer surfaces 11, 14. The wafer surfaces may be pure
`elemental semiconductor surfaces, may be pure elemental
`semiconductor surfaces including a relatively small amount
`of native oxide, or may be an insulator such as oxide-coated
`surface. The surfaces may be prepared as described in
`application Ser. Nos. 09/410,054, 09/505,283 and 09/532,
`886,
`to produce a smooth, activated surface. Techniques
`such as polishing or polishing and very slightly etching
`(VSE) may be used. A bonding layer may be deposited and
`polished or polished and slightly etched. The resulting
`surfaces are complementary and have chemical bonding
`surfaces that are planar and smooth, havingchemical bond-
`ing surface roughness1n the range of 5—15 A, preferably no
`more than 10 A, and more preferably no more than 5 A.
`Each wafer includes a set of metallic pads 12, 15 and a
`non-metallic region adjacent to the metallic bonding pads in
`the surfaces 11, 14. The non-planarity and surface roughness
`of the metallic bonding pads may be larger than that of the
`chemical bonding surfaces. Pads 12, 15 may be used to route
`electrical connections to the respective devices and/or cir-
`cuits pre-fabricated on the wafers. The pads are preferably
`formed before surface treatment, and VSE is preferably
`performed after the pads are formed. As shown in FIG. 1A,
`pads 12, 15 are on the respective wafers are aligned. FIG. 1B
`shows the wafers upon placing the wafers together to contact
`the respective pads. At this stage, pads 12, 15 would be
`separable. In FIG. 1C, slight additional pressure is applied to
`the wafers to elastically deform one or both of the semicon-
`ductor wafers, resulting in contact between some of the
`
`6
`non-metal areas on the wafers. The location shown of the
`contacting is an example, and the contact may occur at
`different locations. Also, the contact may occur at more than
`one point. This contact initiates chemical wafer-to-wafer
`bonding, and the bonded structure is shown in FIG. 1D. The
`bonding seam 16 expands after the initial chemical bonding
`to produce bonding seam 17 shown in FIG. 1D. The bond
`strength is initially weak and increases as the bonding
`propagates, as explained in Ser. Nos. 09/410,054, 09/505,
`283 and 09/532,886. The opposing non-metallic regions are
`chemically bonded at room or low temperature.
`In more detail, as the wafer surfaces including the metal
`bonding pads contact at room temperature, the contacting
`non-metal parts of opposing wafer surfaces began to form a
`bond at
`the contact point or points, and the attractive
`bonding force between the wafers increases as the contact
`chemical bonding area increases. Without the presence of
`the metal pads,
`the wafers would bond across the entire
`wafer surface. According to the present invention, the pres-
`ence of the metal pads, while interrupting the bonding seam
`between the opposing wafers, does not prohibit chemical
`wafer to wafer bonding. Due to the malleability and ductility
`of the metal bonding pads, the pressure generated by the
`chemical wafer-to-wafer bonding in the non-metal regions
`may results in a force by which nonplanar and/or rough
`regions on the metal pads may be deformed resulting in
`improved planarity and/or roughness of the metal pads and
`intimate contact between the metal pads. The pressure
`generated by the chemical bonding is sufficient to obviate
`the need for external pressure to be applied in order for these
`metal pads to be intimately contacted to each other. A strong
`metallic bond can be formed between the intimately con-
`tacted metal pads, even at room temperature, due to inter-
`diffusion or self-diffusion of metal atoms at
`the mating
`interface. This diffusion is thermodynamically driven to
`reduce the surface free energy and is enhanced for metals
`that typically have high inter-diffusion and/or self-diffusion
`coefficients. These high diffusion coefficients are a result of
`a cohesive energy that is typically mostly determined by the
`mobile free electron gas that is not disturbed by the motion
`of metal ions during the diffusion The wafer-to-wafer chemi-
`cal bonding in the non-metal regions thus effects electrical
`connection between metal pads on the two different wafers.
`The geometrical and mechanical constraints governing this
`effect are described below.
`
`An unbonded area around the bonding pad having a width
`W will be generated in which the non-metal surfaces of the
`two wafers are precluded from contacting (see FIG. 1D). As
`long as the thickness of metal films is not too large, the gaps
`between two bonding wafers or dies can be reduced leaving
`a small unbonded area around each metal pad. This is
`illustrated in FIGS. 2A—2C, where wafer 20 with metal pads
`21 is ready to be bonded to wafer 22 with pads 23. A gap 24
`is between adjacent pads. The metal pads are contacted
`(FIG. 2B) and the wafers elastically deform to bond in the
`gaps 24 to form bonds 25 (FIG. 2C). It is noted that the
`dimensions in FIGS. 2A—2C are not to scale.
`The formula to calculate the width of the unbonded area
`
`as a function of metal film thickness, mechanical properties
`of the wafer or die, the wafer or die thickness, the bonding
`energy will be shown below. FIG. 2D is a graph showing the
`relationship between the gap height 2h and the width w of
`an unbonded area. When the deformation of the wafers
`
`obeys an elastic constant given by Young’s modulus E and
`the wafers each have a thickness of tw, according to the
`simple theory of small deflection of a thin plate, the width
`W of the unbonded area can be roughly estimated by the
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`IPR of U.S. Pat. No. 7,485,968
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`TSMC1009
`IPR of U.S. Pat. No. 7,485,968
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`US 6,962,835 B2
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`7
`following equation for W>2tw, where the metal bonding
`pads as a pair have a height of 2h above the wafer surface:
`
`W=[(ZE’lw°)/(3‘{)ll/4hl/2
`
`(1)
`
`where E' is given by E/(1—v2) with v being Poisson’s ratio.
`It has been suggested that with decreasing h, the situation
`changes drastically. See for example, U. Goesele and Q.-Y.
`Tong, Proc. The 2nd Intl. Symposium on semiconductor
`wafer bonding, the Electrochemical Soc. Proc. Vol. 93—29,
`p. 395 (1993). If W calculated by Eq. (1) leads to values
`below Wm-t=2tw, corresponding to h<hm-t where herit=5(twv/
`E')1/2, then an elastomechanical instability is supposed to
`occur, leading to an unbonded area with much smaller W
`that is independent of wafer thickness tw, and is given by:
`
`W~kh
`
`(2)
`
`where k is a dimensionless constant on the order of 1.
`
`Experimentally, as shown in FIG. 2D if h<300 A, W is much
`smaller than what is predicted by Eq. (1). Further work by
`the inventors of the present application has shown that, if the
`spacing between metal bonding pad pairs 2R is smaller than
`2W, the wafer pairs may not bond to each other. However,
`when 2R>2W, surfaces between the two unbonded areas
`around the metal posts will bond and the metal posts will be
`bonded and electrically connected.
`The pressure P on the metal bonding pairs that is gener-
`ated by the bonding of the surrounding area can be expressed
`as:
`
`P=(16 E’zW3h)/(3W4)
`
`(3)
`
`Combining Eq.(3) with Eq.(1) or (2), when W>2 tw, the
`following is obtained:
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`P=8y/3h,
`
`and when W<2 tw, the following is obtained:
`
`P=(1 6 E’tW3)/(3k4h3)
`
`(4)
`
`(5)
`
`40
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`For bonded silicon wafers where the metal pads have
`height h of 500 A and the bonding energy is 300 mJ/m2, the
`compressive pressure on the metal bonding pads is about
`1.6><108 dynes/cm2, i.e. 160 atmospheres. Since this pres-
`sure is sufficiently high for metal bonding, there is no need
`to apply any external pressure during bonding. When metal
`height h1s 300 A or less, W<2tw is satisfied and the pressure
`on the metal pairs is in the order of 5000 atmospheres if k= 1
`is assumed.
`
`In one example of the first embodiment of the present
`invention, 5 mm diameter Au bonding pads with a thickness
`less than 300 A and a separation distance of 1 mm were
`deposited on oxide covered 100 mm silicon wafers. Since
`the Au bonding pads were formed on the surface of the
`oxide, they also had a height of 300 Angstroms above the
`surface of the oxide. However, h can be much smaller than
`actual metal thickness since metal cam be partially buried in
`oxide or other insulator and h is the height
`the metal
`extended above the die surface. Aroom temperature bonding
`technology has been developed that cleans and activates the
`metal and the oxide surfaces compatibly and simultaneously.
`The Au posts formed a metallic bond by room temperature
`bonding at wafer level in ambient without using external
`pressure after storage in air for a period of time, e.g. 60 hr
`depending on the metal thickness and bonding energy. When
`the wafer pairs were forcibly separated, by inserting a wedge
`between the bonded interface, either the Au or the Au/oxide
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`layer peeled from the silicon substrate, indicating that the
`metal-to-metal bond formed was stronger than the adhesion
`of the Au pad on the oxide surface or the oxide on the silicon
`surface. As mentioned above, a strong metallic bond can be
`formed between the intimately contacted metal pads at room
`temperature due to inter-diffusion or self-diffusion of metal
`atoms on the mating interface to reduce the surface free
`energy. The inter-diffusion or self-diffusion coefficient
`between metal atoms increases exponentially with
`temperature, in order to shorten the storage time to achieve
`full metallic bonding, annealing can be performed after
`room temperature bonding. The preferred annealing time for
`metallic bonding between the Au posts shortened as the
`temperature increased. For this case, 5 hr was preferred for
`100° C., 1 hr for 150° C., and 5 min for 250° C. Thinner
`metals require lower temperatures for bonding than thicker
`metals due to higher pressure generated by the bonding of
`non-metal surrounding areas. The time for the formation of
`metallic bond at room temperature and at elevated tempera-
`tures becomes longer as the Au thickness (i.e., height)
`increases. For example, when the thickness of Au pads h1s
`600 A, 5 min at 250° C. is needed to form metallic bond
`while at h=500 A, 15 min is required
`In flip-chip bonding of state-of-the art integrated circuits,
`the solder ball