(12) Unlted States Patent
`(10) Patent N0.:
`US 6,902,987 B1
`
`Tong et al.
`(45) Date of Patent:
`Jun. 7, 2005
`
`U5006902987B1
`
`(54) METHOD FOR LOW TEMPERATURE
`BONDING AND BONDED STRUCTURE
`
`JP
`W0
`W0
`
`03101128 A
`W0 9613060 A
`W0 9845130 A
`
`4/1991
`5/1996
`10/1998
`
`(75)
`
`Inventors: Qin-Yi Tong, Durham, NC (US); Gaius
`Gillman Fountain, Jr., Youngsville,
`gjcstS); Paul M. Enqulst, Cary, NC
`
`(73) Assignee: ZiPtI‘OIliX, Inc” Research Triangle Park,
`NC (US)
`
`*
`
`)
`
`(
`
`.
`NOTICE:
`
`.
`.
`.
`.
`Subject to any disclaimer, the term 0f thls
`patent is extended or adjusted under 35
`U’S'C' 154(b) by 0 days.
`
`(21) Appl. No.: 09/505,283
`
`(22)
`
`Filed:
`
`Feb. 16, 2000
`
`Int. Cl.7 ................................................ H01L 21/48
`(51)
`(52) U.S. Cl.
`....................... 438/455; 438/459; 438/974;
`148/DIG. 12
`
`(58) Field of Search ................................. 438/455, 459,
`438/406, 974; 148/DIG. 12
`
`(56)
`
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`
`Primary Examiner—George Fourson
`Assistant Examiner—Joannie Adelle Garcia
`(74) Attorney, Agent, or Firm—Oblon, Spivak, McClelland,
`Maier & Neustadt, P.C.
`
`(57)
`
`ABSTRACT
`
`A method for bonding at low or room temperature includes
`steps of surface cleaning and activation by cleaning or
`etching. One etching process the method may also include
`removing by-products of interface polymerization to prevent
`a reverse polymerization reaction to allow room temperature
`chemical bonding of materials such as silicon, silicon nitride
`and SiOz. The surfaces to be bonded are polished to a high
`degree of smoothness and planarity. VSE may use reactive
`ion etching or wet etching to slightly etch the surfaces being
`bonded. The surface roughness and planarity are not
`degraded and may be enhanced by the VSE process. The
`etched surfaces may be rinsed in solutions such as ammo-
`nium hydroxide or ammonium fluoride to promote the
`formation of desired bondin s ecies on the surfaces
`g p
`‘
`
`147 Claims, 9 Drawing Sheets
`
`55
`
`~51.
`”bl
`”Bo
`
`r19 “51
`
`
`
`
`
`31‘31"
`
`TSMC1008
`
`IPR of U.S. Pat. No. 7,485,968
`
`TSMC1008
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`US 6,902,987 B1
`
`Page 2
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`

`

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`
`TSMC1008
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`US 6,902,987 B1
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`Page 5
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`* cited by examiner
`
`TSMC1008
`
`IPR of U.S. Pat. No. 7,485,968
`
`TSMC1008
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`U.S. Patent
`
`Jun. 7, 2005
`
`Sheet 1 0f 9
`
`US 6,902,987 B1
`
`FORM BONDING LAYER
`
`ON WAFER 0R MATERIAL ’b 1
`
`SMOOTH AND PLANARIZE
`BONDING LAYER
`
`N2
`
`SLIGHTLY ETCH BONDING
`LAYER TO ACTIVATE
`
`SURFACE
`
`
`TERMINATE BONDING a, 4
`
`
`BOND SURFACES
`
`TOGETHER
`
`FIG. 1
`
`TSMC1008
`
`IPR of U.S. Pat. No. 7,485,968
`
`TSMC1008
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`U.S. Patent
`
`Jun. 7, 2005
`
`Sheet 2 0f 9
`
`US 6,902,987 B1
`
`FORM PECVD OXIDE
`
`LAYER ON WAFER
`
`OXIDE LAYER
`
`SMOOTH AND PLANARIZE
`
`EXPOSE OXIDE TO VSE
`PLASMA RIB PROCESS
`
`~12
`
`IMMERSE WAFER IN
`
`SOLUTION
`
`ANOTHER LAYER
`
`BOND OXIDE TO
`
`FIG. 2
`
`TSMC1008
`
`IPR of U.S. Pat. No. 7,485,968
`
`TSMC1008
`IPR of U