(12) United States Patent
`(10) Patent N0.:
`US 6,867,073 B1
`
`Enquist
`(45) Date of Patent:
`Mar. 15, 2005
`
`USOO6867073B1
`
`(54) SINGLE MASK VIA METHOD AND DEVICE
`
`2002/0094661 A1 *
`2003/0109083 A1 *
`
`.............. 438/455
`7/2002 Enquist et a1.
`6/2003 Ahmad ....................... 438/125
`
`(75)
`
`Inventor; Paul M, Enquist, Cary, NC (US)
`
`2003/0129796 A1 *
`
`7/2003 Bruchhaus et al.
`
`......... 438/239
`
`(73) Assignee: Ziptronix, Inc., Morrisville, NC (US)
`
`* cited by examiner
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154a,) by 0 days.
`
`Prinmry Examiner—Matthew Smith
`Asszstant Exammer—Vlctor V YeVSIkov
`(74) Attorney, Agent, or Firm—Oblon, Spivak, McClelland,
`Maier & Neustadt, PC.
`
`(21) Appl. No.: 10/688,910
`
`(57)
`
`ABSTRACT
`
`OCt- 21: 2003
`Filed:
`(22)
`Int. Cl.7 ................................................ H01L 21/44
`(51)
`(52) U S C]
`438/125, 438/106' 438/455,
`'
`' 438/456438/459 438/618? 438/620? 438/637?
`’
`’
`’
`’ 438/666
`
`.
`(58) Fleld of Search ................................. 438/125, 106,
`438/455’ 456’ 459’ 618’ 620’ 637’ 666
`References Cited
`U.S. PATENT DOCUMENTS
`
`(56)
`
`4/2001 Khoury et al.
`6,218,203 B1 *
`................ 438/15
`
`2/2003 Shroff et a1.
`6,515,343 B1 *
`..... 257/530
`6,656,826 B2 * 12/2003 Ishimaru ..................... 438/612
`6,720,212 B2 *
`4/2004 Robl et a1. .................. 438/132
`
`A method of connecting elements such as semiconductor
`devices and a device having connected elements such as
`semiconductor devices. Afirst element having a first contact
`structure is bonded to a second element having a second
`contact structure. A single mask is used to form a via in the
`first element
`to expose the first contact and the second
`contact. The first contact structure is used as a mask to
`expose the second contact structure. A contact member is
`formed In contact With the first and second contact struc-
`tures. The first contact structure may have an aperture or gap
`through Which the first and second contact structures are
`connected. Aback surface of the first contact structure may
`be eX 056d b
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`48 Claims, 11 Drawing Sheets
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`U.S. Patent
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`Mar. 15, 2005
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`Sheet 1 0f 11
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`US 6,867,073 B1
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`Mar. 15, 2005
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`Sheet 2 0f 11
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`US 6,867,073 B1
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`FIG. ZC
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`Sheet 3 0f 11
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`US 6,867,073 B1
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`Sheet 4 0f 11
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`US 6,867,073 B1
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`Sheet 5 0f 11
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`US 6,867,073 B1
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`FIG. 8A
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`Sheet 6 0f 11
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`US 6,867,073 B1
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`Sheet 7 0f 11
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`US 6,867,073 B1
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`FIG. 9C:
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`Sheet 8 0f 11
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`US 6,867,073 B1
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`Sheet 9 0f 11
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`US 6,867,073 B1
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`FIG. 13
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`Mar. 15, 2005
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`Sheet 10 0f 11
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`Sheet 11 0f 11
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`FIG. 17
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`US 6,867,073 B1
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`1
`SINGLE MASK VIA METHOD AND DEVICE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is related to applications Ser. Nos.
`09/532,886, now U.S. Pat. No. 6,500,794 and 10/011,432,
`the entire contents of which are incorporated herein by
`reference.
`
`BACKGROUND OF THE INVENTION
`
`10
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`2
`The substrate is thus typically removed to the greatest extent
`practicable,
`leaving sufficient residual substrate to avoid
`damage to the transistors. An interconnection to the die IC
`is then preferably made by etching a via through the remain-
`ing substrate to an interconnection location in the die IC,
`such that there are no necessary transistors in the vicinity of
`this via. It is furthermore preferable, in order to achieve the
`highest interconnection density, to continue this via through
`the entire die-IC and into the wafer-IC to an interconnection
`
`location in the wafer IC. This via typically extends through
`an insulating dielectric material that provides desired elec-
`trical isolation from interconnection locations in the die IC
`
`1. Field of the Invention
`
`invention relates to the field of three-
`The present
`dimensional integrated circuits and more particularly to the
`fabrication of three-dimensional integrated circuits using
`direct wafer bonding.
`2. Description of the Related Art
`Semiconductor integrated circuits (ICs) are typically fab-
`ricated into and on the surface of a silicon wafer resulting in
`an IC area that must increase as the size of the IC increases.
`
`Continual improvement in reducing the size of transistors in
`ICs, commonly referred to as Moore’s Law, has allowed a
`substantial increase in the number of transistors in a given IC
`area. However, in spite of this increased transistor density, a
`continual demand in increased IC complexity and function-
`ality has resulted in a continued increase in IC chip area.
`This increase in chip area results in a reduction in chip yield
`and, correspondingly, increased chip cost.
`Another trend in IC fabrication has been to increase the
`
`number of different types of circuits within a single IC, more
`commonly referred to as a System-on a-Chip (SoC). This
`fabrication typically requires an increase in the number of
`mask levels to make the different types of circuits and an
`increase in IC area to accommodate the increased number of
`
`types of circuits. This increase in mask levels and IC area
`also result in a reduction in yield, and correspondingly,
`increased chip cost.
`An approach to avoiding this undesired decrease in yield
`and increase in cost is to vertically stack and subsequently
`interconnect ICs. These ICs can be of different size, come
`from different size wafers, comprise different functions (i.e.,
`analog, digital, optical), be made of different materials (i.e.,
`silicon, GaAs, InP, etc.). The ICs can be tested before
`stacking to allow Known Good Die (KGD) to be combined
`to improve yield. The success of this stack first, interconnect
`second approach depends on the yield and cost of the
`stacking and interconnection being favorable compared to
`the yield and cost associated with the increased IC area or
`SoC. A generic method for realizing this approach is to stack
`ICs using direct bonding and to interconnect ICs using
`conventional wafer thinning, photolithography masking, via
`etching, and interconnect metallization.
`The cost of the interconnect portion of this approach is
`directly related to the number of photolithography masking
`levels required to etch vias and form electrical interconnects.
`It is thus desirable to minimize the number of photolithog-
`raphy masking levels required to etch vias and form elec-
`trical interconnects.
`
`One version of vertical stacking and interconnection is
`where ICs (on a substrate) are bonded face-to-face, or
`IC-side to IC-side. This version is typically done in a
`die-to-wafer format where die are bonded IC-side down, to
`a wafer IC-side up. In this format, after bonding, the die are
`typically substantially thinned by removing most of the die
`substrate. The die substrate can not, in general, be totally
`removed due to the location of transistors in the substrate.
`
`and wafer IC. After the formation of this via, it is typically
`necessary to interconnect the interconnection location in the
`die-IC with the interconnection location in the wafer-IC.
`
`15
`
`This is preferably done with a conductive material on an
`insulating layer between the conductive material and the
`exposed substrate on the via sidewall to avoid undesired
`electrical conduction between the conductive material and
`the substrate.
`
`The fabrication of this structure typically takes four
`photolithography masking levels to build. These levels are
`1) via etch through substrate, 2) via etch through insulating
`dielectric material in the die IC and wafer IC that exposes
`desired conductive material in the die IC and wafer IC, 3) via
`etch through the insulating layer that electrically isolates the
`conductive material that interconnects the interconnect loca-
`tion in the die IC with the interconnect location in the wafer
`
`IC to the exposed substrate via sidewall that exposes desired
`conductive material in the die IC and wafer IC, 4) intercon-
`nection with conductive material between exposed intercon-
`nection point in the die IC with exposed interconnection
`point in the wafer IC.
`The patterns defining the via etching through the insulat-
`ing (dielectric) material(s) are typically smaller than the
`pattern defining the via etch through the substrate to
`adequately expose the interconnection points in the die IC
`and wafer IC and to avoid removing insulating material on
`the substrate via sidewall. Since these patterns are formed
`after the via in the substrate, this patterning is typically done
`at a lower topographical level that the patterning of the
`substrate via. This results in a patterning over a non-planar
`structure that limits the scaling of the structure to very small
`feature size that is desirable to achieve the highest intercon-
`nection density and consumes the least possible silicon
`substrate where functional
`transistors would otherwise
`reside.
`
`It is thus desirable to have a device that comprises a
`structure and a method to fabricate the structure requiring a
`reduced number of masking steps and masking steps that can
`be realized on a planar surface, at the highest, or one of the
`highest, levels of topography in the structure.
`
`SUMMARY OF THE INVENTION
`
`The present invention is directed to a method and device
`where a single masking step is used to etch a via or vias
`through a substrate in a first device to expose contacts in first
`and second devices to provide for interconnection of the
`contacts.
`
`As one example, a single masking step can be used to etch
`a via through a remaining portion of a substrate, etch a via
`through insulating material exposing conductive material in
`two separate and vertically stacked IC devices, cover desired
`exposed remaining substrate portion surfaces with a desired
`insulating material, and expose conductive material in two
`separate IC devices by removing desired insulating material
`
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`US 6,867,073 B1
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`3
`from said conductive material without removing desired
`insulating material from said desired exposed remaining
`substrate surfaces.
`
`The present invention is further directed to a method and
`device comprising interconnection between interconnection
`points in the two separate IC devices where a masking step
`is not done at a lower topographical level than the single
`masking step.
`It is an object of the present invention to etch a via through
`different materials, exposing conductive material on at least
`two different topographical levels lower than a top surface
`using a single masking step.
`It is a further object of the present invention to mask an
`interconnect level, interconnecting two subcutaneous con-
`ductive layers, at a level above the two subcutaneous con-
`ductive layers.
`It is another object of the present
`patterning a mask in a recess.
`Another object of the present invention is to maximize the
`interconnect density between two stacked ICs.
`Another object of the present invention is to minimize the
`amount of substrate used to form an interconnection
`between two stacked ICs.
`
`invention to avoid
`
`These and other objects are achieved by a device having
`a first element having a first contact structure and a second
`element having a second contact structure. The first element
`is bonded the second element. Afirst via is formed in the first
`element and extends from a back surface of the first element
`to the first contact structure. A second via extends from the
`first contact structure to the second contact structure and
`communicates with the first via. A contact member connects
`the first and second contact structures.
`
`These and other objects are also achieved by a method of
`interconnecting first and second elements bonded together,
`including forming one mask over an exposed side of said
`first element, using the one mask to etch the first element and
`expose a first contact structure in the first element, etch
`through a bond interface between the first and second
`elements, and expose a second contact structure in the
`second element, and connecting the first and second contact
`structures.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A more complete appreciation of the present invention
`and many attendant advantages thereof will be readily
`obtained as the same becomes better understood by refer-
`ence to the following detailed description when considered
`in connection with the accompanying drawings, wherein:
`FIG. 1 is a diagram showing die to be bonded face-down
`to a wafer face-up;
`FIG. 2A is a diagram of die bonded to a substrate;
`FIG. 2B is a diagram of die bonded to a substrate with a
`portion of the substrate of the die removed;
`FIG. 2C is a diagram of a substrate bonded to another
`substrate;
`FIG. 3A is a diagram showing formation of a dielectric
`film and mask layer over the structure of FIG. 2A;
`FIG. 3B is a diagram showing formation a dielectric film
`and mask layer after forming a planarizing material;
`FIG. 4 is a diagram showing apertures formed in the
`dielectric film and mask layer of FIGS. 3A and 3B;
`FIG. 5 is a diagram showing etching of the die using the
`aperture formed as shown in FIG. 4;
`FIG. 6A is a diagram showing further etching to expose
`contact structures in the die and wafer;
`
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`FIG. 6B is a diagram of a process modification including
`forming a hard mask;
`FIG. 7A is a diagram of a section of the structure of FIG.
`6A after formation of a conformal insulative sidewall layer;
`FIG. 7B is a variation of the embodiment where the hard
`mask is removed;
`FIG. 8A is a diagram showing anisotropic etching of a
`conformal insulative sidewall layer;
`FIG. 8B is a variation of the embodiment where the hard
`mask is removed;
`FIG. 9A is a diagram showing forming a metal contact
`comprising a metal seed layer and a metal fill;
`FIG. 9B is a variation of the embodiment where the hard
`mask is removed;
`FIG. 9C is a variation of the embodiment where no seed
`
`layer is formed;
`FIG. 10A is a diagram of the structure of FIG. 9A or 9B
`after chemo-mechanical polishing;
`FIG. 10B is a diagram of the structure of FIG. 9C after
`chemo-mechanical polishing;
`FIG. 11 is a diagram illustrating metallization of the
`structure of FIG. 10A;
`FIG. 12 is a diagram of a second embodiment using a
`mask layer without an intervening dielectric layer;
`FIG. 13 is a diagram showing forming a metal contact in
`the second embodiment;
`FIG. 14 is a diagram showing the structure of FIG. 13
`after chemo-mechanical polishing;
`FIG. 15 is a diagram illustrating another embodiment of
`the invention;
`FIG. 16A is a diagram illustrating an embodiment where
`a contact structure is located in the surface of one of the
`devices;
`FIG. 16B is a diagram of the structure of FIG. 16A after
`further processing;
`FIG. 17 is a diagram showing a device produced using the
`method according to the invention with the structure shown
`in FIGS. 16A and 16B;
`FIG. 18 is a diagram of another embodiment of the
`invention; and
`FIG. 19 is a diagram showing a device produced using the
`method according to the invention with the structure shown
`in FIG. 18.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`Referring now to the drawings, in particular FIG. 1, a first
`embodiment of the method according to the invention will
`be described. It is noted here that the drawings are not drawn
`to scale but are drawn to illustrate the concepts of the
`invention.
`
`Substrate 10 includes a device region 11 having contact
`structures 12. Substrate 10 may be made of a number of
`materials, such as semiconductor material or
`insulating
`material, depending on the desired application. Typically,
`substrate 10 is made of silicon or III—V materials. Contact
`
`structures 12 are typically metal pads or interconnect struc-
`tures making contact to device or circuit structures (not
`shown) formed in substrate 10. Substrate 10 may also
`contain an integrated circuit to which the contact structures
`12 are connected, and substrate 10 may be a module
`containing only contact structures. For example, substrate 10
`may be a module for interconnecting structures bonded to
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`substrate 10, or bringing out connections for packaging or
`integration with other modules or circuit structures on, for
`example, a printed circuit board. The module may be made
`of insulative materials such as quartz or ceramic.
`Positioned for bonding to substrate 10 on surface 13 are
`three separated die 14—16. Each die has a substrate portion
`19, a device region 18 and contact structures 17. The die may
`be previously separated from another wafer by dicing, etc.
`Die 14—16 may be made of a number of materials, such as
`semiconductor materials, depending on the desired applica-
`tion. Typically, the substrate is made of silicon or III—V
`materials. Contact structures 17 are typically metal pads or
`interconnect structures making contact to device or circuit
`structures formed in device region 18. The sizes of pads 12
`and 17 each may vary. The sizes and relative sizes are
`dependent upon alignment tolerances, circuit design param-
`eters or other factors. The sizes of the pads are drawn to
`illustrate the inventive concepts are and are not meant to be
`limiting. Device region 18 may also contain an integrated
`circuit to which the contact structures 17 are connected.
`
`Substantially all of substrate portion 19 may be removed,
`leaving a layer of devices, a circuit, or a circuit layer. Also,
`the substrates of dies 14—16 may be thinned after bonding to
`a desired thickness.
`
`Die 14—16 may be of the same technology as wafer 10, or
`of different technology. Die 14—16 may each be the same or
`different devices or materials. Each of die 14—16 has con-
`
`ductive structures 17 formed in a device region 18. Struc-
`tures 17 are spaced apart to leave a gap therebetween, or may
`be a single structure with an aperture which may extend
`across the entire contact structure.
`In other words,
`the
`aperture may be a hole in contact structure or may divide the
`contact structure in two. The size of the gap or aperture may
`be determined by the photolithographic ground rules for the
`particular technology being bonded, i.e., at least a minimum
`width for the subsequent contact connecting structures 12
`and 17 to be reliably formed with sufficiently low contact
`resistance.
`
`An additional factor that determines the optimum size of
`the gap or aperture is a ratio of a distance given by the
`vertical separation between conductive structures 17 and 12
`plus the thickness of the conductive structure 17 to the size
`of the gap or aperture. This defines an aspect ratio of a via
`that will subsequently be formed between conductive struc-
`tures 17 and 12 to enable electrical interconnection between
`
`structures 17 and 12. This vertical separation is typically 1—5
`microns for oxide to oxide direct bonding, as described in
`application Ser. No. 09/505,283, the contents of which are
`incorporated herein by reference, or potentially zero for
`metal direct bonding, as described in application Ser. No.
`10/359,608, the contents of which are herein incorporated by
`reference. Furthermore, the conductive structure 17 thick-
`ness is typically 0.5 to 5 microns. With a typical desired via
`aspect ratio of 0.5 to 5 depending on the process technology
`used, a typical range of the size of the gap is 0.3—20 microns
`for oxide to oxide bonding or ~0.1—10 microns for metal
`direct bonding.
`Dies 14—16 are generally aligned with the contact struc-
`tures 12 such that structures 17 and the gap or aperture are
`positioned over corresponding contact structures 12. The
`size of contact structures 12 is chosen to allow die 14—16 to
`
`be simply aligned with the gap between structures 17. This
`size depends on the alignment accuracy of the method used
`to place die 14—16 on substrate 10. Typical methods using
`commercially available production tools allow alignment
`accuracies in the range of 1—10 microns, although future
`improvements in these tools is likely to result in smaller
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
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`55
`
`60
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`65
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`6
`alignment accuracies. The lateral extent of structures 17
`exterior to the gap or aperture is preferably at least a distance
`given by this alignment accuracy.
`Although only one set of structures 17 is shown for each
`die 14—16, it is understood that the lateral extent of struc-
`tures 17 is typically much smaller than the lateral extent of
`each die 14—16, so that each die may have several or a very
`large number of structures 17. For example, structures 17
`may have a lateral extent in the range of 1—100 microns and
`die 14—16 may have a lateral extent in the range of 1—100
`mm. Aquantity of structures 17 in die 14—16 having an order
`of magnitude 104 and much higher is thus practically
`realizable.
`
`As shown in FIG. 2A, surface 20 of die 14 is bonded to
`surface 13 of substrate 10. This may be accomplished by a
`number of methods, but
`is preferably bonded at room
`temperature using a bonding method as described in appli-
`cation Ser. No. 09/505,283. The bonding of die 14—16 to
`substrate 10 is illustrated in FIG. 2. After bonding the
`substrates of die 14—16 are thinned. Thinning is typically
`achieved by polishing, grinding, etching, or a combination
`of these three techniques to leave thinned substrate 21 or to
`completely remove substrate portion 19. FIG. 2B illustrates
`the example where substrate portion 19 is completely or
`substantially completely removed. Also, the substrates of
`dies 14—16 may be thinned prior to bonding.
`While three die are shown bonded to a single substrate 10
`in FIG. 2A, it is also possible to bond a larger or smaller
`number of die to substrate 10. Also, it is possible to bond
`another substrate of a size comparable to that of substrate 10,
`which is illustrated in FIG. 2C where a substrate 22 having
`a device region 23 is bonded to wafer 10 such that spaced
`apart conductive structures 24 are generally aligned with
`conductive structures 12. Substrate 22 may be thinned or
`removed prior to bonding to facilitate alignment. Substrate
`22 may be thinned after bonding, and substantially all of
`substrate 22 may be removed if desired. The procedures
`described in the following figures are also applicable to the
`structures shown in FIGS. 2B and 2C, but separate drawings
`are omitted for brevity.
`As shown in FIG. 3A, a conformal dielectric film 30 is
`formed over surface 13 of substrate 10 and dies 14—16. This
`
`film may be formed by, for example, CVD, PVD or PECVD
`and preferably consists of an oxide film such as silicon
`oxide. Also, a filler material such as a deposited or spun-on
`oxide or polymer 32 such as polyimide or benzocyclobutene
`may be formed over and/or between dies 14—16, as shown
`in FIG. 3B. Material 32 may be formed at various points in
`the process. FIG. 3B shows the example where material 32
`is formed prior to forming films 30 and 31. Filler, material
`may also be formed after forming the structure shown in
`FIGS. 3A, after forming mask 40 (FIG. 4), or at various
`other points in the process depending on many factors such
`as the materials chosen or temperature considerations. Hav-
`ing a flat surface may improve forming photoresist and other
`films on the surface and forming apertures in such films, for
`example, aperture 41 shown in FIG. 4.
`Subsequently, a hard mask 31 is formed on dielectric film
`30 and patterned to leave apertures 41 generally aligned with
`structures 17 (FIG. 4). The hard mask is preferably com-
`prised of a material that has a high etch selectivity to a
`subsequent etch process or processes used to etch a via
`through thinned substrate 21 and device regions 18 and 11
`to contact structures 12. Examples of a hard mask are
`aluminum,
`tungsten, platinum, nickel, and molybdenum,
`and an example of an etch process is an SF6-based reactive
`
`TSMC1007
`
`IPR of U.S. Pat. No. 7,485,968
`
`TSMC1007
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`US 6,867,073 B1
`
`7
`ion etch to etch a via through a thinned silicon substrate and
`a CF4-based reactive ion etch to etch a subsequent via
`through device regions 18 and 11 to contact structures 12.
`Aperture 41 is formed using standard photolithographic
`patterning and etching techniques of the hard mask 31 and
`dielectric film 30. For example, an aperture can be formed
`in photoresist using photolithography. This aperture can be
`aligned to alignment marks on the die 14—16 (or substrate
`22), or substrate 10. Optical or IR imaging can be used for
`the alignment. The hard mask 31 can then be etched with an
`appropriate wet chemical solution or a dry reactive ion etch
`that depends on the hard mask material, revealing the
`dielectric film 30 in the aperture. The dielectric film 30 can
`then be etched in a manner similar to the hard mask 31 with
`
`an appropriate wet chemical solution or a dry reactive ion
`etch that depends on the dielectric film material. An example
`of a wet chemical solution for a hard mask is Aluminum
`
`10
`
`15
`
`Etchant Type A if the hard mask is Aluminum. An example
`of a reactive ion etch for a dielectric film material is a
`CF4-based reactive ion etch if the dielectric film material is
`
`20
`
`silicon oxide. Many other wet and dry etches are possible for
`these and other hard mask and dielectric film materials. The
`
`width of the apertures 41 is preferably wider than the
`spacing between the structures 17 if the aperture is aligned
`to the die 14—16 (or substrate 22), or, preferably wider than
`the spacing between the structures 17 plus the alignment
`accuracy of the method used to place die 14—16 (or substrate
`22), on substrate 20 if the aperture is aligned to the lower
`substrate 20.
`
`Using the hard mask 40, substrate portions of dies 14—16
`are etched to form vias 50, as shown in FIG. 5. The etching
`is continued through the material surrounding conductive
`structures 12 and 17, which typically is a dielectric material,
`to expose back and side portions of conductive structure 17
`and a top surface of conductive structures 12. A first set of
`gases and conditions, for example SF6-based, may be used
`to etch through the substrate material of dies 14—16, and a
`second set of gases and conditions, for example CF4-based,
`may be used to etch through the dielectric layers surround-
`ing the contact structures 17. Both etches may be performed
`in one chamber by switching gases and conditions
`appropriately, without having to break vacuum. The etching
`to expose conductive structure 12 is shown in FIG. 6A. The
`etching produces a via portion 60 extending through the gap
`or aperture of conductive structures 17 to conductive struc-
`ture 12.
`
`The dielectric via etching to expose conductive structures
`12 and 17 preferably has a high etch selectivity to conduc-
`tive structures 17 so as to avoid a detrimental amount of
`
`etching to conductive structures 17. However, there may be
`some combinations of dielectric via etching and conductive
`structures that result in a detrimental amount of etching to
`conductive structures 17. For example, detrimental effects
`may occur when conductive structure 17 is sufficiently thin
`or when the vertical distance between conductors 12 and 17
`
`is sufficiently large.
`An example of a detrimental amount of etching is some
`combinations of aluminum conductive structures 17 sur-
`
`rounded by silicon oxide dielectric and some CF4-based
`reactive ion etches where the ratio of the aluminum con-
`ductive structure etch rate to the silicon oxide dielectric etch
`
`rate is comparable to or higher than the ratio of the thickness
`of conductive structure 17 to the thickness of silicon oxide
`dielectic between conductive structures 12 and 17.
`In those situations where there would be a detrimental
`
`amount of etching to contact structures 17, the thickness of
`
`25
`
`30
`
`35
`
`40
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`45
`
`50
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`55
`
`60
`
`65
`
`8
`conductive structures 17 may be increased or an intermedi-
`ate step is added to protect conductive structures 17 from the
`dielectric via etch. An intermediate process step can be used
`to avoid detrimental etching as follows. When the dialectic
`etching first exposes back and side portions of upper con-
`ductive structure 17, a hard mask, such as a metal material,
`can be selectively deposited on revealed portions of con-
`ductive structure 17 before continuation of the dielectric
`
`etching results in detrimental etching to conductive structure
`17. After selective deposition of a hard mask, the dielectric
`etching can be continued without detrimental etching to
`conductive structure 17. An example of a selective deposi-
`tion of a hard mask is electroless nickel plating. This is
`shown, for example, in FIG. 6B where etching is stopped
`after exposing contact structures 17 and before any signifi-
`cant detrimental etching occurs. Contact structures 17 are
`then coated with a protective hard mask material 61, for
`example, nickel using, for example, electroless plating. A
`material such as nickel may remain in the device in subse-
`quent connecting of the structures 12 and 17. Alternatively,
`the material 61 may be removed before forming connecting
`structures 12 and 17, if needed.
`Note that protective hard mask 61 may also be selectively
`deposited on hard mask 40. An example is when hard mask
`40 is conductive and deposition of protective hard mask 61
`is accomplished with electroless plating This may be advan-
`tageous for decreasing the required thickness of hard mask
`40. A further advantage of deposition of protective hard
`mask material 61 on hard mask 40 may be a restriction of the
`aperture of via 50 resulting in shadowing of a portion of
`contact structures 17 from anisotropic etching of via 60.
`FIG. 7A illustrates one of the elements 14—16 in detail to
`
`more clearly illustrate the subsequent steps. A conformal
`insulative film 70 is formed over mask 40 and conductive
`structures 12 and 17, and the sidewall of vias 50 and 60,
`partially filling vias 50 and 60. Examples of a suitable
`insulative film are silicon oxide, silicon nitride or Parylene.
`The insulative film may be formed using a number of typical
`deposition methods including but not limited to physical
`vapor deposition, chemical vapor deposition, and vapor
`phase deposition. An example of physical vapor deposition
`is sputtering, an example of chemical vapor deposition is
`plasma enhanced chemical vapor deposition, and an
`example of vapor phase deposition is vaporization of a solid,
`followed by pyrolysis and then deposition.
`Mask 40 or mask 40 and dielectric film 30 may be
`removed before formation of conformal insulative film 70
`
`by, for example, etching. FIG. 7B illustrates the case where
`mask 40 is removed. If the etch to remove mask 40 or mask
`
`40 and film 30 is selective to materials exposed by vias 50
`and 60, this etch can be done without a mask. If this etch is
`not selective to materials