(12) United States Patent
`US 6,465,892 B1
`(45) Date of Patent:
`Suga
`Oct. 15, 2002
`
`(10) Patent N0.:
`
`USOO6465892B1
`
`(54)
`
`INTERCONNECT STRUCTURE FOR
`STACKED SEMICONDUCTOR DEVICE
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(75)
`
`Inventor: Tadatomo Suga, Tokyo (JP)
`
`(73) Assignees: Oki Electric Industry C0., Ltd., Tokyo
`(JP); Sanyo Electric C0., Ltd., Osaka
`(JP); Sony Corporation, Tokyo (JP);
`Kabushiki Kaisha Toshiba, Kanagawa
`(JP); NEC Corporation, Tokyo (JP);
`Sharp Kabushiki Kaisha, Osaka (JP);
`Hitachi, Ltd., Tokyo (JP); Fujitsu
`Limited, Kanagawa (JP); Matsushita
`Electronics Corporation, Osaka (JP);
`Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP); R0hm C0., Ltd., Kyoto
`(JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.:
`
`09/548,916
`
`(22)
`
`Filed:
`
`Apr. 13, 2000
`
`(30)
`
`Foreign Application Priority Data
`
`Apr. 13, 1999
`
`(JP)
`
`........................................... 11—105970
`
`(51)
`
`Int. Cl.7 ......................... H01L 23/48; H01L 23/52;
`H01L 29/40; H01L 21/30; H01L 21/46
`....................... 257/777; 257/782; 257/783;
`(52) US. Cl.
`257/753; 438/455; 438/107; 438/109; 438/118;
`228/122.1; 228/123.1
`(58) Field of Search ................................. 438/455—459,
`438/106—107; 257/753, 508, 665, 685—688,
`777, 782—783; 228/1221, 123.1
`
`5
`
`
`4,829,018 A *
`5,419,806 A *
`5,626,279 A *
`5,902,118 A *
`6,080,640 A *
`
`5/1989 Wahlstrom .................. 438/154
`5/1995 Huebner ................... 216/20
`
`5/1997 Pamler et al.
`228/123.1
`5/1999 Hubner .................... 438/106
`
`............. 438/455
`6/2000 Gardner et al.
`
`* cited by examiner
`
`Primary Examiner—Charles Bowers
`Assistant Examiner—Erik J Kielin
`
`(74) Attorney, Agent, or Firm—Sonnenschein, Nath &
`Rosenthal
`
`(57)
`
`ABSTRACT
`
`In a multi-layer interconnection structure, the Wiring length
`is to be reduced, and the interconnection is to be
`straightened, at the same time as measures need to be taken
`against radiation noise. To this end, there is disclosed a
`semiconductor device in which plural semiconductor
`substrates, each carrying semiconductor elements, are
`bonded together. On each semiconductor substrate is depos-
`ited an insulating layer through which is formed a connec-
`tion Wiring passed through the insulating layer so as to be
`connected to the interconnection layer of the semiconductor
`element. On a junction surface of at
`least one of the
`semiconductor substrates is formed an electrically conduc-
`tive layer of an electrically conductive material in which an
`opening is bored in association with the connection Wiring.
`The semiconductor substrates are bonded together by the
`solid state bonding technique to interconnect the connection
`Wirings formed on each semiconductor substrate.
`
`11 Claims, 10 Drawing Sheets
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`US. Patent
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`Oct. 15, 2002
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`Sheet 1 0f 10
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`US 6,465,892 B1
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`US. Patent
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`Oct. 15, 2002
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`Sheet 2 0f 10
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`US 6,465,892 B1
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`US. Patent
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`Oct. 15, 2002
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`Sheet 3 0f 10
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`US 6,465,892 B1
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`US. Patent
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`Sheet 4 0f 10
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`US. Patent
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`Sheet 5 0f 10
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`US. Patent
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`Oct. 15, 2002
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`Sheet 6 0f 10
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`US. Patent
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`Oct. 15, 2002
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`Sheet 7 0f 10
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`US 6,465,892 B1
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`US. Patent
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`Sheet 8 0f 10
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`FIG.9A ——21b}2121a
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`FIG.9C
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`FIG.9D
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`US. Patent
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`Oct. 15, 2002
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`Sheet 9 0f 10
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`US 6,465,892 B1
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`US. Patent
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`Oct. 15, 2002
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`Sheet 10 0f 10
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`US 6,465,892 B1
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`US 6,465,892 B1
`
`1
`INTERCONNECT STRUCTURE FOR
`STACKED SEMICONDUCTOR DEVICE
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`This invention relates to a semiconductor device in which
`
`layered films and wiring layers on a semiconductor substrate
`are bonded together using the solid state bonding technique,
`and a manufacturing method therefor. More particularly, it
`relates to an improvement intended for reducing radiation
`noises.
`
`2. Description of the Related Art
`In the field of semiconductor devices, there has so far
`been known a electromagnetic noise shield for eliminating
`the noise in which an electrically conductive material is
`applied to the perimeter of a wiring layer on a semiconductor
`substrate in an encapsulating fashion, as disclosed for
`example in Japanese Laying-Open Patent H-5-47767.
`There is also known from the Japanese Laying-Open
`Patent H-5-47943 such a structure in an analog/digital
`hybrid semiconductor device in which a shield line is
`arranged between a high-frequency digital signal line and an
`analog signal
`line susceptible to noise, at points of
`intersections, and a shield line is arranged as upper and
`lower layers and on lateral sides of the analog signal lines.
`In the above-described conventional technique, the wiring
`on the same semiconductor substrate is encapsulated via an
`insulator with an electrically conductive material to prevent
`the effect of the radiation noise. This structure is effective to
`
`prevent occurrence of radiation noise on the same semicon-
`ductor substrate.
`
`However, if the radiation noise on the multi-layer semi-
`conductor substrate is to be prohibited from occurring, the
`above-mentioned structure cannot directly be used.
`Specifically, with the multi-layer semiconductor
`substrate, a multi-layer film-forming process is required.
`With the increasing number of layers of the multi-layer film,
`the surface of the multi-layer film becomes increasingly
`irregular such that planar smoothness is lost. If the number
`of layers is increased further,
`the film surface becomes
`increasingly irregular to cause line breakage in the course of
`the process. This indicates that difficulties are met in form-
`ing the shield line as described above.
`If a higher operating speed is achieved in the semicon-
`ductor device in time to come,
`it becomes necessary to
`reduce the length of the wiring (to increase the density) and
`to use wirings closer to straight wirings. That is, since the
`radiation level is higher in keeping pace with the increase in
`the operating speed, it is necessary to take measures against
`radiation noise,
`to reduce the length of the wiring (to
`increase the density) and to use wirings closer to straight
`wirings.
`This is intimately related to a device structure of the
`semiconductor substrate, such that it is necessary to attempt
`to increase the operating rate of the semiconductor substrate
`in consideration of the grounding layer, power source layer
`and the wiring layer surrounding the device structure.
`SUMMARY OF THE INVENTION
`
`It is therefore an object of the present invention to provide
`a novel semiconductor device in which it is possible to
`reduce the length of the wiring, to use wirings closer to
`straight wirings and to take measures against radiation noise,
`and a method for manufacturing the novel semiconductor
`device.
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`2
`In one aspect, the present invention provides a semicon-
`ductor device in which a plurality of semiconductor
`substrates, each carrying semiconductor elements, are
`bonded together, wherein an insulating layer is deposited on
`each semiconductor substrate, there being formed a connec-
`tion wiring passing through the insulating layer for connec-
`tion to a wiring layer on the semiconductor elements, and
`wherein an electrically conductive layer of an electrically
`conductive material, having an opening formed by pattern-
`ing in register with the connection wiring, is formed on a
`junction surface of at least one of the semiconductor sub-
`strates. The semiconductor substrates are bonded together to
`interconnect the connection wirings formed on each semi-
`conductor substrate.
`
`In another aspect, the present invention provides a method
`for manufacturing a semiconductor device in which a plu-
`rality of semiconductor substrates, each carrying semicon-
`ductor elements, are bonded together, including the steps of
`depositing an insulating layer on a semiconductor substrate
`and forming a connection wiring connected to a wiring layer
`of the semiconductor elements in the insulating layer, form-
`ing an electrically conductive layer of an electrically con-
`ductive material, having an opening formed by patterning in
`register with the connection wiring, on a junction surface of
`at least one of the plural semiconductor substrates, smooth-
`ing the junction surface of each semiconductor substrate and
`applying a compressive load from both sides of the semi-
`conductor substrates placed one on another to interconnect
`the semiconductor substrates and to interconnect the con-
`
`nection wirings formed in each semiconductor substrate.
`According to the present invention, a wiring electrode and
`a grounding electrode are provided on each semiconductor
`substrate carrying semiconductor elements. An insulating
`layer and a grounding layer as an electrically conductive
`layer are deposited in this order on the surface of each
`semiconductor substrate. An opening is bored in the insu-
`lating layer and in the grounding layer and a grounding layer
`electrode and the grounding layer are electrically connected
`to each other via an electrically conductive material charged
`into the opening. The surfaces of the semiconductor
`substrates, formed by multiple layers, are planarized and
`smoothed. The planarized surfaces of the two semiconductor
`substrates are placed in a facing relation and aligned with
`respect to each other. The semiconductor substrates, thus
`aligned, are bonded to each other by applying loads thereon.
`By this technique, that is by forming a grounding layer
`between the two substrates, the radiation noise generated
`from respective elements on the semiconductor substrate are
`absorbed by the grounding layer while the radiation noise
`generated from each element on the opposite side semicon-
`ductor substrate is similarly absorbed by the grounding
`layer, so that
`it
`is possible for the grounding layer to
`eliminate the reciprocal effect on the semiconductor ele-
`ments on the semiconductor substrates. Since a common
`
`grounding layer is provided between the two substrates, it is
`possible to effect three-dimensional grounding interconnec-
`tion via the opening to reduce the grounding wiring length.
`Alternatively, a grounding layer and a power source layer,
`common to two semiconductor substrates, are provided
`between the two semiconductor substrates. That
`is,
`the
`wiring electrode, grounding electrode and the power source
`electrode are provided on one of the semiconductor sub-
`strates carrying the semiconductor elements, an insulating
`layer, a grounding layer and an insulating layer are sequen-
`tially formed on the surface of the semiconductor substrate,
`and openings are formed in the insulating layer, grounding
`layer and in the insulating layer. An electrically conductive
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`3
`member is placed in the openings. The grounding layer is
`electrically connected to the grounding electrode. The elec-
`trically conductive member in one of the openings is con-
`nected to the power source electrode while the electrically
`conductive member in the remaining opening is connected
`to the wiring electrode. The grounding wiring layer, power
`source wiring layer and the through-hole wiring are electri-
`cally insulated by an insulator, followed by surface polish-
`ing.
`On the opposite side semiconductor substrate, carrying
`semiconductor elements, a wiring electrode, a grounding
`electrode and a power source electrode are provided, while
`an insulating layer and a power source layer are sequentially
`formed on the substrate surface. There are formed openings
`in the insulating layer and the power source layer and an
`electrically conductive member is placed in the openings.
`The grounding layer is electrically connected to the ground-
`ing electrode. The electrically conductive member in one of
`the openings is electrically connected to the power source
`wiring, while the electrically conductive member in the
`remaining opening is connected to the wiring electrode. The
`grounding wiring layer, power source wiring layer and the
`through-hole wiring are electrically insulated by an
`insulator, followed by surface polishing. The two substrates
`are placed in a facing relation to each other and aligned so
`that the wiring layers grounding layers and the power source
`wiring are aligned to one another, and a load is applied from
`both sides of the substrates.
`
`Since the grounding layer and the power source layer
`operating for grounding and as a power source of the
`respective elements of the two substrates are provided
`between the substrates, the wiring length can be effectively
`reduced, while the radiation noise generated from one of the
`semiconductor substrates can be absorbed by the grounding
`layer.
`The present invention thus provides an arrangement in
`which the grounding layer and the power source layer are
`sandwiched between the two substrates when the substrates
`
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`35
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`are bonded together. A way is provided for reducing the
`wiring and prohibiting reciprocal interference of the radia-
`tion noises from both substrates.
`
`40
`
`According to the present invention as described above,
`since an electrically conductive layer (grounding layer) is
`provided between the first and second substrates, each
`carrying semiconductor elements, radiation noises from the
`semiconductor elements on the first substrate can be
`
`shielded without affecting the semiconductor elements on
`the second substrate. Also, signal transmission between the
`first and second substrates can be realized by a connection
`wiring (through-hole wiring) provided in the grounding
`layer sandwiched between the first and second substrates.
`If a conductor layer serving as a power source layer is
`provided on each of the first and second substrates for
`extending parallel
`to a conductor layer operating as a
`grounding layer, these conductor layers can serve as power
`sources for the first and second substrates via the through-
`holes, thus improving the efficiency.
`Also,
`in the manufacturing method according to the
`present invention, the first and second substrates from the
`separate processes, carrying the semiconductor elements,
`are bonded together by the solid state bonding technique.
`Thus, the multi-layer substrates, comprised of semiconduc-
`tor substrates having different functions, can be produced
`easily, thus assuring efficient manufacture.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a schematic cross-sectional view showing an
`embodiment of a semiconductor device according to the
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`present invention, and especially showing the state prior to
`connection for unification.
`
`FIG. 2 is a schematic cross-sectional view showing the
`state of connection and unification of the semiconductor
`device of FIG. 1.
`
`FIG. 3 is a schematic cross-sectional view showing
`another embodiment of a semiconductor device according to
`the present invention, and especially showing the state prior
`to connection for unification.
`
`FIG. 4 is a schematic cross-sectional view showing the
`state of connection for unification of the semiconductor
`device of FIG. 3.
`
`FIG. 5 is a schematic cross-sectional view showing still
`another embodiment of a semiconductor device according to
`the present invention, and especially showing the state prior
`to connection for unification.
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`10
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`15
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`FIG. 6 is a schematic cross-sectional view showing the
`state of connection for unification of the semiconductor
`device of FIG. 5.
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`20
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`FIG. 7 is a schematic view showing an illustrative con-
`nection structure to an external driving circuit.
`FIG. 8 is a schematic view showing another illustrative
`connection structure to an external driving circuit.
`FIGS. 9A to 9G are schematic cross-sectional views
`
`showing, step-by-step, an illustrative manufacturing process
`by the solid state bonding.
`FIGS. 10A to 101 are schematic cross-sectional views
`
`showing, step-by-step, another illustrative manufacturing
`process by the solid state bonding.
`FIG. 11 is a schematic view showing another flat panel
`computer as an illustrative application.
`FIG. 12 is a schematic view showing an illustrative
`system LSI interconnecting process LSIs of different species
`by chip-on-chip.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Referring to the drawings, preferred embodiments of
`structure of a semiconductor device, and a manufacturing
`method therefor, according to the present invention, will be
`explained in detail.
`FIGS. 1 and 2 illustrate features of the semiconductor
`
`invention. In the present
`device embodying the present
`embodiment, a pair of semiconductor substrates 1, 2, each
`carrying semiconductor elements, are connected and unified
`to each other.
`
`On the substrates 1, 2 are formed wiring layers 3, 4, as
`semiconductor element
`interconnections,
`respectively.
`There are arranged connection wirings 5, 6, termed herein
`through-hole wirings, within openings,
`termed herein
`through-holes. The through-hole wirings 5, 6 may also be
`so-called plugs, adapted to assure electrically connection via
`electrically conductive members arranged in holes, instead
`of the so-called through-hole wirings.
`On the substrates 1, 2 are deposited insulating layers 7, 8.
`The through-hole wirings 5, 6 are formed by charging an
`electrically conductive material
`in through-holes 14, 15
`formed in these insulating layers 7, 8, respectively.
`On the insulating layers 7, 8 are deposited grounding
`wiring layers 9,10, formed of an electrically conductive
`metal material, respectively.
`The grounding wiring layers 9,10 are each formed sub-
`stantially as continuous uninterrupted pattern, except that
`through-holes 16, 17 connecting to the through-holes 14, 15
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`5
`formed in the insulating layers 7, 8, respectively, are bored
`therein substantially in register with the through-hole wir-
`ings 5, 6, respectively.
`Meanwhile, the through-holes 16, 17 are slightly larger in
`diameter than the through-holes 14, 15 to form gap with
`respect to the through-holes 7, 8. In this gap are embedded
`insulating materials 12, 13 to assure insulation between the
`grounding wiring layers 9,10 and the through-hole wirings
`5, 6. Therefore,
`the through-holes 16, 17 are desirably
`dimensioned so as not to cause dielectric breakdown of the
`insulating materials 12, 13 embedded in the gap defined
`between the grounding wiring layers 9,10 and the through-
`hole wirings 5, 6.
`In the above configuration, the through-hole 14 is first
`bored in the substrate by a photolithographic process, a
`film-forming process and a lift-off process. In the through-
`hole 14 is formed the through-hole wiring 5, using the
`photolithographic process and the lift-off process, as shown
`in FIG. 1. The grounding wiring layer 9 having the through-
`hole 16 then is formed on the insulating layer 7 and the
`through-hole wiring 5 is also formed in the through-hole 16.
`The insulating material 12 then is formed between the
`grounding wiring layer 9 and the through-hole wiring 5,
`followed by surface polishing.
`On the substrate 2, there are similarly formed the insu-
`lating layer 8, grounding wiring layer 10, through-hole 15,
`insulating material 13 and the through-hole wiring 6, fol-
`lowed by surface polishing.
`The substrates 1, 2 are placed in register with each other
`so that the grounding wiring layers 9, 10 face each other.
`There is then imposed a load from both sides of the
`substrates 1, 2.
`By the imposed load, the substrates 1, 2 are connected to
`each other, with the through-hole wirings 5, 6 and with the
`grounding wiring layers 9, 10 being bonded to each other.
`After the connection, electrical conduction between the
`through-hole wirings 5, 6 and that between the grounding
`wiring layers 9, 10 are verified. Meanwhile, the grounding
`wiring layers 9, 10 are electrically connected to a grounding
`electrode, not shown, of the substrate 1 and to a grounding
`electrode, not shown, of the substrate 2, respectively.
`In the present embodiment, silicon oxide films were used
`as the insulating layers 7,8 while copper was used as the
`grounding wiring layers 9, 10 and through-holes wirings 5,
`6. Also, silicon oxide films were used as the insulating
`materials 12, 13. It is also possible to use an Al oxide film
`or silicon nitride for the insulating layers 7, 8 and for the
`insulating materials 12, 13, and to use Au and Al for the
`grounding wiring layers 9, 10 and for the through-hole
`wirings 5, 6.
`FIGS. 3 and 4 show a configuration in which the ground-
`ing wiring layer is formed on only the substrate 1 of the
`paired substrates 1, 2 each carrying the semiconductor
`elements.
`
`On the substrates 1, 2 are formed wiring layers 3, 4, as
`interconnection for the semiconductor devices. The through-
`hole wirings 5, 6, formed in the through-holes, are electri-
`cally connected to these wiring layers 3, 4, respectively, as
`in the previous embodiment.
`On the substrates 1 and 2 are formed insulating layers 7,
`8, respectively. The through-hole wirings 5, 6 are formed by
`charging the electrically conductive material in through-
`holes 14, 15 formed in these insulating layers 7, 8, respec-
`tively.
`On solely the substrate 1, there is formed the grounding
`wiring layer 9 of e.g., an electrically conductive metal
`material, by layering on the insulating layer 7.
`
`6
`The grounding wiring layer 9 is formed substantially in a
`continuous pattern except that an opening (through-hole) 16,
`connecting to the through-hole 14 formed in the insulating
`layer 7, is bored therein substantially in register with the
`through-hole wiring 5.
`Meanwhile, the through-hole 16 is formed so as to be
`slightly larger than the through-hole 14. An insulating mate-
`rial 12 is buried in the gap between the outer periphery of the
`through-hole 16 and the through-hole wiring 5 to assure
`insulation between the grounding wiring layer 9 and the
`through-hole wiring 5.
`In the above configuration, the through-hole 14 is first
`formed in the substrate 1, using a photolithographic process,
`a film-forming process and a lift-off process. A through-hole
`wiring 5 then is formed in the through-hole 14, using the
`photolithographic process and the lift-off process, as shown
`in FIG. 3. On the insulating layer 7, there is then formed a
`grounding wiring layer 9, having the through-hole 16, in
`which the through-hole wiring 5 is also formed.
`Between the grounding wiring layer 9 and the through-
`hole wiring 5, an insulating material is formed, followed by
`surface polishing.
`The insulating layer 8, through-hole 15 and the through-
`hole wiring 6 are formed similarly, followed by surface
`polishing.
`The substrates 1, 2, thus prepared, are placed in alignment
`with each other so that the grounding wiring layer 9 and the
`insulating layer 8 will face each other, and a load is imposed
`from both sides of the substrates 1, 2.
`By the imposed load, the substrates 1, 2 were connected
`to each other, with the through-hole wirings 5, 6 being
`bonded to each other and with the grounding wiring layers
`9 being similarly bonded to each other. After the connection,
`electrically conduction between the through-hole wirings 5,
`6 is verified. Meanwhile, the grounding wiring layer 9 is
`electrically connected to a ground electrode, not shown, of
`the substrate 1.
`
`In the present embodiment, a silicon oxide films, copper,
`a silicon oxide film and copper, are used for the insulating
`layers 7, 8, grounding electrode layer 9, through-hole wir-
`ings 5, 6 and for the insulating material 12, respectively. It
`is also possible to use an Al oxide film and a silicon nitride
`for the insulating layers 7, 8 and for the insulating material
`12, and to use Au or Al for the grounding electrode layer 9
`and for the through-hole wirings 5, 6.
`FIGS. 5 and 6 show a configuration in which a power
`source wiring layer is formed on the substrate 1 of the paired
`substrates 1, 2 carrying the semiconductor elements and in
`which a grounding wiring layer is formed on the opposite
`side substrate 2.
`
`On the substrates 1, 2 are formed wiring layers 3, 4, as the
`interconnection for the semiconductor devices, respectively.
`Through-hole wirings 5, 6, formed in through-holes 14, 15,
`respectively, are electrically connected to these wiring layers
`3, 4, respectively, as in the previous embodiment.
`On the substrates 1 and 2 are deposited insulating layers
`7, 8. The through-hole wirings 5, 6 are formed by charging
`an electrically conductive material in the through-holes 14,
`15 formed in these insulating layers 7, 8, respectively.
`On solely the substrate 2, there is formed the grounding
`wiring layer 10 of e.g., an electrically conductive metal
`material, by layering on the insulating layer 8.
`The grounding wiring layer 10 is formed substantially in
`a continuous pattern except that an opening (through-hole)
`17 connecting to the through-hole 15 formed in the insulat-
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`TSMC 1006
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`IPR of US. Pat. No. 7,485,968
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`TSMC1006
`IPR of U.S. Pat. No. 7,485,968
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`

`

`US 6,465,892 B1
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`7
`ing layer 8 is formed therein substantially in register with the
`through-hole wiring 6.
`Meanwhile, the through-hole 17 is formed so as to be
`slightly larger than the through-hole 15. An insulating mate-
`rial 13 is buried in the gap between the outer periphery of the
`through-hole 17 and the through-hole wiring 6 to assure
`insulation between the grounding wiring layer 10 and the
`through-hole wiring 6.
`As for the opposite side substrate 1, the insulating layer is
`multi-layered and a power source wiring layer 20 is arranged
`between the insulating layers 7, 11.
`In the power source wiring layer 20 and in the insulating
`layer 11, there are formed through-holes 18, 19, respectively.
`A through-hole wiring 5 is passed through these through-
`holes 18, 19. An insulating material 12 is embedded in a gap
`to assure electrical insulation between the power source
`wiring layer 20 and the through-hole wiring 5
`In the above configuration, the through-hole 14 is first
`formed in the substrate 1, using a photolithographic process,
`a film-forming process and a lift-off process. The through-
`hole wiring 5 then is formed in the through-hole 14, using
`the photolithographic process and the lift-off process, as
`shown in FIG. 5. On the insulating layer 7, there are then
`formed the power source wiring layer 20 having the
`through-hole 18 and the insulating layer 1 1, having the
`through-hole 19. In these through-holes 18, 19, the through-
`hole wiring 5 is also formed.
`Between the power source wiring layer 20 and the
`through-hole wiring 5, an insulating material 12 is formed,
`followed by surface polishing.
`through-hole 15,
`Similarly,
`the insulating layer 8,
`through-hole wiring 6 and the grounding wiring layer 10 are
`formed on the substrate 2, followed by surface polishing.
`The substrates 1, 2, thus prepared, are placed in alignment
`with each other so that
`the insulating layer 11 and the
`grounding wiring layer 10 will face each other, and a load is
`imposed from both sides of the substrates 1, 2.
`By the imposed load, the substrates 1, 2 are connected to
`each other, with the through-hole wirings 5, 6 being bonded
`to each other and with the insulating layer 11 and the
`grounding wiring layer 10 being similarly bonded to each
`other.
`
`In each of the above-described configurations, any suit-
`able method for connection to an external driving circuit,
`routinely used in a semiconductor device, may be used.
`For example, it suffices if, in FIG. 7, showing a semicon-
`ductor device comprised of a semiconductor chip A and a
`semiconductor chip B bonded together, the outer size of the
`semiconductor chip Ais set so as to be larger than that of the
`semiconductor chip B, and a connection wire W is wire-
`bonded to a connection pad P exposed on the junction
`surface of the semiconductor chip A. It is noted that the
`structure of the semiconductor device shown in FIG. 7 is
`
`shown in any of FIGS. 2, 4 and 6, and that the semiconductor
`chips A and B are each comprised of a semiconductor
`substrate, with insulating layers and variable wiring layers
`formed thereon, as described above.
`Alternatively, the semiconductor chips A and B may be of
`a substantially equal size and a connection wire W may be
`bonded to a connection pad P formed on the back side of the
`semiconductor chip B. In this case, the pad P needs to be
`electrically connected via a through-hole wiring to a pre-set
`wiring layer of the semiconductor chip B or to a wiring layer
`exposed to the junction surface of the semiconductor chip A.
`The manufacturing method for the semiconductor device
`of the above-described structure is hereinafter explained.
`
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`The manufacturing method exploits solid state bonding.
`The process used therefor may be enumerated by a process
`shown in FIG. 9 and a process shown in FIG. 10.
`FIG. 9 shows an illustrative manufacturing process by
`direct solid state bonding of a heterogeneous device sub-
`strate. In this manufacturing process, a first semiconductor
`substrate 21, such as $01 substrate or a hetero-epi substrate,
`is prepared, as shown in FIG. 9A.
`This semiconductor substrate 21 is formed by layering an
`etching stop layer 21b and a device layer 216 on a silicon
`base 21a. The device layer 216 is etched to a semiconductor
`chip, as shown in FIG. 9B.
`Then, a semiconductor substrate 22, such as a wiring
`substrate carrying an optional wiring, or a heterogeneous
`device substrate, is bonded by solid state bonding on the
`device layer 216, as shown in FIG. 9C.
`The solid state bonding exploits the phenomenon in
`which, if two wafer surfaces approach to each other, stable
`arraying is collapsed to produce interatomic attraction and in
`which,
`if a certain distance is reached,
`the attraction is
`equivalent to that in the bulk to lead ultimately to bonding.
`The solid state bonding has an advantage that there is no
`necessity of using an adhesive nor heating.
`The surface of an actual solid material is stabilized by
`oxidation in case of a metal or by adsorption of an organic
`material. Thus, mere contact is insufficient to produce the
`connection. However, if the stable surface layer is removed
`by collision with inert atoms, such as argon atoms, to expose
`an unstable and active surface, it is possible to realize solid
`state bonding faithfully conforming to the principle of
`bonding.
`in the above-described solid state bonding,
`Therefore,
`smoothing the junction surface and surface activation are
`indispensable.
`FIG. 9D shows the state in which the second semicon-
`ductor substrate 22 is bonded to the first semiconductor
`substrate 21. The silicon base 21a of the first semiconductor
`
`substrate 21 is etched off, as shown in FIG. 9E. An etching
`stop layer 21b then etched off, as shown in FIG. 9F to
`complete a