United States Patent
`
`[191
`
`5,753,536
`May 19, 1998
`Sugiyama et al.
`[45] Date of Patent:
`
`USOOS753536A
`
`[11] Patent Number:
`
`[54] SEMICONDUCTOR DEVICE AND
`ASSOCIATED FABRICATION METHOD
`
`[75]
`
`Inventors: Tatsuo Sugiyama; Shuji Hirao;
`Kousaku Yano. all of Osaka; Noboru
`Nomura. Kyoto, all of Japan
`
`[73] Assignee: Matsushita Electric Industrial Co.,
`Ltd., Osaka, Japan
`
`[21] Appl. No.: 520,252
`
`[22] Filed:
`
`Aug. 28, 1995
`
`[30]
`
`Foreign Application Priority Data
`
`Aug. 29, 1994
`
`[JP]
`
`Japan .................................... 6-203845
`
`Int. Cl;6 ..................................................... H01L 21/60
`[51]
`[52] US. Cl.
`............................................. 438/108; 438/109
`[58] Field of Search ..................................... 438/107. 108,
`438/109. 118, 119
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,754,316
`4,998,665
`5,107,586
`5,270,261
`5,466,634
`5,489,804
`5,567,653
`
`6/1988 Reid .......................................... 357/68
`3/1991 Hayashi
`.................................. 228/180
`4/1992 Eichelberger et a1.
`.
`12/1993 Bertin et al.
`............................ 438/109
`11/1995 Beilstein, Jr. et a1.
`..... 438/109
`
`2/1996 Dasch .....................
`438/108
`10/1996 Bertin et al.
`............................ 438/109
`
`FOREIGN PATENT DOCUlVIENTS
`
`0 270 067
`41 22 297
`2-246368
`2-278849
`6—29456
`6-77101
`WO 91/11833
`
`6/1988
`1/1993
`10/1990
`11/1990
`2/1994
`3/1994
`8/1991
`
`.
`
`European Pat. Oflr'.
`Germany .
`Japan .
`Japan .
`Japan .
`Japan .
`WIPO .
`
`Primary Examiner—Kevin Picardat
`Attorney, Agent, or Firm—McDermott. Will & Emery
`
`[57]
`
`ABSTRACT
`
`A first electrode and a first insulating layer of electrode
`insulation are formed on a first semiconductor substrate. A
`second electrode and a second insulating layer of electrode
`insulation are formed on a second semiconductor substrate.
`
`The first semiconductor substrate has at its surface a pattern
`of recesses/projections (i.e., a pattern of sawteeth in cross
`section) at regular intervals in stripe arrangement. Likewise.
`the second semiconductor substrate has at its surface a
`pattern of recesses/projections (i.e.. a pattern of sawteeth in
`cross section) at regular intervals in stripe arrangement.
`wherein the pattern of the second semiconductor substrate
`has a phase shift of 180 degrees with respect to the pattern
`of the first semiconductor substrate. The first and second
`semiconductor substrates are bonded together with their
`patterns in engagement.
`
`23 Claims, 36 Drawing Sheets
`
`
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`TSMC1005
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`IPR of US. Pat. No. 7,485,968
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`US. Patent
`
`May 19, 1998
`
`Sheet 1 of 36
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`5,753,536
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`FIG/1
`
`
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`US. Patent
`
`May 19, 1998
`
`Sheet 2 of 36
`
`5,753,536
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`US. Patent
`
`May 19, 1998
`
`Sheet 3 of 36
`
`5,753,536
`
`FIG.3(G)
`
`ARGON ION
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`US. Patent
`
`May 19, 1998
`
`Sheet 4 of 36
`
`5,753,536
`
`FIOHG)
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`22
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`US. Patent
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`May 19, 1998
`
`Sheet 5 of 36
`
`5,753,536
`
`FIG.5(Q)
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`US. Patent
`
`May 19, 1998
`
`Sheet 6 of 36
`
`5,753,536
`
`FIG.6(Q)
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`US. Patent
`
`May 19, 1998
`
`Sheet 7 of 36
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`5,753,536
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`FIG.7{G)
`
`FIG.7(b}
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`US. Patent
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`May 19, 1998
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`Sheet 8 of 36
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`5,753,536
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`F I G .8 ( a )
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`US. Patent
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`May 19, 1998
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`Sheet 9 of 36
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`5,753,536
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`US. Patent
`
`May 19, 1998
`
`Sheet 10 of 36
`
`5,753,536
`
`FIG.10(0)
`
`FIG.10(d)
`
`FIG/10M)
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`US. Patent .
`
`May 19, 1998
`
`Sheet 11 of 36
`
`5,753,536
`
`FIG.’|’I( C1)
`
`FIG.1’1(b)
`
`FIG.’H(C)
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`US. Patent
`
`May 19, 1998
`
`Sheet 12 of 36
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`5,753,536
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`FIG.12(G)
`
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`US. Patent
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`May 19, 1998
`
`Sheet 13 of 36
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`5,753,536
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`
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`FIG.’13(C)
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`U.S._ Patent
`
`May 19, 1998
`
`Sheet 14 0f 36
`
`5,753,536
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`US. Patent
`
`May 19, 1998
`
`Sheet 15 of 36
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`5,753,536
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`US. Patent
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`May 19, 1998
`
`Sheet 16 of 36
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`5,753,536
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`US. Patent
`
`May 19, 1998
`
`Sheet 17 of 36
`
`5,753,536
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`US. Patent
`
`May 19, 1998
`
`Sheet 18 0f 36
`
`5,753,536
`
`FIG.18(0)
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`US. Patent
`
`May 19, 1998
`
`Sheet 19 0f 36
`
`5,753,536
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`FIG/19(0) 10
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`US. Patent
`
`May 19, 1998
`
`Sheet 20 of 36
`
`5,753,536
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`FIG.20(d}
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`US. Patent
`
`May 19, 1998
`
`Sheet 21 of 36
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`5,753,536
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`US. Patent
`
`May 19, 1998
`
`Sheet 22 0f 36
`
`5,753,536
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`FIG.22(G)
`
`G.22(b)
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`US. Patent
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`May 19, 1998
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`Sheet 23 of 36
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`5,753,536
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`US. Patent
`
`May 19, 1998
`
`Sheet 24 of 36
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`5,753,536
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`FIOQMG)
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`FIG.24(b)
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`IPR of U.S. Pat. No. 7,485,968
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`US. Patent
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`May 19, 1993
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`Sheet 25 of 36
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`5,753,536
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`
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`US. Patent
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`May 19, 1998
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`Sheet 26 of 36
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`5,753,536
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`
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`FIG.26(b)
`
`FIG.26(C)
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`US. Patent
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`May 19, 1998
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`Sheet 27 0f 36
`
`5,753,536
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`FIG.27(G)
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`US. Patent
`
`May 19, 1998
`
`Sheet 28 of 36
`
`5,753,536
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`[028(a}
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`US. Patent
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`May 19, 1998
`
`Sheet 29 of 36
`
`5,753,536
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`FIOZEHQ}
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`US. Patent
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`May 19, 1998
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`Sheet 30 of 36
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`5,753,536
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`FIG.30{G)
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`US. Patent
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`May 19, 1998
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`Sheet 31 0f 36
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`5,753,536
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`US. Patent
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`May 19, 1993
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`Sheet 32 of 36
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`5,753,536
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`FIG.32(O)
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`FIG.32(b)
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`US. Patent
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`May 19, 1998
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`Sheet 33 of 36
`
`5,753,536
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`FIG.33(C1}
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`PRIOR ART
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`US. Patent
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`May 19, 1998
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`Sheet 34 of 36
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`5,753,536
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`F[ 0.34 (O )
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`US. Patent
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`May 19, 1998
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`Sheet 35 of 36
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`5,753,536
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`I 0.35 I Q)
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`US. Patent
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`May 19, 1998
`
`Sheet 36 of 36
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`5,753,536
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`FIG.36(O)
`PRIOR ART
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`12L
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`‘23
`122
`121
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`FI 0.36 (b)
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`FI 0.36( c)
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`127
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`PRIOR ART
`PRIOR ART
`PRIOR ART
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`FI G.36(<j)
`
`PRIOR ART
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`FI G.36(ea)
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`TSMC1005
`
`IPR of US. Pat. No. 7,485,968
`
`TSMC1005
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`1
`SEMICONDUCTOR DEVICE AND
`ASSOCIATED FABRICATION METHOD
`
`BACKGROUND OF THE INVENTION
`
`This invention relates to a semiconductor device and to an
`associated semiconductor device fabrication method. More
`
`particularly it pertains to a technique of bonding semicon—
`ductor substrates to form a semiconductor device.
`
`Various sophisticated information communicating
`devices have been developed in which high-performance.
`multifunctional LSIs play a key role. Three-dimensional
`(3D) semiconductor devices are now of great interest Vari-
`ous approaches for fabrication of 3D semiconductor devices
`have been proposed (“FED-109 Report on Reaching Effects
`of 3D Circuit Device and Its Future Prospects,” October,
`1991, by New Function Device Research and Development
`Association, Foundation). A 3D semiconductor device,
`formed by laminating two semiconductor substrates with
`their principal surfaces facing each other. has been consid-
`ered most attractive because of its convenience and simplic-
`ity (M. Yasumoto el al., IEDM (1984) pp. 816—820; Hayashi
`el al., Symp. of VLSI Tech. (1990). pp. 95—96).
`A conventional 3D semiconductor device is now
`described below. Referring to FIGS. 33(a)—33(c) and FIGS.
`34(a)—34(c), a conventional bonding technique for bonding
`together semiconductor substrates is illustrated
`FIG. 33(a) shows a fabrication step. First wiring 102 of
`aluminum is formed on a principal surface of first semicon—
`ductor substrate 101 having a semiconductor element. First
`bump 103 of tungsten is selectively formed by means of a
`CVD process. The principal surface of semiconductor sub-
`strate 101 is bonded to supporting material 105 using
`adhesive 104.
`
`A surface of first semiconductor substrate 101 opposite to
`the principal surface is polished (FIG. 33(b)). Thereafter, as
`shown in FIG. 33(c). second wiring 106 of aluminum is
`formed on the surface of first semiconductor substrate 101
`opposite to the principal surface thereof. The surface of first
`semiconductor substrate 101 opposite to the principal sur-
`face thereof is covered with polyimide film 107. An opening
`region is formed in polyimide film 107. Pool electrode 108
`of an alloy of gold and indium is formed in the opening
`region by means of a lift-off process.
`FIG. 34(a) shows a subsequent fabrication step. An align-
`ment step is performed to align the surface of semiconductor
`substrate 101 opposite to the principal surface thereof and a
`principal surface of second semiconductor substrate 110
`having second bump 109 of tungsten. FIG. 34(b) shows a
`fabrication step in which first and second semiconductor
`substrates 101 and 110 are bonded together by application of
`heat.
`
`Next, as shown in FIG. 34(0), supporting material 105 is
`removed to form a 2-leve1 semiconductor device. In this
`2-level semiconductor device. first bump 103, formed on the
`first semiconductor substrate, is utilized as a contact termi-
`nal for providing connection to an external electrode.
`Pool electrode 108 is formed of a gold:indium alloy
`whose melting point is low enough to bond first and second
`semiconductor substrates 101 and 102 without bringing
`second wiring 106 of first semiconductor substrate 101 to a
`meltdown. Additionally. polyimide film 107 guarantees a
`good mechanical strength.
`Referring now to FIGS. 35(a)—(f), the formation of a
`bump is described below.
`Deposited on a surface of semiconductor substrate 111 are
`first silicon oxide layer 112, aluminum layer 113. and second
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`silicon oxide layer 114 (see FIG. 35(a)). A photolithography
`process and a dry etching process are performed to form
`opening region 114a in second silicon oxide layer 114 (see
`FIG. 3S(b)). Thereafter. as shown in FIG. 35(0). tungsten
`115 is embedded into opening region 114a by means of a
`selective CVD process.
`Next. as shown in FIG. 35(d), second sflicon oxide 114 is
`selectively removed by means of an etching process. Semi-
`conductor substrate 111 is then covered with polyimide film
`116 (see FIG. 35(e).
`Next. as shown in FIG. 350‘). an organic solvent is used
`to etch part of polyimide film 116, to form bump 117 of
`tungsten which corresponds to first bump 103 or second
`bump 109 of FIG. 34.
`Referring now to FIGS. 36(a)—(e), the formation of a pool
`electrode is illustrated below.
`
`Silicon oxide layer 122. and wiring 123 of tungsten and
`an aluminum layer are deposited on semiconductor substrate
`121. and semiconductor substrate 121 is coated with poly-
`imide film 124 (see FIG. 36(a)).
`Next, as shown in FIG. 36(b). resist layer 125 is applied
`onto polyimide film 124. A lithography process is performed
`on resist layer 125 to form resist pattern 126 (see FIG.
`36(c)). Thereafter, a dry etching process is carried out using
`resist pattern 126 as an etch mask. to form opening region
`124a in polyimide film 124.
`Next, as shown in FIG. 36(d). alloy layer 127 of gold and
`indium is deposited. whereupon opening region 124a is
`filled up with alloy layer 127. Thereafter. an organic solvent
`is used to lift resist pattern 126 off from alloy layer 127. In
`this way, pool electrode 128 is formed which corresponds to
`pool electrode 108 of FIG. 34.
`Although the above—described prior art bonding technique
`proves to be an adequate method for manufacture of mul-
`tifunctional semiconductor devices. it represents the prob-
`lem that the formation of bump 117 of tungsten and pool
`electrode 128 of a goldzindium alloy requires complicated
`formation processing.
`Additionally the formation of bump 117 and pool elec-
`trode 128 increases the number of fabrication steps, result-
`ing in decreasing the yield of semiconductor device and
`resulting in increasing the cost of semiconductor device
`production.
`Furthermore. in the above-described prior art bonding
`technique, after a semiconductor substrate having semicon-
`ductor elements is bonded to a supporting material, the
`substrate is polished and is removed from the supporting
`material. Due to these steps. the degree of warping becomes
`great when bonded together. This produces the problem that
`good connection cannot be established between semicon-
`ductor substrates to be bonded together.
`Additionally, a step of embedding an alloy of gold and
`indium into an opening region during the pool electrode
`formation is performed by means of a solder reflow process
`or the like, in other words it is hard to embed a fine pattern
`of micron design rules into an opening region.
`SUMMARY OF THE INVENTION
`
`Bearing in mind the above-noted problems with the prior
`art techniques, this invention was made. Therefore. an object
`of this invention is to provide a semiconductor device
`fabrication method capable of reducing the number of steps
`required in bonding semiconductor substrates and capable of
`reducing the degree of post-bonding warping to improve the
`reliability of interconnection between semiconductor ele-
`
`TSMC1005
`
`IPR of US. Pat. No. 7,485,968
`
`TSMC1005
`IPR of U.S. Pat. No. 7,485,968
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`

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`5,753,536
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`3
`ments. Another object of this invention is to provide semi-
`conductor devices having fine—patterned opening regions.
`The present invention shows a first semiconductor device
`comprising:
`(a) a first semiconductor substrate having:
`a first semiconductor element which is formed on said
`first semiconductor substrate;
`a plurality of first electrodes which are formed on a
`principal surface of said first semiconductor substrate
`and which are electrically connected to said first semi—
`conductor element;
`a first insulating layer which is formed on the principal
`surface of said first semiconductor substrate and which
`insulates said plurality of first electrodes; and
`a plurality of projections which are formed on said
`plurality of first electrodes as well as on said first
`insulating layer;
`(b) a second semiconductor substrate having:
`a second semiconductor element which is formed on said
`second semiconductor substrate;
`a plurality of second electrodes which are formed on a
`principal surface of said second semiconductor sub-
`strate wherein said plurality of second electrodes cor-
`respond in position to said plurality of first electrodes,
`and which are electrically connected to said second
`semiconductor element;
`a second insulating layer which is formed on the principal
`surface of said second semiconductor substrate and
`which insulates said plurality of second electrodes; and
`a plurality of recesses which are formed on said plurality
`of second electrodes as well as on said second insulat—
`
`ing layer wherein said plurality of recesses correspond
`in position to said plurality of projections;
`wherein:
`said first semiconductor substrate and said second semi—
`conductor substrate are bonded together by bringing
`said plurality of projections and said plurality of
`recesses into engagement with one another.
`In the first semiconductor device. the first and second
`semiconductor substrates are bonded together by bringing
`the projections of the first semiconductor substrate and the
`recesses of the second semiconductor substrate into engage-
`ment with one another. This provides a greater contact area
`between the substrates thereby bonding them with a greater
`bonding strength.
`In the first semiconductor device, it is preferable that the
`projections of the first semiconductor substrate and the
`recesses of the second semiconductor substrate are formed
`in such away as to have one— or two-dimensionally the same
`pattern. This increases the number of projections and the
`number of recesses therefore increasing the number of
`bonding points. The first and second semiconductor sub-
`strates are bonded together with a much greater bonding
`strength.
`This invention shows a first method of fabricating a
`semiconductor device comprising:
`(a) a first step of:
`forming, on a principal surface of a first semiconductor
`substrate having a first semiconductor element. a plu—
`rality of first electrodes which are electrically con—
`nected to said first semiconductor element;
`forming, on the principal surface of said first semicon-
`ductor substrate. a first insulating layer for insulating
`said plurality of first electrodes;
`forming. on a principal surface of a second semiconductor
`substrate having a second semiconductor element. a
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`plurality of second electrodes which are electrically
`connected to said second semiconductor element
`wherein said plurality of second electrodes correspond
`in position to said plurality of first electrodes; and
`forming. on the principal surface of said second semicon-
`ductor substrate a second insulating layer for insulat—
`ing said plurality of second electrodes;
`(b) a second step of:
`etching said plurality of first electrodes and said first
`insulating layer of said first semiconductor substrate to
`form a plurality of projections; and
`etching said plurality of second electrodes and said sec—
`ond insulating layer of said second semiconductor
`substrate to form a plurality of recesses wherein said
`plurality of recesses correspond in position to said
`plurality of projections; and
`(c) a third step of:
`bonding said first semiconductor substrate and said sec-
`ond semiconductor substrate by bringing said plurality
`of projections and said plurality of recesses into
`engagement with each other.
`In accordance with the first semiconductor device fabri-
`
`cation method. a plurality of projections and a plurality of
`recesses are formed by means of an etching process. and
`these projections and recesses are brought into engagement.
`This not only eliminates the need for forming bump elec-
`trodes and pool electrode required in conventional semicon-
`ductor devices but also enables the first and second semi-
`conductor substrates to be aligned with each other
`automatically. This method. therefore. can bond semicon-
`ductor substrates at a great bonding strength to form a
`semiconductor device.
`in a simple way and with a less
`number of steps in comparison with a conventional semi—
`conductor device fabrication method.
`
`In the first semiconductor fabrication method. it is pref—
`erable that the second step includes:
`forming. on the first electrodes and on the first insulating
`layer, a first resist pattern. and thereafter etching the
`first electrodes and the first insulating layer to form the
`projections by making use of the first resist pattern as
`an etch mask;
`forming. on the second electrodes and on the second
`insulating layer, a second resist pattern in inverting
`relationship with respect to the first resist pattern and
`thereafter etching the second electrodes and the second
`insulating layer to form the recesses by making use of
`the second resist pattern as an etch mask.
`Since projections and recesses are formed by making use
`of the first and second resist patterns in inverting
`relationship. this simplifies a way of forming projections and
`recesses.
`
`This invention provides a second method of fabricating a
`semiconductor device comprising:
`(a) a first step of:
`forming, on a principal surface of a first semiconductor
`substrate having a first semiconductor element, a plu-
`rality of first electrodes which are electrically con—
`nected to said first semiconductor element;
`forming, on the principal surface of said first semicon-
`ductor substrate, a first insulating layer for insulating
`said plurality of first electrodes;
`forming. on a principal surface of a second semiconductor
`substrate having a second semiconductor element. a
`plurality of second electrodes which are electrically
`connected to said second semiconductor element
`wherein said plurality of second electrodes correspond
`in position to said plurality of first electrodes;
`
`TSMClOOS
`
`IPR of U.S. Pat. No. 7,485,968
`
`TSMC1005
`IPR of U.S. Pat. No. 7,485,968
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`forming. on the principal surface of said second semicon-
`ductor substrate. a second insulating layer for insulat-
`ing said plurality of second electrodes;
`(b) a second step of:
`planarizing said plurality of first electrodes and said first
`insulating layer; and
`planarizing said plurality of second electrodes and said
`second insulating layer;
`(c) a third step of:
`aligning said first semiconductor substrate and said sec-
`ond semiconductor substrate such that said plurality of
`first electrodes and said plurality of second electrodes
`face one another; and
`(d) a fourth step of:
`press bonding said first semiconductor substrate and said
`second semiconductor substrate.
`In accordance with the second semiconductor device
`fabrication method. the first semiconductor substrate and the
`second semiconductor substrate have plauarized surfaces
`that are brought in contact with each other when these
`substrates are bonded together. This guarantees that the first
`and second semiconductor substrates contact with each
`other. This method. therefore. can bond semiconductor sub-
`strates at a great bonding strength to form a semiconductor
`device, in a simple way and with a less number of steps in
`comparison with a conventional semiconductor device fab-
`rication method.
`In the second semiconductor device fabrication method. it
`is preferable that the second method further comprises
`forming a molecular layer having dangling bonds on the first
`electrodes and on the first insulating layer wherein the
`aforesaid molecular layer forming step is carried out
`between the second and third steps. and that the fourth step
`includes bonding the first semiconductor substrate and the
`second semiconductor substrate by means of chernisorption
`of the dangling bonds to the second electrodes and the
`second insulating layer.
`Because of such chemisorption the first and second semi-
`conductor substrates are bonded together at a greater bond-
`ing strength.
`In the second semiconductor device fabrication method. it
`is preferable that the third step includes aligning the first
`semiconductor substrate and the second semiconductor sub—
`strate in a liquid.
`Because of such arrangement. the first and second semi-
`conductor substrates are brought into contact with each other
`while a liquid trapped between these two substrates is forced
`out. in other words a liquid exists between the first and
`second semiconductor substrates until they have come to
`contact with each other. This not only straightens the warp-
`ing of the first semiconductor substrate as well as the
`warping of the second semiconductor substrate but also
`prevents a sudden contact of the first semiconductor sub—
`strate with the second semiconductor substrate. in other
`words their surfaces are not damaged by contact.
`In the second semiconductor device fabrication method. it
`is preferable that the third step includes:
`forming. on the principal surface of the first semiconduc-
`tor substrate. a first resist pattern. and thereafter etching
`the first semiconductor substrate to form a recess of
`alignment by making use of the first resist pattern as an
`etch mask;
`forming, on the principal surface of the second sernicon—
`ductor substrate. a second resist pattern in inverting
`relationship with respect to the first resist pattern;
`aligning the first semiconductor substrate and the second
`semiconductor substrate such that the recess and the
`second resist pattern are brought into engagement with
`each other.
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`The first and second semiconductor substrates are aligned
`with each other by bringing the alignment recess formed in
`the first semiconductor substrate by means of an etching
`process using the first resist pattern as an etch mask and the
`inverting second resist pattern into engagement. This guar-
`antees that the first and second semiconductor substrates are
`correctly aligned with each other.
`In the second semiconductor device fabrication method. it
`is preferable that the fourth step includes:
`holding the first semiconductor substrate and the second
`semiconductor substrate in alignment
`in a vacuum
`atmosphere;
`applying a pressure by gas against at least one of surfaces
`of the first and second semiconductor substrates oppo—
`site to the principal surfaces thereof.
`As a result of such arrangement. the first semiconductor
`substrate is aligned with the second semiconductor substrate
`in a vacuum atmosphere. whereupon the first and second
`semiconductor substrates are bonded close to each other.
`Thereafter. at least one of the opposite surfaces of the first
`and second semiconductor substrates is pressed using gas.
`whereupon the first and second electrodes are bonded
`together sharing electrons. This enables the first and second
`semiconductor substrates to be bonded together at a greater
`bonding strength.
`In the second semiconductor device fabrication method. it
`is preferable that the fourth step includes press-bonding the
`first and second semiconductor substrates in alignment while
`applying heat to the first and second semiconductor sub-
`strates. This enables the first and second semiconductor
`
`substrates to be bonded together at a greater bonding
`strength.
`In the second semiconductor device fabrication method. it
`is preferable that the first semiconductor substrate of the first
`step is transparent and has thereon an alignment mark. and
`that the second method further comprises a fifth step of:
`etching. with the aid of the alignment mark. a surface of
`the first semiconductor substrate bonded at the fourth
`step to the second semiconductor substrate opposite to
`the principal surface thereof. to form an opening region
`extending to a conductive layer which is formed in the
`first semiconductor substrate and which is electrically
`connected to the first electrode; and
`filling up the opening region with a metallic material. to
`form on the first semiconductor substrate an extraction
`electrode that is electrically connected to an external
`electrode.
`
`As a result of such arrangement. a semiconductor device
`formed by bonding semiconductor substrates can be accom-
`plished which is capable of easily being connected to an
`external electrode.
`In the second semiconductor device fabrication method. it
`is preferable that the first step includes forming a first
`metallic layer that is embedded in the first insulating layer
`and forming a second metallic layer that is embedded in the
`second insulating layer wherein the second metallic layer
`corresponds in position to the first metallic layer. and that the
`second step includes planarizing the first insulating layer
`with the first metallic layer embedded therein and planariz—
`ing the second insulating layer with the second metallic
`layer embedded therein, and that the fourth step includes
`bonding the first metallic layer and the second metallic layer.
`As a result of such arrangement. the first metallic layer
`embedded in the first insulating layer and the second metal-
`lic layer embedded in the second insulating layer are bonded
`together. This increases the number of bonding portions
`between the first and second semiconductor substrates
`
`TSMClOOS
`
`IPR of US. Pat. No. 7,485,968
`
`TSMC1005
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`5,753,536
`
`7
`thereby enabling the first and second semiconductor sub-
`strates to be bonded together at a greater bonding strength.
`This invention shows a third method of fabricating a
`semiconductor device comprising:
`(a) a first step of:
`forming, on a principal surface of a first semiconductor
`substrate having a first semiconductor element. a first
`interconnect line that is electrically connected to said
`first semiconductor element; and
`forming. on a principal surface of a second semiconductor
`substrate having a second semiconductor element. a
`second interconnect line that is electrically connected
`to said second semiconductor element;
`(b) a second step of:
`forming, on the principal surface of said first semicon-
`ductor substrate having said first interconnect line. a
`first interlayer insulating film having therein a first
`opening region wherein said first opening region cor-
`responds in position to said first interconnect line;
`forming, on the principal surface of said second semicon—
`ductor substrate having said second interconnect line, a
`second interlayer insulating film having therein a sec-
`ond opening region wherein said second opening
`region corresponds in position to said second intercon-
`nect lin