Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`
`Richard A. Blanchard, Ph.D.
`
`
`
`Expertise
`
` MOS and Bipolar Device Technology
` Semiconductor Device Physics
` Microchip Fabrication & Analysis
` Electronic Systems
` Electrical & Electronic Failures
` ESD & EOS Failures
` Assembly & Packages
`
`
`
`
` CMOS, DMOS & BiCMOS Technology
` Power IC’s & Power Electronics
` Printed Circuit Board Manufacturing
` Printable Electronics, including LEDs
` Semiconductor Process & Control
` Patents & Trade Secrets
`
`Integrated circuit technology
`
`
`Professional Summary
`
`Dr. Blanchard has over 40 years of combined industry, research, academic, and consulting
`experience. His research covers semiconductor device and electronics design, semiconductor
`device physics, semiconductor manufacturing processes and equipment, failure analysis, and
`reverse engineering of semiconductor devices and electronic circuits. Dr. Blanchard is a
`named inventor on more than 170 issued U.S. patents. As a result, he has been involved in
`numerous patent and trade secret litigation matters including a number of ITC proceedings. He
`has also authored or co-authored books and articles dealing with semiconductor design, process
`development, and failure analysis.
`
`Employment History
`
`From:
`
`Blanchard Associates
`
`To:
`
`
`
`
`
`
`
`1991,
`2008-
`Los Altos, CA
`Present
`Position: 2008-Present: Industry Consultant and Expert Witness
`
`Blanchard Associates specializes in working with both start-ups and
`established companies in the development of new products as well as
`intellectual property. His projects have included the development of
`improved low voltage and high voltage MOS-gated devices and the
`development of printable electronics such as LEDs and discrete
`transistors. This work has included the identification of patentable
`material and work to protect this material. He is also an Exclusive
`Expert for SVEWG.
`
`
`
`
`
`Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 1
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`1998
`Silicon Valley Expert Witness Group, Inc.
`Mountain View, CA
`2007
`Position: Exclusive Expert and Consultant
`
`Silicon Valley Expert Witness Group, Inc. (SVEWG) is a high
`technology, “Silicon Valley” consulting company specializing in
`expert witness litigation support and technology consulting. SVEWG
`has an extensive roster of world-class technology experts used in the
`defense and promotion of intellectual property rights and other
`litigation disputes. SVEWG Principals offer extensive in-house
`technology, legal and business expertise and have direct access to
`senior litigation and technology consultants worldwide.
`
`1991
`Failure Analysis Associates, Inc. (Now named “Exponent”)
`Menlo Park, CA
`1998
`Position: Principal Engineer & Division Manager
`
`Responsible for the Electrical/Electronic Division of Failure
`Analysis Associates providing consulting services to the electrical
`and electronics industry. Specific duties include:
` Semiconductor devices. Failure analysis and reverse engineering
`of solid-state electronic components and circuits. Semiconductor
`processing and semiconductor process equipment.
`Semiconductor manufacturing and process control.
` Failure analysis of electric and electronic systems, subsystems,
`and components, including causes of electrical fires
` Reliability modeling and lifetime prediction of electrical and
`electronic systems and subsystems
` Automotive electronics. Design of discrete devices and
`integrated circuits
` Power Electronics. Power MOS and Smart Power Technologies
`
`1987
`IXYS Corporation
` San Jose, CA
`1991
`Position: Senior Vice President
`
`Responsible for the development of IC products. Established an in-
`house CAD capability. Recruited an IC design team and
`coordinated the definition and development of IXYS ICs. Identified,
`qualified and monitored the IC foundries that manufactured these
`circuits. Set up testing capability at IXYS. Coordinated assembly on
`IC’s. Worked on various MOSFET and IGBT device, test, and
`assembly problems.
`
`1982
`Siliconix, Inc.
` Santa Clara, CA
`1987
`Position: Vice President, Engineering
`
`From:
`To:
`
`
`
`
`From:
`To:
`
`
`
`
`From:
`To:
`
`
`
`
`From:
`To:
`
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 2
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`
`
`
`
`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`Other titles held at Siliconix, Inc. were Engineering Manager (1982-
`1983) and Director (1983-1984). Responsible for the development
`of advanced process technology and the design of both discrete
`devices (JFETs, lateral and vertical DMOS transistors) and
`integrated circuits (low and high voltage CMOS, D/CMOS and
`bipolar-JFET). Personally responsible for many key innovations and
`inventions in power MOS and D/CMOS IC technology and their
`assembly and test requirements. He submitted approximately 20
`patent disclosures while employed at Siliconix, Inc. He holds the
`two key “trench FET” patents, of which he is the sole inventor.
`
`
`From:
`To:
`
`
`
`
`From:
`To:
`
`
`
`
`From:
`To:
`
`
`
`
`1976
`Supertex, Inc.
` Sunnyvale, CA
`1982
`Position: Founder and Vice President, MOS Power Products
`
`Responsible for investigation of new semiconductor devices and
`new technologies. In charge of Power MOS device research, design
`and development. His work lead to the design and development of
`both the discrete power MOS device family and the high voltage IC
`(HVIC) family sold by Supertex, Inc. Responsible for an in-house
`assembly area as well as engineering aspects of power MOS and
`HVIC testing.
`
`1976
`Cognition, Inc.
` Mountain View, CA
`1978
`Position: Founder and Consulting Engineer
`
`Responsible for developing the process technology for fabricating
`monolithic silicon pressure sensors. A process line was established
`for the manufacture of piezoresistive pressure sensors, including the
`precision etching of thin silicon diaphragms.
`
`
`
`1974
`Foothill College
` Los Altos Hills, CA
`1978
`Position: Associate Professor, Assistant Division Chairman, Engineering &
`Technology Division
`Accomplishments included developing the curriculum for the
`Semiconductor Technology Program, and establishing a small
`processing facility for teaching students the fundamentals of
`semiconductor technology. Supervised approximately 60 instructors
`in the evening and off-campus programs.
`
`
`From:
`To:
`
`
`1974
`1976
`Duties:
`
`Independent Consultant
` Los Altos Hills, CA
`Consultant to the semiconductor industry, including court appointed
`“Special Master” in the Fairchild Semiconductor Corporation v.
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 3
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`National Semiconductor Corporation Isoplanar patent suit.
`
`
`From:
`To:
`
`
`
`1970
`Fairchild Semiconductor
`Mountain View, CA
`1974
`Position: Senior Engineer, Department Manager
`
`Responsible for the fabrication of the integrated circuits in the
`Polaroid SX-70 camera. Technologies directly related to this work
`include standard bipolar technology, bipolar- MOS technology,
`silicon gate technology and flip-chip assembly technology.
`
`
`Deposition and Trial Testimony (Past Five Years)
`
`Anthony Bookhamer, Lena J. Tyron, Charles Thomas Martin, Jr., and Carl Disilvestro v.
`Sunbeam Products, Inc., United States District Court, Northern District of California, Civil
`Action No. 09-CV-06027 EMC (DMR).
`
`Kentucky Farm Bureau Mutual Insurance Company v. Sunbeam Products, Inc., United States
`District Court, Western District of Kentucky, Paducah Division, Civil Action No. 5:11-CV-
`0098-R. (R, D)
`
`Osram v. LG Electronics, United States International Trade Commission, Washington, DC, In
`the matter of Certain light-Emitting Diodes and Products Containing the Same, Investigation
`No. 337-TA-784. (D, R, T)
`
`Thomas Post; Debra Ferguson, Bobbie Haskett, Michael Post, Laura Zedaker, and Margie
`Zervos v. Sunbeam Products, Inc., United States District Court, Eastern District of California,
`Case No. 2:11-CV-00792-JAM-CMK. (R, D)
`
`Osram v. LG Electronics/Samsung, United States International Trade Commission,
`Washington, DC, in the matter of Certain Light-Emitting Diodes and Products Containing the
`Same, Investigation No. 337-TA-785. (D, R, Tutorial)
`
`Nationwide Mutual Insurance Company v. Mack Wallbed Systems, in the Superior Court of the
`State of California, County of Sonoma, Case No. SCV-247147. (D, T)
`
`Richtek v. uPI, et al., In the matter of Certain DC-DC Controllers and Products Containing
`Them, International Trade Commission, Washington, DC, Case No. 337-TA-698. (D, R, T)
`
`Quality Investment Properties Santa Clara, Inc. v. Serrano Electric, Inc. and Peterson Power
`Systems, Inc., and Serrano Electric, Inc. (Cross-Claimant) v. Peterson Power Systems, Inc.
`(Cross-Defendant), United States District Court, Case No. 5:09-CV-05376LHK. (D, R)
`
`Michael J. Anderson and Deborah M. Anderson v. Sunbeam Products, Inc., Supreme Court of
`the State of New York County of Oswego, Case No. 08-2230. (D, R)
`
`Security Mutual Insurance, et al. v. Sunbeam Products, Inc. et al., United States District Court
`Northern District of New York, Civil Action No.: 5:09-CV-0460. (D, R)
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 4
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`
`
`Coorstek, Inc. v. Steven F. Reiber and Mary L. Reiber, United States District Court, District of
`Colorado, Case No. 08-CV-01133-KMT-CBS. (D, R, Tutorial)
`
`Nationwide Mutual Fire Insurance Company, as subrogee of Mildred Harrop v. Sunbeam
`Products, Inc., United States District Court, District of Rhode Island, C.A. No. 09-509/S. (D, R)
`
`Kay A. Reed and Charlie Wear, Trust Administrators for the Vornado Liquidating Trust v. Tyco
`Electronics Corporation, Global Wire Technologies of Indiana, Inc. GWT Investments, Inc. and
`Unicable, Inc., Superior Court of California, Case No. CGC-05-441279. (D, T)
`
`Jeffery Quist, as Trustee for the heirs and next of kin of Jerald Quist, Deceased, and Virginia
`Quist v. Sunbeam Products, Inc., d/b/a Jarden Consumer Solutions. (D, R)
`
`Barbara Kay and James Kay v. Sunbeam Products, Inc., United States District Court, Western
`District of Missouri, Central Division, Case No. 2:09CV-4065-NKL. (D, R, T)
`
`Tessera, Inc. v. United Test and Assembly Center, LTD and UTAC America, Inc., Superior
`Court of California, County of Alameda, Case No. RG08410327. (D)
`
`Sun Yen v. Volkswagen Group of America, Inc., Superior Court of California, County of
`Alameda, Case No. RG08416335. (D)
`
`LG Display Co., Ltd. v. Chi Mei Optoelectronics Corporation, AU Optronics Corporation, AU
`Optronics Corporation of America: Tatung Company, Tatung Company of America, Inc. and
`Viewsonic Corporation, United States District Court, District of Delaware, Civil Action No. 06-
`726 (JJF). (D, R)
`
`Safeco Insurance Company of Illinois v. BSH Home Appliances Corporation and Chun Yuen
`Ng, Superior Court of California, County of San Francisco, Case No. 060-08-471246. (D)
`
`Olivia Evans, et al. v. G3 Energy, LLC, et al., Alameda County Superior Court Case No.: VG-
`05-218563. (D)
`
`State Farm Fire and Casualty Co., as Subrogee of Benjamin Parr and June Parr, and Benjamin
`Parr and June Parr, Individually v. Sunbeam Products, Inc., United States District Court, Central
`District, Peoria Division, Case No. 1:06-CV-01208. (D, R, T)
`
`Safeco Insurance v. Eaton Electrical, Inc., et al., Marin Superior Court, Case No. 60820. (D)
`
`Quantum Research Group v. Apple Computer Company, Inc., Cypress Semiconductor Corp.,
`Cypress Microsystems, and Fingerworks, Inc., Unites States District of Maryland, Civil Action
`No. 1:05-CV-03408-WMN. (D, R)
`
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 5
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`Nathan J. Sheridan v. Fladeboe Volkswagen, Inc., Volkswagen of America, Inc., Superior Court
`of the State of California for the County of Orange, Case No. 06CC09510. (D, T)
`
`Underlined Party Indicates Provided: Deposition (D), Report (R), or Testimony in Court (T)
`
`Patents
`
`Patent Number
`
`Date Filed
`
`Title
`
`8,456,393
`
`8,456,392
`
`8,450,795
`8,415,879
`8,395,568
`8,390,060
`8,384,630
`8,354,711
`8,330,217
`
`8,330,213
`
`8,319,278
`8,310,006
`
`8,193,565
`8,133,768
`
`8,049,271
`
`7,989,293
`7,825,492
`
`7,745,885
`7,736,976
`
`7,705,397
`
`7,704,842
`
`7,586,165
`7,586,148
`
`7,557,394
`7,544,544
`7,535,041
`
`9/15/2009
`
`9/15/2009
`
`8/11/2008
`8/21/2011
`9/15/2009
`4/26/2012
`9/15/2009
`6/11/2010
`12/11/2012
`
`12/11/2012
`
`3/10/2010
`9/21/2010
`
`Method of Manufacturing a Light Emitting, Photovoltaic or other Electronic
`Apparatus and System
`Method of Manufacturing a Light Emitting, Photovoltaic or other Electronic
`Apparatus and System
`Technique for Forming the Deep Doped Columns in Superjunction
`Diode for Printable Composition
`Light Emitting, Photovoltaic or other Electronic Apparatus and System
`Power Semiconductor Devices, Structures, and Related Methods
`Light Emitting Photovoltaic or other Electronic Apparatus and System
`Power MOSFET and its Edge Termination
`Devices, Methods, and Systems with MOS-Gated Trench-to-Trench Lateral,
`Current Flow
`Power Semiconductor Devices, Methods, and Structures with Embedded
`Dielectric Layers Containing Permanent Charges
`Power Device Structures and Methods Using Empty Space Zones
`Devices, Structures, and Methods using Self-aligned Resistive Source
`Extensions
`Multi-level Lateral Floating Coupled Capacitor Transistor Structures
`Method of Manufacturing a Light Emitting Photovoltaic or Other Electronic
`Apparatus and System
`Power Semiconductor Device Having a Voltage Sustaining Layer with a
`Terraced Trench Formation of Floating Islands
`Trench Device Structure and Fabrication
`Isolated Vertical Power Device Structure with Both N-Doped and P-Doped
`Trenches
`High Voltage Power MOSFET Having Low On-Resistance
`06/29/2010
`06/15/2010 Method for Fabricating a Power Semiconductor Device Having a Voltage
`Sustaining Layer with a Terraced Trench Facilitating Formation of Floating
`Islands
`Devices, Methods, and Systems with MOS-Gated Trench-to-Trench Lateral
`Current Flow
`Lateral High-Voltage Transistor with Vertically-Extended Voltage-Equalized
`Drift Region
`09/08/2009 Microelectromechanical Systems (MEMS) Device Including a Superlattice
`09/08/2009
`Power Semiconductor Device Having a Voltage Sustaining Region that
`Includes Doped Columns Formed by Terraced Trenches
`High-Voltage Transistor Fabrication with Trench Etching Technique
`07/07/2009
`Low Capacitance Two-Terminal Barrier Controlled TVS Diodes
`06/09/2009
`05/19/2009 Method for Making a Semiconductor Device Including Regions of Band-
`
`4/17/2009
`03/13/2012
`
`11/01/2011
`
`08/02/2011
`11/02/2010
`
`04/27/2010
`
`04/27/2010
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 6
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`05/12/2009
`
`05/12/2009
`
`03/17/2009
`01/06/2009
`10/28/2008
`
`08/12/2008
`
`07/08/2008
`
`07/17/2007
`05/29/2007
`
`04/10/2007
`04/03/2007
`11/21/2006
`08/22/2006
`
`08/15/2006
`
`08/01/2006
`
`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`Engineered Semiconductor Superlattice to Reduce Device-On Resistance
`Semiconductor Device Including a Memory Cell with a Negative Differential
`Resistance (NDR) Device
`Semiconductor Device Including Regions of Band-Engineered
`Semiconductor Superlattice to Reduce Device-On Resistance
`Technique for Forming the Deep Doped Regions in Superjunction Devices
`Oxide-Bypassed Lateral High Voltage Structures and Methods
`Isolated Vertical Power Device Structure with Both N-Doped and P-Doped
`Trenches
`Lateral High-Voltage Transistor with Vertically-Extended Voltage-Equalized
`Drift Region
`Integrated Released Beam Layer Structure Fabricated in Trenches and
`Manufacturing Method Thereof
`Semiconductor Having Thick Dielectric Regions
`03/04/2008
`12/04/2007 Method for Fabricating a Power Semiconductor Device Having a Voltage
`Sustaining Layer with a Terraced Trench Facilitating Formation of Floating
`Islands
`Low Capacitance Two-Terminal Barrier Controlled TVS Diodes
`High Voltage Power MOSFET Having a Voltage Sustaining Region that
`Includes Doped Columns Formed by Trench Etching and Diffusion from
`Regions of Oppositely Doped Polysilicon
`FinFET Including a Superlattice
`DMOS Device with a Programmable Threshold Voltage
`Technique for Fabricating Multilayer Color Sensing Photodetectors
`Fabrication on Diaphragms and “Floating” Regions of Single Crystal
`Semiconductor for MEMS Devices
`High Voltage Power MOSFET Having a Voltage Sustaining Region that
`Includes Doped Columns Formed by Trench Etching and Ion Implantation
`Power Semiconductor Device Having a Voltage Sustaining Region that
`Includes Terraced Trench with Continuous Doped Columns Formed in an
`Epitaxial Layer
`High Voltage power MOSFET Having Low On-Resistance
`06/27/2006
`Integrated Circuit Inductors Using Driven Shields
`06/13/2006
`04/04/2006 Method for Forming Thick Dielectric Regions Using Etched Trenches
`03/28/2006
`High Voltage Power MOSFET Having a Voltage Sustaining Region that
`Includes Doped Columns Formed by Trench Etching Using an Etchant Gas
`that is also a Doping Source
`Technique for Forming the Deep Doped Columns in Superjunction
`High Voltage Power MOSFET Having Low On-Resistance
`Trench DMOS Transistor Structure Having a Low Resistance Path to a Drain
`Contact Located on an Upper Surface
`Double Diffused Field Effect Transistor Having Reduced On-Resistance
`07/26/2005
`Capacitive Sensor Device With Electrically Configurable Pixels
`06/14/2005
`DMOS Device with a Programmable Threshold Voltage
`04/19/2005
`03/01/2005 Method for Using a Surface Geometry for a MOS-Gated Device in the
`Manufacture of Dice Having Different Sizes
`Trench DMOS Transistor Structure Having a Low Resistance Path to a Drain
`Contact Located on an Upper Surface
`
`03/21/2006
`01/31/2006
`09/27/2005
`
`11/02/2004
`
`7,531,850
`
`7,531,829
`
`7,504,305
`7,473,966
`7,442,584
`
`7,411,249
`
`7,397,097
`
`7,339,252
`7,304,347
`
`7,244,970
`7,224,027
`
`7,202,494
`7,199,427
`7,138,289
`7,094,621
`
`7,091,552
`
`7,084,455
`
`7,067,376
`7,061,072
`7,023,069
`7,019,360
`
`7,015,104
`6,992,350
`6,949,432
`
`6,921,938
`6,906,529
`6,882,573
`6,861,337
`
`6,812,526
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 7
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`Technique for Fabricating MEMS Devices Having Diaphragms of “Floating”
`Regions of Single Crystal Material
`09/21/2004 Method of Making a Power Semiconductor Device
`09/14/2004
`Fabrication of Dielectrically Isolated Regions of Silicon in a Substrate
`08/17/2004
`Symmetric Trench MOSFET Device and Method of Making Same
`06/15/2004
`Photodiode Stacks for Photovoltaic Relays and the Method of Manufacturing
`the Same
`High Voltage Power MOSFET Having a Voltage Sustaining Region that
`Includes Doped Columns Formed by Trench Etching Using an Etchant Gas
`that is also a Doping Source
`Two Terminal Programmable MOS-Gated Current Source
`05/11/2004
`05/04/2004 Minimum Sized Cellular MOS-Gated Device Geometry
`04/20/2004 MOSFET Device Having Geometry that Permits Frequent Body Contact
`04/20/2004
`Semiconductor Device Having a Schottky Diode
`03/30/2004
`Double Diffused Field Effect Transistor Having Reduced On-Resistance
`03/23/2004
`Surface Geometry for a MOS-Gated Device that Allows the Manufacture of
`Dice Having Different Sizes
`03/23/2004 Method for Fabricating a High Voltage Power MOSFET Having a Voltage
`Sustaining Region that Includes Doped Columns Formed by Rapid Diffusion
`02/10/2004 Method of Forming a High Voltage Power MOSFET Having Low On-
`Resistance
`Power Semiconductor Device Having a Voltage Sustaining Region that
`Includes Doped Columns Formed with a Single Ion Implantation Step
`High Voltage Power MOSFET Having Low On-Resistance
`High Voltage Power MOSFET Having a Voltage Sustaining Region that
`Includes Doped Columns Formed by Trench Etching and Ion Implantation
`11/18/2003 Method for Fabricating a Power Semiconductor Device Having a Voltage
`Sustaining Layer with a Terraced Trench Facilitating Formation of Floating
`Islands
`High Voltage Power MOSFET Having Low On-Resistance
`09/30/2003
`09/23/2003 Method for Fabricating a Power Semiconductor Device Having a Floating
`Island Voltage Sustaining Layer
`Trench DMOS Transistor with Embedded Trench Schottky Rectifier
`High Voltage Power MOSFET Having Low On-Resistance
`Field Effect Transistor Having Dielectrically Isolated Sources and Drains and
`Method for Making Same
`High Voltage Power MOSFET Having a Voltage Sustaining Region that
`Includes Doped Columns Formed by Trench Etching and Diffusion from
`Regions of Oppositely Doped Polysilicon
`05/20/2003 Method for Fabricating a High Voltage Power MOSFET Having a Voltage
`Sustaining Region that Includes Doped Columns Formed by Rapid Diffusion
`High-Side Switch with Depletion-Mode Device
`03/25/2003
`Universal Source Geometry for MOS-Gated Power Devices
`12/10/2002
`11/12/2002 Method of Fabricating High Voltage Power MOSFET Having Low On-
`Resistance
`Trench DMOS Transistor Structure Having a Low Resistance Path to a Drain
`Contact Located on an Upper Surface
`Single Feature Size MOS Technology Power Device
`
`10/29/2002
`
`10/22/2002
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 8
`
`11/02/2004
`
`06/15/2004
`
`02/03/2004
`
`12/09/2003
`12/02/2003
`
`09/16/2003
`07/15/2003
`07/15/2003
`
`06/10/2003
`
`6,812,056
`
`6,794,251
`6,790,745
`6,777,745
`6,750,523
`
`6,750,104
`
`6,734,495
`6,730,963
`6,724,044
`6,724,039
`6,713,351
`6,710,414
`
`6,710,400
`
`6,689,662
`
`6,686,244
`
`6,660,571
`6,656,797
`
`6,649,477
`
`6,627,949
`6,624,494
`
`6,621,107
`6,593,619
`6,593,174
`
`6,576,516
`
`6,566,201
`
`6,538,279
`6,492,663
`6,479,352
`
`6,472,709
`
`6,468,866
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`08/13/2002
`
`07/16/2002
`
`06/11/2002
`
`06/04/2002
`
`05/29/2001
`05/01/2001
`04/10/2001
`
`03/06/2001
`
`05/30/2000
`05/16/2000
`
`04/04/2000
`
`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`10/15/2002 Method for Fabricating a Power Semiconductor Device Having a Floating
`Island Voltage Sustaining Layer
`Trench DMOS Transistor Structure Having a Low Resistance Path to a Drain
`Contact Located on an Upper Surface
`Field Effect Transitor (sic. Transistor) Having Dielectrically Isolated Sources
`and Drains and Methods for Making Same
`Field Effect Transistor Having Dielectrically Isolated Sources and Drains and
`Method for Making Same
`Field Effect Transistor Having Dielectrically Isolated Sources and Drains and
`Method for Making Same
`Transistor with Integrated Photodetector for Conductivity Modulation
`04/09/2002
`04/09/2002 Method of Fabricating Nan (sic. an) Embedded Flash EEPROM with a
`Tunnel Oxide Grown on a Textured Substrate
`Phase Leg with Depletion-Mode Device
`12/18/2001
`11/13/2001 Method for Forming Buried Layers with Top-Side Contacts and the Resulting
`Structure
`Fully-Dielectric-Isolated FET Technology
`09/18/2001
`08/07/2001 Method and Apparatus for Providing an Embedded Flash-EEPROM
`Technology
`Semiconductor Chip Package that is also an Antenna
`Semiconductor Structure with Heavily Doped Buried Breakdown Region
`Structure for Single Conductor Acting as Ground and Capacitor Plate
`Electrode Using Reduced Area
`Field Effect Transistor Having Dielectrically Isolated Sources and Drains and
`Method for Making Same
`Trench MOS-Gated Device
`Ballast Resistance for Producing Varied Emitter Current Flow Along the
`Emitter’s Injecting Edge
`Structure and Process for Reducing the On-Resistance of MOS-Gated Power
`Devices
`High Voltage Termination with Buried Field-Shaping Region
`01/04/2000
`Single Feature Size MOS Technology Power Device
`11/16/1999
`Single Feature Size MOS Technology Power Device
`11/09/1999
`Fully-Dielectric-Isolated FET Technology
`11/09/1999
`09/28/1999 Method of Making a Merged Device with Aligned Trench FET and Buried
`Emitter Patterns
`05/27/1999 Method of Manufacturing Insulated Gate Semiconductor Device to Improve
`Ruggedness
`Structure and Process for Reducing the On-Resistance of MOS-gated Power
`Devices
`Field Effect Transistor Having Dielectrically Isolated Sources and Drains
`Inverted Field-Effect Device with Polycrystalline Silicon/Germanium
`Channel
`Inverted Field-Effect Device with Polycrystalline Silicon/Germanium
`09/01/1998
`Channel
`
`Conductive Layer Overlaid Self-Aligned MOS-Gated Semiconductor Devices
`08/25/1998
`06/30/1998 Method Of Making A Fully-Dielectric-Isolated FET
`05/26/1998 Method of Making Trench MOS-Gated Device with A Minimum Number of
`
`02/09/1999
`
`01/05/1999
`10/13/1998
`
`6,465,304
`
`6,432,775
`
`6,420,764
`
`6,403,427
`
`6,399,961
`
`6,369,426
`6,368,918
`
`6,331,794
`6,316,336
`
`6,291,845
`6,272,050
`
`6,239,752
`6,225,662
`6,215,170
`
`6,198,114
`
`6,069,385
`6,064,109
`
`6,046,473
`
`6,011,298
`5,985,721
`5,981,998
`5,981,318
`5,960,277
`
`5,897,355
`
`5,869,371
`
`5,856,696
`5,821,136
`
`5,801,396
`
`5,798,549
`5,773,328
`5,756,386
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 9
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`
`11/25/1997
`
`01/07/1997
`
`Masks
`01/20/1998 Merged Device with Aligned Trench FET and Buried Emitter Patterns
`01/13/1998
`Pad Protection Diode Structure
`12/23/1997
`Insulated Gate Semiconductor Device Typically Having Subsurface-Peaked
`Portion of Body Region for Improved Ruggedness
`Integrated Structure Current Sensing Resistor For Power Devices Particularly
`For Overload Self-Protected Power MOS Devices
`09/16/1997 Method of Making a FET with Dielectrically Isolated Sources and Drains
`09/02/1997 Method of Making Increased Density MOS-Gated Semiconductor Devices
`07/15/1997
`Trench MOS-Gated Device with a Minimum Number of Masks
`06/17/1997
`Cell with Self-Aligned Contacts
`06/10/1997
`Composite Power Transistor Structures Using Semiconductor Materials With
`Different Bandgaps
`Process for Manufacturing a Vertical Switched-Emitter Structure with
`Improved Lateral Isolation
`12/31/1996 Method for Forming a Semiconductor Structure with Self-Aligned Contacts
`11/19/1996 Method of Making Vertical Current Flow Field Effect Transistor
`11/12/1996
`Vertical Switched-Emitter Structure with Improved Lateral Isolation
`06/18/1996
`Conductive-Overlaid Self-Aligned MOS-Gated Semiconductor Devices
`01/16/1996
`Isolated DMOS IC Technology
`03/29/1994
`Vertical Current Flow Field Effect Transistor with Thick Insulator Over Non-
`Channel Areas
`Temperature Sensing Device for Use in a Power Transistor
`08/17/1993
`High Voltage MOS Transistors with Reduced Parasitic Current Gain
`06/08/1993
`11/17/1992 Method of Making a Vertical Current Flow Field Effect Transistor
`10/20/1992
`Complementary, (sic) Isolated DMOS IC Technology
`07/21/1992 Method for Fabricating a High Voltage MOS Transistor
`07/23/1991
`Planar Vertical Channel DMOS Structure
`01/08/1991
`Vertical DMOS Transistor Fabrication Process
`12/18/1990
`Current Source with a Process Selectable Temperature Coefficient
`09/18/1990
`Junction Field-Effect Transistor with a Novel Gate
`09/11/1990
`Integrated Circuit with High Power, Vertical Output Transistor Capability
`08/28/1990 Method and Apparatus for Improving the On-Voltage Characteristics of a
`Semiconductor Device
`Rugged Lateral DMOS Transistor Structure
`05/29/1990
`Power Transistor with Integrated Gate Resistor
`04/24/1990
`04/10/1990 Method for Obtaining Low Interconnect Resistance on a Grooved Surface and
`the Resulting Structure
`Grooved DMOS Process with Varying Gate Dielectric Thickness
`Vertical DMOS Power Transistor with an Integral Operating Condition
`Sensor
`01/09/1990 Method for Increasing the Performance of Trenched Devices and the
`Resulting Structure
`Doped SiO2 Resistor and Method of Forming Same
`09/19/1989
`07/25/1989 Method for Providing Dielectrically Isolated Circuit
`07/04/1989
`Buried Gate JFET
`05/30/1989
`Dual-Gate High Density FET
`05/02/1989
`Implantation of Ions into an Insulating Layer to Increase Planar PN Junction
`
`04/03/1990
`01/23/1990
`
`5,710,443
`5,708,289
`5,701,023
`
`5,691,555
`
`5,668,025
`5,663,079
`5,648,670
`5,640,037
`5,637,889
`
`5,591,655
`
`5,589,415
`5,576,245
`5,574,301
`5,528,063
`5,485,027
`5,298,781
`
`5,237,481
`5,218,228
`5,164,325
`5,156,989
`5,132,235
`5,034,785
`4,983,535
`4,978,631
`4,958,204
`4,956,700
`4,952,992
`
`4,929,991
`4,920,388
`4,916,509
`
`4,914,058
`4,896,196
`
`4,893,160
`
`4,868,537
`4,851,366
`4,845,051
`4,835,586
`4,827,324
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 10
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`Breakdown Voltage
`04/25/1989 Method for Obtaining Regions of Dielectrically Isolated Single Crystal
`Silicon
`Power MOS Transistor with Equipotential Ring
`03/28/1989
`01/17/1989 Method and Apparatus for Increasing Breakdown of a Planar Junction
`
`01/17/1989 Method for Manufacturing a Power MOS Transistor
`12/27/1988
`High Voltage Drifted-Drain MOS Transistor
`12/13/1988
`Dense Vertical J-MOS Transistor
`09/27/1988 Method of Bonding Semiconductor Wafers
`08/30/1988 Method for Making Planar Vertical Channel DMOS Structures
`07/26/1988
`Ion Implantation of Thin Film CrSi2 and SiC Resistors
`11/24/1987 Manufacture of Trimmable High Value Polycrystalline Silicon Resistors
`07/28/1987 Methods for Forming Lateral and Vertical DMOS Transistors
`08/30/1983
`Composite MOS/Bipolar Power Device
`08/16/1983
`Fabrication Method for High Power MOS Device
`07/12/1983
`Power MOS Transistor With a Plurality of Longitudinal Grooves to Increase
`Channel Conducting Area
`08/17/1982 MOS Power Transistor with Improved High-Voltage Capability
`08/10/1982
`Combined DMOS and a Vertical Bipolar Transistor Device and Fabrication
`Method Therefor (sic)
`High Power MOS Device and Fabrication Method Therefor (sic)
`
`03/20/1979
`
`4,824,795
`
`4,816,882
`4,799,100
`
`4,798,810
`4,794,436
`4,791,462
`4,774,196
`4,767,722
`4,759,836
`4,707,909
`4,682,405
`4,402,003
`4,398,339
`4,393,391
`
`4,345,265
`4,344,081
`
`4,145,703
`
`Education
`
`Year
`1982
`1970
`1968
`
`Publications – Books
`
`Blanchard, R. A., Burgess, David, “Wafer Failure Analysis for Yield Enhancement,”
`Accelerated Analysis, 2000.
`
`University
`Stanford University
`M.I.T.
`M.I.T.
`
`Degree
`Ph.D., Electrical Engineering
`MSEE
`BSEE
`
`Blanchard, R.A., “Electronic Failure Analysis Handbook,” co-author of three chapters, P. L.
`Martin, ed., McGraw-Hill, 1999.
`
`Blanchard, R.A., Trapp, O., Lopp, L., “Semiconductor Technology Handbook,” Portola
`Valley, California, Technology Associates, 1993.
`
`Blanchard, R.A., “Discrete Semiconductor Switches: Still Improving,” Chapter 3, Section 6,
`Modern Power Electronics, B. K. Bose, ed., Piscataway, N.J, IEEE Press, 1992.
`
`Blanchard, R.A., “Power Integrated Circuits: Physics, Design, and Application,” (Chapter 3
`with J. Plummer) McGraw-Hill, 1986.
`
`Blanchard, R.A., Gise, P., “Modern Semiconductor Fabrication Technology,” Reston
`Publishing Company, 1986.
`
`Resume of Richard A. Blanchard, Ph.D.
`Printed: 06/12/13
`
`
`
`Page 11
`
`TSMC1004
`IPR of U.S. Pat. No. 7,485,968
`
`

`

`Thomson Reuters Expert Witness Services
`Consultant Curriculum Vitae
`
`
`Blanchard, R.A. and others, “MOSPOWER Applications Handbook,” Siliconix, Inc., 1984;
`Sections 1.3, 2.9, 2.9.1, 2.11, 4.2, 5.6, 5.6.2, 7.1.
`
`Blanchard, R.A., Gise, P., “Semiconductor and Integrated Circuit Fabrication Techniques,”
`Reston Publishing Company, 1979.
`Publications - Papers
`
`Blanchard, R.A., Wong, Chuck, “Off-Line Battery Charger Circuit with Secondary-Side
`PWM Control,” HFPC 2000 Proceedings, October 2000.
`
`Blanchard, R. A., Kusko, Alexander, “Electrical Arcing—Its Impact on Power Quality,”
`Power Quality Assurance, May/June 1996.
`
`Blanchard, R. A., Kusko, Alexander, “Standby vs. Online UPS,” Power Quality Assurance,
`March/April 1996.
`
`Blanchard, R. A., Kusko, Alexander, “Power Electronic Equipment Protection,” Power
`Quality Assurance, January/February 1996.
`
`Blanchard, R.A., Li, R., “Quantitative Analysis and M