throbber
Declaration of Richard A. Blanchard in Support of Petition for
`inter partes review of U.S. Patent No. 7,485,968
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`
`Mail Stop: Inter Parties Review
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`
`
`Attn: Patent Trial and Appeal Board
`Commissioner for Patents
`PO Box 1450
`Alexandria, VA 22313-1450
`
`Commissioner:
`
`I, Richard A. Blanchard, declare as follows:
`
`1.
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`I have been retained on behalf of (TSMC) for the above-captioned inter
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`partes review proceeding. I understand that this proceeding involves U.S. Patent
`
`No. 7,485,968 (hereinafter the “ ‘968 Patent”).
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`2.
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`I have reviewed and am familiar with the specification of the ‘968 Patent,
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`which was filed on August 11, 2005, and issued on February 3, 2009.
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`3.
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`I have reviewed and am familiar with U.S. Patent No. 5,753,536 to
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`Sugiyama et al. (hereinafter “Sugiyama”), U.S. Patent No. 6,465,892 to Suga et al.
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`(hereinafter “Suga”), U.S. Patent No. 6,867,073 to Enquist et al., (hereinafter
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`“Enquist”), U.S. Patent No. 6,902,987 to Tong et al., hereinafter the “ ‘987
`
`Patent”), and U.S. Patent No. 6,962,835 to Tong et al. (hereinafter the “ ‘835
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`Patent”).
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`4.
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`I have been asked to provide my technical review, analysis, insights and
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`opinions regarding the above-noted references that form the basis for the grounds
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`for rejection set forth in the Petition for inter partes review of the ‘968 Patent.
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`5.
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`In my judgment, as an expert in the field of semiconductor manufacturing
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`and semiconductor materials since at least 1977, I am qualified to provide an
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`opinion as to what a person of ordinary skill in the art would have understood,
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`known or concluded at the time that the ‘968 Patent was filed.
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`I. Qualifications
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`6.
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`I am a consultant for Thomson Reuters Expert Witness Services
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`(previously known as Silicon Valley Expert Witness Group), a consulting
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`company specializing in expert witness litigation support and technology
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`consulting. I also provide technical consulting services to the semiconductor and
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`electronics industry through Blanchard Associates
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`7. My academic credentials include both a Bachelor of Science Degree in
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`Electrical Engineering (BSEE) and a Master of Science Degree in Electrical
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`Engineering (MSEE) from the Massachusetts Institute of Technology in 1968 and
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`1970, respectively. I subsequently obtained a Ph. D. in Electrical Engineering in
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`1982 from Stanford University.
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`8. My professional background and technical qualifications are stated above
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`and are also reflected in my Curriculum Vitae, which is attached as TSMC-1004.
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`I am being compensated at a rate of $275.00 per hour, with reimbursement for
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`actual expenses, for my work related to this petition for Inter Partes Review. My
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`compensation is not dependent on and in no way affects the substance of my
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`statements in this declaration.
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`9.
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`I have worked or consulted for more than 40 years as an Electrical Engineer.
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`My primary focus has been the development, manufacture, operation and use of
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`devices and integrated circuits, the assembly of these devices and integrated
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`circuits, products that use them and their failures. My employment history
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`following my graduation from MIT began at Fairchild Semiconductor in 1970. At
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`Fairchild, my responsibilities included circuit and device design, process
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`development and product engineering in the Linear Integrated Circuits
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`Department.
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`10.
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`In 1974, I joined Foothill College as an Associate Professor in the
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`Engineering & Technology Division. My responsibilities included developing a
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`program in Semiconductor Technology as well as teaching other courses in the
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`division. While at Foothill College, I co-founded two companies, Cognition and
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`Supertex, and later joined Supertex as a Vice President in 1978. At Supertex, I
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`designed and developed discrete DMOS (double-diffused metal oxide
`
`semiconductor) transistors as well as integrated circuits that contained DMOS
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`transistors. At Supertex, I also supervised the in-house assembly area, which
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`included responsibility for the semiconductor manufacturing processes.
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`11.
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`I left Supertex to join Siliconix in 1982, where I soon became Vice President
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` of Engineering, with the responsibility for directing all of the company’s product
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`design and development. At Siliconix, I directed and contributed to the
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`development of both discrete transistors and integrated circuits, including aspects
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`of their assembly.
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`12.
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`In 1987, I joined IXYS Corporation as a Senior Vice President with the
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`responsibility for organizing an integrated circuits department. At IXYS, I
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`developed integrated circuits that contained DMOS transistors or that interfaced to
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`DMOS devices. My responsibilities included the design, the assembly, and the
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`testing of these integrated circuits.
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`13. These duties continued until 1991, when I left IXYS to set up Blanchard
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`Associates, a consulting firm specializing in semiconductor technology, including
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`intellectual property. Soon thereafter, I was invited to join Failure Analysis
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`Associates, which I did in late 1991. At Failure Analysis Associates, I investigated
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`failures in electrical and electronic systems in addition to performing design and
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`development consulting. Some of this work included the investigation of
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`semiconductor material properties.
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`14.
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`I left Failure Analysis in 1998 to join IP Managers, which later merged with
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`the Silicon Valley Expert Witness Group, now known as Thomson Reuters Expert
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`Witness Services (“Thomson Reuters”). At Thomson Reuters, I work with
`
`companies on patent and trade secret matters. I also consult for a number of
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`semiconductor companies, working with them to develop products and intellectual
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`property, or assisting them in other technical areas through Blanchard Associates.
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`I am a member of a number of professional societies, including the Institute of
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`Electrical and Electronic Engineers, the International Microelectronics and
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`Packaging Society, the American Vacuum Society, the Electronic Device Failure
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`Analysis Society, and the Electrostatic Discharge Society.
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`II. My understanding of anticipation and obviousness
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`15.
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` It is my understanding that a claimed invention is unpatentable if the
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`claimed invention is anticipated by a single prior art reference. To anticipate a
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`claim, the prior art reference must disclose each and every element as set forth in
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`the claim, either expressly or by an inherent description. However, if a claim
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`covers several alternatives, the claim is anticipated if any of the structures or
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`composition within the scope of that claim is known in the prior art.
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`16.
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` It is my understanding that a claimed invention is unpatentable if the
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`differences between the invention and the prior art are such that the subject matter
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`as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which the subject matter pertains. It is my
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`understanding that “obviousness” is a question of law based on underlying factual
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`issues including the content of the prior art and the level of skill in the art. I
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`understand that for a single reference or a combination of references to make the
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`claimed invention obvious, a person of ordinary skill in the art must have been able
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`to arrive at the claimed invention by modifying, altering or combining the applied
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`references.
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`17.
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`I also understand that when considering the obviousness of a patent claim,
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`one should consider whether a teaching, suggestion or motivation to combine the
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`references exists so as to avoid impermissibly applying hindsight when considering
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`the prior art. I understand this test should not be rigidly applied, but that the test
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`can be important to avoid such hindsight.
`
`III. Background of the ‘968 Patent
`
`18. The ‘968 Patent describes vertically stacking ICs using direct bonding and
`
`forming vertical interconnections. See ‘968 Patent, Col. 1:52-57. The ‘968 Patent
`
`provides methods for forming vias in three-dimensionally stacked dies or wafers.
`
`See, ‘968 Patent, Abstract. These methods were known in the art at the time of the
`
`invention.
`
`19. An example of this structure is shown, among others, as in Figure 23(O) of
`
`the ‘968 Patent, where a lower substrate 140 including contacts 142 is bonded to an
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`upper substrate 140 with contact structures 147 bonded to it. See, e.g., ‘968 Patent,
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`Col. 30:56-65. Such techniques were well known in the art at the time of the
`
`invention.
`
`20. Structures described in the ‘968 Patent, in particular those claimed, were
`
`well known in the art at the time of the invention. By 2000, methods of increasing
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`the density of integrated circuits, as dictated by Moore’s law, had progressed to the
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`point that vertically interconnected stacked devices were becoming more important
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`for increasing circuit density. The structures such as those described in the ‘968
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`Patent were practiced in the art at the time of the invention.
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`21. The technology of the ‘968 Patent, for example as described in Col. 32:29-
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`52 of the ‘968 Patent, and related patents and literature known in the art at the time
`
`of the invention are focused on providing a solution to the need for very dense 3D
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`integrated circuits. Basically, this art provides methods to directly bond
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`semiconductor devices together with interconnect structures including vias to
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`provide vertical interconnection paths. The methods described in the ‘968 Patent
`
`were also practiced in the art at the time of the invention.
`
`22. Currently, technologies used to increase chip complexity are being
`
`accomplished with ever smaller feature sizes using semiconductor layers separated
`
`by insulators connected in 3D stacks with conductive interconnect layers bridging
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`between the isolated layers. The ‘968 Patent and related patents and literature
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`known in the art at the time of the invention provided complete directly bonded 3D
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`IC structures at low temperatures. These 3D IC structures were vertically
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`interconnected using vias, which enabled the increasingly dense 3D chip
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`technology .
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`IV. Application of the Sugiyama Reference
`
`23. Sugiyama describes direct bonding of insulation layers 15 to 12 as illustrated
`
`in Figure 5(b), for example; describing the elements of “said first insulating layer
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`directly bonded to said second insulating layer” as in claim 1, “said first and
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`second insulating layer are directly bonded” as in claim 17, “said first insulating
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`region directly bonded to said second insulating region” as in claim 20 and
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`“wherein said first element is bonded to said second element using a direct bonding
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`process” as in claim 41. In Sugiyama, in various embodiments, the insulating
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`layers are described as silicon oxide and silicon nitride, for example at Col. 18:1-5
`
`as silicon nitride at Col. 26:10-25; and as a plasma (silicon) oxide, at Col. 13:39-
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`41. These disclosures in Sugiyama would be consistent with forming low
`
`temperature oxide-to-oxide bonds known in the art of the time of the invention of
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`the ‘968 Patent.
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`24.
`
`In Sugiyama, metal contacts are formed adjacent to the SiO2 described in
`
`paragraph 23, above. Sugiyama discloses “said first contact structure directly
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`connected to said second contact structure” as is described in claim 1 and “said
`
`first conducting region directly connected to said second conducting region;” as is
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`described in claim 20 of the ‘968 Patent. Sugiyama mentions that the metal layers
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`are pressed together and make contact as illustrated in Figure 28(b) (contacts 11,
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`14) and described in Col. 25: 49-51.
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`25. Sugiyama describes the first contact structure, electrode 11, directly
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`connected to the second contact structure, electrode 14 as illustrated and described
`
`in Fig. 28(b); Col. 25: 49-51. Sugiyama creates an interconnect structure in a via,
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`extending through dielectric between horizontal metal layers shown over substrate
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`10 and connected to the first contact structure, 11, as shown in Fig. 28(b). The
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`electrode 11 and the interconnect structure are in contact and coupled as shown in
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`Fig. 28(a), and Fig. 28(b). Thus, Sugiyama describes an interconnect structure
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`disposed in a via and connected to the first contact structure, as recited in claim 1.
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`26.
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`In Figure 28(b), Sugiyama illustrates processes and structures used to satisfy
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`the elements of “said first contact structure being substantially planar with a
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`surface of said first insulating layer” recited in claim 2 where the first contact
`
`structure, 11, created in SiO2 layer 12 with said layer substantially planar. In
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`various embodiments, Sugiyama describes planarizing insulating layers with a
`
`polishing process that exposes the surface of electrodes, for example see Col.
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`26:10-14, 25-26. Thus, Sugiyama discloses creating a planar surface on the first
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`contact structure and the first insulating layer. The same process disclosed by
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`Sugiyama described above for claim 2 also discloses “said second contact structure
`
`being substantially planar with a surface of said second insulating layer” as recited
`
`in claim 3 to form the contact structure and the second insulating layer that are also
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`substantially planar. Again, the same steps described by Sugiyama which as
`
`described above also meet the limitations described for claim 27, “said first
`
`conducting region being substantially planar with a surface of said first insulating
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`region;” and the limitations of claim 28; “said second conducting region being
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`substantially planar with a surface of said second insulating region” to form the
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`first contact structure that is substantially planar with the surface of the first
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`insulating layer. Finally, for all four claims addressed in this paragraph, the
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`polishing processes used to create these substantially planar surfaces were well
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`known in the semiconductor art at the time of the invention.
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`27. Sugiyama adds additional metals to the contact structures. Tin is disclosed
`
`as a contact structure that Sugiyama describes as electrodes for instance, at Col.
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`19:14-20. A further list of metals that Sugiyama describes as electrodes include
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`tungsten, aluminum and copper; as found in Col. 27:23-26. Sugiyama also adds
`
`nickel and silver as metals that may be used to electroplate these electrodes as
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`described in Col 27:20-22. Thus, Sugiyama discloses claim elements such as
`
`“wherein said first contact structure comprises one of copper, tungsten, nickel, and
`
`gold” in claim 4, “wherein each of said first and second contact structures
`
`comprises one of copper, tungsten, nickel and gold” in claim 9, “wherein said first
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`conducting region comprises one of copper, tungsten, nickel, and gold” in claim 29
`
`and “wherein each of said first and second conducting regions comprises one of
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`copper, tungsten, nickel, and gold” in claim 34 of the ‘968 Patent. The metals
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`described by Sugiyama for electrodes as well as those described for electroplating
`
`are consistent with the semiconductor metallurgical art practiced at the time of the
`
`invention.
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`28. The Enquist ‘968 Patent describes the metals preferred for thermally
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`expanded contact structures as “copper, nickel and gold,” and “tungsten and
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`nickel” at, for example, See ‘968 Patent, Col. 15:20-24. Sugiyama also describes
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`first and second substrates with contract structures that are heated after direct
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`bonding, and describes that this creates a thermally-expanded metal contract
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`structure in Col. 23:21-26. Sugiyama describes an example, heating the substrates
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`at above 400 degrees C. to improve bonding as described in Col. 13: 39-41.
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`Sugiyama discloses that the contact structures (electrodes) may be formed of any
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`of CVD deposited tungsten, aluminum, and copper; see, e.g., Col. 27:23-26; and
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`further the electrodes may be electroplated and may include nickel and silver; see,
`
`e.g., Col. 27: 20-22. Thus, Sugiyama discloses “wherein each of said first and
`
`second contact structures comprises a thermally-expanded metal contact structure”,
`
`as recited in claim 8; and the limitation “at least one of said first and second
`
`conducting regions comprises a thermally-expanded metal contact structure” of
`
`claim 20. These elements are also shown by the above arguments where Sugiyama
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`describes that first and second substrates are heated after direct bonding, thus
`
`forming a thermally-expanded metal contract structure, as described in Col. 25:48-
`
`51.
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`29. Sugiyama also discloses “first and second conducting regions comprises a
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`thermally-expanded metal contact structure” as recited in claim 33, based on the
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`prior paragraph 28 discussion and discloses that first and second substrates
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`including the first and second conducting regions are heated after direct bonding,
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`thus forming a thermally-expanded metal conducting regions as described in Col.
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`23: 21-26, where the first conducting regions which are electrodes that may be
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`formed using CVD deposited tungsten, aluminum, and copper as described in Col.
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`27: 23-26, and further the electrodes may be electroplated with nickel and silver; as
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`described in Col. 27: 20-22.
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`V. Application of the Suga Reference
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`30. Suga describes directly bonding the first insulating layer 12 and second
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`insulating layer 13 as illustrated in Fig. 2 of Suga, which is described in Col. 10: 4-
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`9; and Suga teaches that the insulating layers are then “mechanically connected” as
`
`described in Col. 2:1-14; see also Col. 8: 4-24; Col. 10: 6-9. Thus, the elements of
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`“said first insulating layer directly bonded to said second insulating layer” recited
`
`in claim 1 and similar elements in claims 17 and 20 are all satisfied. Additionally,
`
`the elements “wherein said first element is bonded to said second element using a
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`direct bonding process” recited in claim 41 are met in light of Suga’s disclosure
`
`that the first element is directly bonded to the second element as illustrated in Fig.
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`2, and described in Col. 2:1-14; see also Col. 5: 28-35; Col. 8: 16-22; and Col. 10:
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`4-9.
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`31. Suga discloses directly connecting the contact structures 5, 6 together during
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`bonding. Thus, Suga describes the first contact structure 5, directly connected to
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`the second contact structure 6 as shown in Fig. 2 and described in Col. 5: 28-35;
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`Col. 10: 4-9. Thus, the elements “said first contact structure directly connected to
`
`said second contact structure” as recited in claim 1 and “said first conducting
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`region directly connected to said second conducting region” as in claim 20 are
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`both described by Suga.
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`32. Suga illustrates and describes forming an interconnect in a via, which is the
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`vertical portion of structure 5 extending from wiring layer 3 through the insulating
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`layer 7 to the first contact structure, which is the bottom portion of structure 5
`
`illustrated in Fig. 2, and described in Col. 5: 13-20. Suga discloses the element “an
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`interconnect structure disposed in a via and connected to said first contact
`
`structure” as recited in claim 1.
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`33. Suga discloses that the first contact structure, which is a portion of structure
`
`5, and the first insulating layer 12, as illustrated in Figure 1, are created on
`
`substrate 1, after which the surface is smoothed by surface polishing that forms a
`
`substantially planar surface as illustrated in Figure 1 and described in Col. 5:21-23
`
`and Col. 9:50-56. Thus, Suga discloses “said first contact structure being
`
`substantially planar with a surface of said first insulating layer” as in claim 2.
`
`Similarly, Suga discloses that the second contact structure, which is a portion of
`
`structure 6 on substrate 2 is formed with the second insulating layer 13 and
`
`smoothed by surface polishing; as illustrated in Suga Figure 1, forms a
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`“substantially planar” surface as described by Suga, in Col. 5: 24-27; Col. 9: 57-65
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`and this discloses the elements of claim 3. Suga further discloses forming the first
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`conducting region and the first insulating region and then polishing the surface,
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`thereby forming substantially planar surface in Col. 7: 21-30. Similarly, Suga
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`discloses surface polishing a contact structure and an insulating layer in Col. 7:31-
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`33, which forms a second contact structure that is therefore substantially planar
`
`with the surface of the second insulating layer. Suga thus discloses the elements of
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`claims 27 and 28.
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`34. Suga states that the first contact structure 5 in Figure 1 may be formed from
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`copper or gold, as illustrated in Fig. 1, and described in Col. 5:42-50. Also, Suga
`
`states the first and second contact structures 5 and 6 illustrated in Figure 2 may be
`
`formed from copper, aluminum or gold in Col. 5:42-50. The claim elements
`
`“wherein said first contact structure comprises one of copper, tungsten, nickel, and
`
`gold” recited in claim 4 and similar elements of claim 9 are disclosed. Similarly,
`
`Suga discloses that the first conducting region which is structure 5 in Fig. 2, for
`
`example, may be formed from copper, aluminum or gold at Col. 5:42-50, which
`
`describes the elements of claim 29. Furthermore, Suga discloses that each of the
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`first and second conducting regions, that are contact structures, comprises copper
`
`or gold, as is also recited in claim 34. The features are illustrated in Suga, Figures
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`1 and 2, and described in Col. 5: 42-50.
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`35. The Enquist ‘968 Patent describes the metals preferred for thermally
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`expanded contact structures as “copper, nickel and gold,” and “tungsten and
`
`nickel,” at , for example, ‘968 Patent, Col. 15:20-24. Similarly, Suga describes the
`
`first contact structure 5 may be formed from copper, aluminum or gold at, Col.
`
`5:42-50. It is well known by those in the art that metals expand when heated,
`
`which Suga states will form thermally expanded contact structures. Thus, the
`
`element of “wherein each of said first and second contact structures comprises a
`
`thermally-expanded metal contact structure” of claim 8 is disclosed by Suga. Suga
`
`further discloses in Col. 5:42-49 the first and second conducting regions which are
`
`structures 5 and 6 may be made of gold and aluminum, which are thermally
`
`expandable materials; thus the elements of “said first and second conducting
`
`regions comprises a thermally-expanded metal contact structure” of claim 20, and
`
`the similar element of claim 33 are also described by Suga.
`
`VI.
`
` The Enquist ‘073 patent
`
`36. There are significant similarities between the ‘968 Patent and U.S. Patent
`
`No. 6,867,073 (the Enquist ‘073 Patent) which was filed on October 21, 2003.
`
`including that Figures 1 – 19 of the ‘073 patent are identical to Figures 1 – 19A of
`
`the’968 Patent, with the exception of the numbering of some elements. The
`
`“Background of the Invention” section of the Enquist ‘073 Patent is included part
`
`of the same section in the ‘968 Patent. Only a small amount of additional
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`information is included in this section of the ‘968 Patent. The initial paragraphs of
`
`the “Detailed Description of the Preferred Embodiments” section of the ‘073
`
`Patent are included in the corresponding section of the ‘968 Patent. It is therefore
`
`no surprise that most or all of the elements of the majority of the claims of the ‘968
`
`Patent are contained in the specification of the ‘073 patent.
`
`37.
`
` Claims 1 and 20 of the ‘968 Patent are independent claims, but share many
`
`of the same features. All of the features of each of these two claims are present in
`
`the Enquist ‘073 Patent. Both Figure 18 and Figure 19 of the ‘073 Patent show
`
`first and second elements, each of which comprises a substrate. The ‘073 Patent at
`
`Col. 5: 46-48 discusses oxide-to-oxide bonding, and also includes by reference,
`
`U.S. Patent Application 09/505,283, which became U.S. 7,902,987 (the ‘987
`
`Patent). The ‘987 Patent discusses wafer bonding, including the bonding of
`
`surfaces of silicon dioxide and silicon nitride (See Col. 2: 64 – 67). The two
`
`substrates each include a contact structure, and the contact structure present on the
`
`first substrate is directly connected to the contact structure on the second substrate
`
`as discussed at Col. 11:25-31 of the ‘073 Patent.
`
`38. Most of the features of the claims that depend on independent claims 1 and
`
`20 are also present in the ‘073 Patent. The ‘073 Patent discusses semiconductor
`
`substrates, for instance at Col. 1: 18-20 and Col. 4: 56-60. The contact structure
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`present on each substrate is substantially planar with the insulating layer as shown
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`IPR of U.S. Pat. No. 7,485,968
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`

`

`in figures 18 and 19 of the ‘073 Patent. Both the insulating regions and the contact
`
`structures of the two substrates are also described as being in contact with each
`
`other at Col. 11: 21-33 of the ‘073 patent. The metal used to form the contact
`
`structures is not described in the ‘073 Patent, but Enquist ‘073 further incorporates
`
`by reference U.S. Patent Application Serial No. 10/359, 608, which issued as U.S.
`
`Patent No. 6,962,835; see, e.g., Enquist ‘073, Col. 11:25-28, and the ‘835 Patent
`
`discloses direct bonding of metal contacts, including copper and gold, see, e.g.,
`
`‘835 Patent, Col. 15:34-35.
`
`39. Enquist ‘073 further incorporates by reference U.S. Patent Application Serial
`
`No. 10/359, 608, which issued as U.S. Patent No. 6,962,835; see, e.g., Enquist
`
`‘073, Col. 11:25-28, and the ‘835 Patent discloses direct bonding of metal contacts,
`
`including copper and gold, see, e.g., ‘835 Patent, Col. 15:34-35.
`
`
`
`VII. Sugiyama, Suga and/or Enquist ‘073 may be combined
`
`40.
`
`If additional support is needed for any elements of the claims described
`
`above, the teachings of Sugiyama, Suga and/or Enquist ‘073 may also be combined
`
`to provide it. One skilled in the art would know to modify Sugiyama, for example,
`
`with the disclosures provided by Suga and/or Enquist ‘073, to form the claimed
`
`features of the ‘968 Patent.
`
`
`
`Page 17 of 18
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`
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`
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`TSMC1003
`IPR of U.S. Pat. No. 7,485,968
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`

`

`I hereby declare that all statements made herein of my own knowledge are
`
`true and that all statements made herein on information and belief are believed to
`
`be true, and further that these statements were made with the knowledge that
`
`willful false statements and the like so made are punishable by fine, or
`
`imprisonment, or both, under Section 1001 of Title 18 of the United States Code.
`
`Tlx
`Executed this ] 5
`
`day of Uyne
`
`in
`
`”20]":
`
`.
`
`gain—l}: Clara Can-wig) CHAN-”ma
`
`{214311 31.st
`
`Richard A. Blanchard
`
`Page 18 of18
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`TSMC1003
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`IPR ofU.S. Pat. No. 7,485.968
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`

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