USOO7485968B2
`
`(12) Unlted States Patent
`(10) Patent No.:
`US 7,485,968 B2
`
`Enquist et a].
`(45) Date of Patent:
`Feb. 3, 2009
`
`(54)
`
`3]) IC METHOD AND DEVICE
`
`2002/0094661 A1
`2002/0113241 A1
`
`7/2002 Enquist et a1.
`8/2002 Kubota et a1.
`
`(75)
`
`_
`.
`_
`InVemorS: Pfiul M- Enqut; Cary, NC (Us): Galus
`Glllman Fountaln, Jr-,Y0ungSVIlle, NC
`(US); Qin-Yi Tong, Durham, NC (US)
`
`(73) Assignee: Ziptronix, Inc., Morrisville, NC (US)
`
`6/2003 Ahmad
`2003/0109083 A1
`7/2003 Bruchhaus et a1.
`2003/0129796 A1
`2004/0262772 A1 * 12/2004 Ramanathan et a1.
`
`....... 257/777
`
`(Continued)
`OTHER PUBLICATIONS
`
`( * ) Netice:
`
`Subjectto any diSCIaimerf the term Ofthis
`patent IS GXtended 01‘ adJUSted under 35
`U.S.C. 154(b) by 266 days.
`
`K. Warner et a1., “Low-Temperature Oxide-Bonded Three-Dimen-
`sional Integrated Circuits”, IEEE International SOI Conference, Oct.
`2002, pp. 123-125.
`
`(21) App1.No.: 11/201,321
`.
`F11ed:
`
`(22)
`
`Aug. 11, 2005
`
`(65)
`
`Prior Publication Data
`
`(commued)
`Primar ExamineriDavid Vu
`y
`(74) Attorney, Agent, or FirmgOblon, Spivak, McClelland,
`Maier & Neustadt, PC.
`
`Us 2007/0037379 A1
`
`Feb. 15, 2007
`
`(57)
`
`ABSTRACT
`
`(51)
`
`Int. Cl.
`(2006.01)
`H01L 23/48
`.
`(52) U.S. Cl.
`....................................... 257/777, 438/455
`(58) Field of Classification Search ................. 257/777,
`257/55275/‘22’0136235636, 71302052%)? iii/(2515’
`.
`.
`‘
`’
`’
`’
`.
`’
`See application file for complete search history.
`References Cited
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`
`(56)
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`4/1989 Rai et a1.
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`
`A method of three-dimensionally integrating elements such
`as singu1ated die or wafers and an integrated structure having
`connected elements such as sin u1ated dies or wafers. Either
`b h f h d'
`d
`f
`gh
`.
`d
`d
`.
`195$;d311;;12a;5x31363321\flihfgsaefinrlsiocgnltlggls1118:1101:
`is bonded to a second element having a second contact struc-
`ture. First and second contact structures can be exposed at
`bonding and electrically interconnected as a result of the
`bonding. A Via may be etched and filled after bonding to
`expose and form an electrical interconnect to interconnected
`first and second contact structures and provide electrical
`access to this interconnect from a surface. Alternatively, first
`and/or second contact structures are not exposed at bonding,
`and a via is etched and filled after bonding to electrically
`interconnect first and second contact structures and provide
`electrical access to interconnected first and second contact
`
`structure to a surface. Also, a device may be formed in a first
`substrate, the device being disposed in a device region of the
`first substrate and having a first contact structure. A via may
`be etched, or etched and filled, through the device region and
`into the first substrate before bonding and the first substrate
`thinned to expose the via, or filled via after bonding.
`
`41 Claims, 33 Drawing Sheets
`
`1 68
`
`147
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`1 68
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`147
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`168
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`
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`140
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`Page 2
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`OTHER PUBLICATIONS
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`Y. Hayashi et al., “Fabrication of Three-Dimensional IC Using
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`* cited by examiner
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`U.S. Patent
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`Sheet 1 of 33
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`US 7,485,968 B2
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`14
`\
`
`15
`\
`
`16
`\
`
`18 \[
`
`'—_ =
`
`10
`
`FIG. 2A
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`FIG. 28
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`Sheet 2 of 33
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`US 7,485,968 B2
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`FIG. 20
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`FIG. 3A
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`FIG. 3B
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`Sheet 3 of 33
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`FIG. 4
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`FIG. 5
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`FIG. 6B
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`FIG. 6A
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`Sheet 4 of 33
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`US 7,485,968 B2
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`FIG. 7A
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`FIG. TB
`
`IIIIIIIIII”Illllltlll’lltl'l'
`
`III’Ill'
`
`a
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`Sheet 5 of 33
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`US 7,485,968 B2
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`FIG. 8A
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`FIG. BB
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`Sheet 6 of 33
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`US 7,485,968 B2
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`
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`FIG. 8D
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`Sheet 7 of 33
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`US 7,485,968 B2
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`FIG. 8E
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`FIG. 8F
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`Sheet 8 of 33
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`FIG. 8G
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`FIG. 8H
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`Sheet 9 of 33
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`US 7,485,968 B2
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`FIG. 8|
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`FIG. 8J
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`Sheet 10 of 33
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`US 7,485,968 B2
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`FIG. 8K
`IlllllllllIl'lllllllllllllllt.
`
`FIG. 9A
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`10
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`Sheet 11 of 33
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`US 7,485,968 B2
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`FIG. QC
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`FIG. QB
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`1O
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`Sheet 12 of 33
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`US 7,485,968 B2
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`FIG. 108
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`FIG. 10A
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`FIG. 1OC
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`Sheet 13 of 33
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`US 7,485,968 B2
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`
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`Sheet 14 of 33
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`US 7,485,968 B2
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`FIG. 11
`10
`
`101
`
`FIG. 12
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`Sheet 15 of 33
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`US 7,485,968 B2
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`104
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`FIG. 13
`FIG. 14
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`105
`
`1O
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`Sheet 16 of 33
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`US 7,485,968 B2
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`107
`
`
`110
`
`FIG. 16A
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`FIG. 16B
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`112
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`Sheet 17 of 33
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`US 7,485,968 B2
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`FIG. 17
`
`
`
`FIG. 19A
`
`110
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`FIG. 18
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`110
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`121
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`Sheet 18 of 33
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`US 7,485,968 B2
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`me. 198 —
`
`
`
`
`110
`
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`Sheet 19 of 33
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`US 7,485,968 B2
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`FIG. 20A
`
`
`
`FIG. 208
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`89
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`88
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`FIG. 20C
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`Sheet 20 of 33
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`US 7,485,968 B2
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`'llllll'ltttat- I'll'l'llllllllt
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`
`80
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`Sheet 21 of 33
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`US 7,485,968 B2
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`76/
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`FIG. ZOG
`
`88/
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`Sheet 22 of 33
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`US 7,485,968 B2
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`FIG. 21B
`
`FIG. 210
`
`FIG. 21D
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`130
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`Sheet 23 of 33
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`US 7,485,968 B2
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`FIG. 22A
`
`147
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`147(154)
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`Sheet 24 of 33
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`US 7,485,968 B2
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`FIG. 22D
`
`147(154)
`150
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`Sheet 25 of 33
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`US 7,485,968 B2
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`144
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`145
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`Sheet 26 of 33
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`US 7,485,968 B2
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`F|C3.122J
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`147(154)
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`147 (154)
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`Sheet 27 of 33
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`US 7,485,968 B2
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`
`
`143
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`
`FIG. 238
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`Sheet 28 of 33
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`US 7,485,968 B2
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`)
`
`140
`
`FIG. 23F
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`FIG. 236
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`140
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`140
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`161
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`Sheet 29 of 33
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`US 7,485,968 B2
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`164
`
`FIG. 231
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`140
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`147 (154)
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`
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`Sheet 30 of 33
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`US 7,485,968 B2
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`
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`Sheet 31 of 33
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`US 7,485,968 B2
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`140
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`FIG. 24A
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`144
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`145
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`TSMC1001
`IPR of U.S. Pat. No. 7,485,968
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`U.S. Patent
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`Feb. 3, 2009
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`Sheet 32 of 33
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`US 7,485,968 B2
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`TSMC1001
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`IPR of U.S. Pat. No. 7,485,968
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`TSMC1001
`IPR of U.S. Pat. No. 7,485,968
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`U.S. Patent
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`Feb. 3, 2009
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`Sheet 33 of 33
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`US 7,485,968 B2
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`7/1
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`TSMC1001
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`IPR of U.S. Pat. No. 7,485,968
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`TSMC1001
`IPR of U.S. Pat. No. 7,485,968
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`

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`1
`3D IC METHOD AND DEVICE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is related to applications Ser. No. 09/532,
`886, now U.S. Pat. No. 6,500,794, Ser Nos. 10/011,432,
`10/359,608, 10/688,910, now U.S. Pat. No. 6,867,073, and
`Ser. No. 10/440,099, the entire contents of which are incor-
`porated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to the field of three-dimen-
`sional integrated circuits and more particularly to devices and
`the fabrication thereof of three-dimensional integrated cir-
`cuits using direct wafer bonding.
`2. Description of the Related Art
`Semiconductor integrated circuits (ICs) are typically fab-
`ricated into and on the surface of a silicon wafer resulting in
`an IC area that must increase as the size of the IC increases.
`
`Continual improvement in reducing the size of transistors in
`ICs, commonly referred to as Moore’s Law, has allowed a
`substantial increase in the number of transistors in a given IC
`area. However, in spite of this increased transistor density,
`many applications require an increase in total IC area due to
`a greater increase in required transistor count or an increase in
`the number of lateral interconnections required between tran-
`sistors to achieve a specific function. The realization of these
`applications in a single, large area IC die typically results in a
`reduction in chip yield and, correspondingly, increased IC
`cost.
`Another trend in IC fabrication has been to increase the
`
`number of different types of circuits within a single IC, more
`commonly referred to as a System-on a-Chip (SoC). This
`fabrication typically requires an increase in the number of
`mask levels to make the different types of circuits. This
`increase in mask levels typically also results in a reduction in
`yield, and correspondingly, increased IC cost. A solution to
`avoiding these undesired decreases in yield and increases in
`cost is to vertically stack and vertically interconnect ICs.
`These ICs can be of different size, come from different size
`wafers, comprise different functions (i.e., analog, digital,
`optical), be made of different materials (i.e., silicon, GaAs,
`InP, etc.). The ICs can be tested before stacking to allow
`Known Good Die (KGD) to be combined to improve yield.
`The economic success of this vertical stacking and vertical
`interconnect approach depends on the yield and cost of the
`stacking and interconnection being favorable compared to the
`yield and cost associated with the increased IC or 80C area. A
`manufacturable method for realizing this approach is to ver-
`tically stack ICs using direct bonding and to form vertical
`interconnect structures using conventional wafer fabrication
`techniques including wafer thinning, photolithography mask-
`ing, via etching, and interconnect metallization. The vertical
`electrical interconnection between stacked ICs can be formed
`
`as a direct result of the direct bonded stacking or as a result of
`a sequence of wafer fabrication techniques after direct
`bonded stacking.
`The cost of the vertical interconnection portion of this
`approach is directly related to the number of photolithogra-
`phy masking levels required to etch vias and form electrical
`interconnects. It is thus desirable to minimize the number of
`
`photolithography masking levels required to form the vertical
`interconnection.
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`One version of vertical stacking and vertical interconnec-
`tion is where ICs (on a substrate) are bonded face-to-face, or
`IC-side to IC-side. This version may be done in a wafer-to-
`wafer format, but is typically preferably done in a die-to-
`wafer format where die are bonded IC-side down, to a wafer
`IC-side up to allow the stacking of Known Good Die to
`improve yield. The vertical interconnection may be formed as
`a direct result of the stacking, for example as described in
`application Ser. No. 10/359,608, or as a result ofa sequence of
`wafer fabrication techniques after direct bonded stacking.
`The sequence of wafer fabrication techniques after direct
`bonded stacking typically includes the following. The die are
`typically substantially thinned by removing most of the die
`substrate. The die substrate can not, in general, be totally
`removed due to the location of transistors in the substrate, as
`is the case, for example in bulk CMOS ICs. The substrate is
`thus typically removed to the greatest extent practicable, leav-
`ing sufficient residual substrate to avoid damage to the tran-
`sistors. An interconnection to the die IC is then formed by
`etching a via through the remaining substrate to an intercon-
`nection location in the die IC, such that there are no necessary
`transistors in the vicinity of this via. It is furthermore prefer-
`able, in order to achieve the highest interconnection density,
`to continue this via through the entire die-IC and into the
`wafer-IC to an interconnection location in the wafer IC. This
`
`via typically extends through an insulating dielectric material
`that provides desired electrical isolation from interconnection
`locations in the die IC and wafer IC and exposes desired
`electrical connection locations in the die IC and wafer IC.
`After the formation of this via, a vertical interconnection can
`be made with a conductive material to exposed desired elec-
`trical connection locations in the die IC and wafer IC. An
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`insulating layer between the conductive material and the
`exposed substrate on the via sidewall may be used to avoid
`undesired electrical conduction between the conductive
`material and the substrate.
`
`The fabrication of this structure typically takes four pho-
`tolithography masking levels to build. These levels are 1) via
`etch through substrate, 2) via etch through insulating dielec-
`tric material in the die IC and wafer IC that exposes desired
`conductive material in the die IC and wafer IC, 3) via etch
`through a subsequently deposited insulating layer that elec-
`trically isolates the conductive material that interconnects the
`interconnect location in the die IC with the interconnect loca-
`
`tion in the wafer IC to the exposed substrate via sidewall that
`exposes desired conductive material in the die IC and wafer
`IC, 4) interconnection with conductive material between
`exposed interconnection point in the die IC with exposed
`interconnection point in the wafer IC.
`The patterns defining the via etching through the insulating
`(dielectric) material(s) are typically smaller than the pattern
`defining the via etch through the substrate to adequately
`expose the interconnection points in the die IC and wafer IC
`and to avoid removing insulating material on the substrate via
`sidewall. Since these patterns are formed after the via in the
`substrate, this patterning is typically done at a lower topo-
`graphical level that the patterning of the substrate via. This
`results in a patterning over a non-planar structure that limits
`the scaling of the structure to very small feature size that is
`desirable to achieve the highest interconnection density and
`consumes the least possible silicon substrate where func-
`tional transistors would otherwise reside.
`
`It is thus desirable to have a device that comprises a struc-
`ture and a method to fabricate said structure requiring a
`reduced number of masking steps and masking steps that can
`be realized on a planar surface, at the highest, or one of the
`highest, levels of topography in the structure. It is further
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`TSMC1001
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`IPR of U.S. Pat. No. 7,485,968
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`TSMC1001
`IPR of U.S. Pat. No. 7,485,968
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`US 7,485,968 B2
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`3
`desirable to have a device that comprises a structure and a
`method to fabricate said structure whereby a minimum con-
`sumption of silicon where functional transistors would oth-
`erwise reside is achieved.
`
`SUMMARY OF THE INVENTION
`
`The present invention is directed to a method of three-
`dimensional device integration and a three-dimensionally
`integrated device.
`In one example of the method, a first element having a first
`contact structure is integrated with a second element having a
`second contact structure. The method may include the steps
`of forming a via in the first element exposed to at least the first
`contact structure, forming a conductive material in the via and
`connected to at least the first contact structure, and bonding
`the first element to the second element such that one of the
`
`first contact structure and the conductive material is directly
`connected to the second contact structure.
`
`In a second example the method may include the steps of
`forming a via in a first element, forming a first conductive
`material in the via, connecting the first conductive material to
`the first contact structure, and bonding the first element to the
`second element such that one of the first contact structure and
`
`the first conductive material is directly connected to the sec-
`ond contact structure.
`
`In a third example, the method includes the steps of form-
`ing a via in a first element having a first substrate, forming a
`conductive material in the via, forming a contact structure in
`the first element electrically connected to the conductive
`material after forming the via and the conductive material,
`forming a second element having at least one second contact
`structure, removing a portion of the first substrate to expose
`the via and the conductive material, bonding the first substrate
`to the second substrate, and forming a connection between the
`second contact structure and one of the first contact structure
`
`and the conductive material as a part of the bonding step.
`In one example of an integrated structure according to the
`invention, a first element has a first contact structure, a second
`element has a second contact structure, a first via is formed in
`the first element, a first conductive material is formed in the
`first via connected to the first contact structure, and the first
`element is bonded to the second element such that one of the
`first conductive material and the first contact structure is
`
`directly connected to the second contact structure.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`A more complete appreciation ofthe present invention and
`many attendant advantages thereofwill be readily obtained as
`the same becomes better understood by reference to the fol-
`lowing detailed description when considered in connection
`with the accompanying drawings, wherein:
`FIG. 1 is a diagram showing die to be bonded face-down to
`a wafer face-up;
`FIG. 2A is a diagram of die bonded to a substrate;
`FIG. 2B is a diagram of die bonded to a substrate with a
`portion of the substrate of the die removed;
`FIG. 2C is a diagram of a substrate bonded to another
`substrate;
`FIG. 3A is a diagram showing formation ofa dielectric film
`and mask layer over the structure of FIG. 2A;
`FIG. 3B is a diagram showing formation a dielectric film
`and mask layer after forming a planarizing material;
`FIG. 4 is a diagram showing apertures formed in the dielec-
`tric film and mask layer of FIGS. 3A and 3B;
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`FIG. 5 is a diagram showing etching of the die using the
`aperture formed as shown in FIG. 4;
`FIG. 6A is a diagram showing further etching to expose
`contact structures in the die and wafer;
`FIG. 6B is a diagram of a process modification including
`forming a hard mask;
`FIG. 7A is a diagram ofa section ofthe structure ofFIG. 6A
`after formation of a conformal insulative sidewall layer;
`FIG. 7B is a variation of the embodiment where the hard
`mask is removed;
`FIG. 8A is a diagram showing anisotropic etching of a
`conformal insulative sidewall layer;
`FIG. 8B is a variation of the embodiment where the hard
`mask is removed;
`FIGS. 8C-8F illustrate variations in forming a conformal
`film in the bonded structure;
`FIGS. 8G-8J illustrate the structures shown in FIGS. 8C-8J
`
`after etching the conformal film, respectively;
`FIG. 8K illustrates an alternative manner of forming a
`sidewall film in the bond structure;
`FIG. 9A is a diagram showing forming a metal contact
`comprising a metal seed layer and a metal fill;
`FIG. 9B is a variation of the embodiment where the hard
`mask is removed;
`FIG. 9C is a variation of the embodiment where no seed
`
`layer is formed;
`FIG. 10A is a diagram of the structure of FIG. 9A or 9B
`after chemo-mechanical polishing;
`FIG. 10B is a diagram of the structure of FIG. 9C after
`chemo-mechanical polishing;
`FIGS. 10C-10F are diagrams illustrating alternative meth-
`ods of filling a cavity in the bonded structure;
`FIG. 11 is a diagram illustrating metallization of the struc-
`ture of FIG. 10A;
`FIG. 12 is a diagram of a second embodiment using a mask
`layer without an intervening dielectric layer;
`FIG. 13 is a diagram showing forming a metal contact in
`the second embodiment;
`FIG. 14 is a diagram showing the structure of FIG. 13 after
`chemo-mechanical polishing;
`FIG. 15 is a diagram illustrating another embodiment ofthe
`invention;
`FIG. 16A is a diagram illustrating an embodiment where a
`contact structure is located in the surface of one of the
`devices;
`FIG. 16B is a diagram of the structure of FIG. 16A after
`further processing;
`FIG. 17 is a diagram showing a device produced using the
`method according to the invention with the structure shown in
`FIGS. 16A and 16B;
`FIG. 18 is a diagram of another embodiment of the inven-
`tion;
`FIG. 19A is a diagram showing a device produced using the
`method according to the invention with the structure shown in
`FIG. 18;
`FIG. 19B illustrates the structure having a planarized mate-
`rial and contact formed over the structure of FIG. 19A;
`FIG. 19C illustrates directly bonded contacts similar to the
`structure of FIG. 19A but without an aperture;
`FIGS. 20A-20H illustrate a fifth embodiment with sidewall
`films;
`FIGS. 21A-21E illustrate a sixth embodiment where the
`
`substrate is substantially completely removed;
`FIGS. 22A-22L illustrate a seventh embodiment of where
`
`vias are formed prior to die singulation;
`FIGS. 23A-23K illustrate an eighth embodiment die are
`mounted top down;
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`IPR of U.S. Pat. No. 7,485,968
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`IPR of U.S. Pat. No. 7,485,968
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`US 7,485,968 B2
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`5
`FIG. 23L illustrates bonding a structure with a filled Via in
`top-down and top-up configurations;
`FIGS. 23M and 23N illustrate bonding a second level of
`die;
`FIG. 23O illustrates wafer-to-wafer bonding;
`FIGS. 24A and 24B illustrate a variation of the eighth
`embodiment where die are mounted top up;
`FIGS. 25A-25F illustrate a ninth embodiment with filled
`
`vias prior to bonding; and
`FIGS. 26A and 26B illustrate a tenth embodiment with
`filled vias and surface contacts.
`
`DETAILED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Referring now to the drawings, in particular FIG. 1, a first
`embodiment of the method according to the invention will be
`described. It is noted here that the drawings are not drawn to
`scale but are drawn to illustrate the concepts of the invention.
`Substrate 10 includes a device region 11 having contact
`structures 12. Substrate 10 may be made of a number of
`materials, such as semiconductor material or insulating mate-
`rial, depending on the desired application. Typically, sub-
`strate 10 is made of silicon or III-V materials. Contact struc-
`
`tures 12 are typically metal pads or interconnect structures
`making contact to device or circuit structures (not shown)
`formed in substrate 10. Substrate 10 may also contain an
`integrated circuit to which the contact structures 12 are con-
`nected, and substrate 10 may be a module containing only
`contact structures. For example, substrate 10 may be a mod-
`ule for interconnecting structures bonded to substrate 10, or
`bringing out connections for packaging or integration with
`other modules or circuit structures on, for example, a printed
`circuit board. The module may be made of insulative materi-
`als such as quartz, ceramic, BeO, or AlN.
`Positioned for bonding to substrate 10 on surface 13 are
`three separated die 14-16. Each die has a substrate portion 19,
`a device region 18 and contact structures 17. The die may be
`previously separated from another wafer by dicing, etc. Die
`14-16 may be made of a number of materials, such as semi-
`conductor materials, depending on the desired application.
`Typically, the substrate is made of silicon or III-V materials.
`Contact structures 17 are typically metal pads or interconnect
`structures making contact to device or circuit structures
`formed in device region 18. The sizes of contact structures 12
`and 17 each may vary. The typical range of contact structure
`size is between 1 and 20 microns, but the sizes and relative
`sizes may be outside this range depending upon alignment
`tolerances, circuit design parameters or other factors. The
`sizes of the contact structures are drawn to illustrate the
`
`inventive concepts are and are not meant to be limiting.
`Device region 18 may also contain an integrated circuit to
`which the contact structures 17 are connected. Substantially
`all of substrate portion 19 may be removed, leaving a layer of
`devices, a circuit, or a circuit layer. Also, the substrates of dies
`14-16 may be thinned after bonding to a desired thickness.
`Die 14-16 may be ofthe same technology as wafer 10, or of
`different technology. Die 14-16 may each be the same or
`different devices or materials. Each of die 14-16 has conduc-
`
`tive structures 17 formed in a device region 18. Structures 17
`are spaced apart to leave a gap therebetween, or may be a
`single structure with an aperture which may extend across the
`entire contact structure. In other words, the aperture may be a
`hole in contact structure or may divide the contact structure in
`two. The size ofthe gap or aperture may be determined by the
`photolithographic design rules for the particular technology
`being bonded. For example, a minimum lateral width of con-
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`tact structures 12 and 17 may be required to subsequently
`form a reliable,
`low resistance electrical connection with
`interconnect metal
`
`An additional factor that determines the optimum size of
`the gap or aperture is a ratio of a distance given by the vertical
`separation between contact structures 17 and 12 plus the
`thickness of the contact structure 17 to the size of the gap or
`aperture. This defines an aspect ratio of a via that will subse-
`quently be formed between contact structures 17 and 12 to
`enable an electrical interconnection between contact struc-
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`tures 17 and 12. This vertical separation is typically l-5
`microns, or less, for oxide to oxide direct bonding, as
`described in application Ser. No. 09/505,283, the contents of
`which are incorporated herein by reference, or potentially
`zero for metal direct bonding, as described in application Ser.
`No. 10/359,608, the contents of which are herein incorpo-
`rated by reference. Furthermore, the contact structure 17
`thickness is typically 0.5 to 5 microns. With a typical desired
`via aspect ratio of 0.5 to 5 depending on the process technol-
`ogy used, a typical range of the size of the gap is 03-20
`microns for oxide to oxide bonding or ~0.l-10 microns for
`metal direct bonding. The metal direct bonding case is
`described below in the fourth embodiment.
`
`Dies 14-16 are generally aligned with the contact struc-
`tures 12 such that structures 17 and the gap or aperture are
`positioned over corresponding contact structures 12. The size
`of contact structures 12 is chosen to allow die 14-16 to be
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`simply aligned with the gap between contact structures 17.
`This size depends on the alignment accuracy of the method
`used to place die 14-16 on substrate 10. Typical methods
`using commercially available production tools allow align-
`ment accuracies in the range of 1-10 microns, although future
`improvements in these tools is likely to result in smaller
`alignment accuracies. The lateral extent of contact structures
`17 exterior to the gap or aperture is preferably at least a
`distance given by this alignment accuracy.
`Although only one set of contact structures 17 is shown for
`each die 14-16, it is understood that the lateral extent of
`contact structures 17 is typically much smaller than the lateral
`extent of each die 14-16, so that each die may have several or
`a very large number of contact structures 17. For example,
`contact structures