`
`.-.,_.1,4A
`
`Escort Ex. 2076, pg. 1
`
`Escort Ex. 2076, pg. 1
`
`

`

`GEC PLESSEY
`
`JUNE 1995
`
`L ‘4 SEMIFONDUCTURS
`
`
`ADVANCE INFORMATION
`034056 - 24
`
`GLOBAL POSITIONING SYSTEM RECEIVER RF FRONT END
`
`GP2010
`
`GP2010
`
`Up 3+
`
`IF Output
`PLL Filter 1
`PLL Filter 2
`
`VEE (030)
`Vac (033i
`VEE (050)
`vEE (REG)
`PREF
`PRESET
`VEE (IO)
`CLK
`MAG
`
`SIGN
`OPCIK~
`OPClK+
`
`V00 ('0)
`PDN
`TEST
`LD
`
`VEE (DIG)
`AGC -
`AGC +
`
`Vcc (DEG)
`REF 2
`REF 1
`
`Vcc (RF)
`VEE (RF)
`V55 (RF)
`RF Input
`vEE (RF)
`vEE (RF)
`Vcc (RF)
`O/P 1-
`O/P 1+
`
`vCC (2)
`IIP 2—
`IfP 2+
`
`VEE (IF)
`VEE (IF)
`O/P 2-
`O/P 2+
`
`Vcc (3)
`VP 3-
`
`The GP2010 is GEC Plessey Semiconductors' second
`generation RF Front-end forGIobaI Positioning System (GPS)
`receivers. The GP2010 uses many innovative design
`techniques and a leading-edge bipolar process to offer a
`lower power. lower cost and higher reliability RF solution than
`existing discrete or gallium—arsenide designs. The GP2010 is
`designed to operate from either 3 or 5 Volt power supplies.
`
`The input to the device is the L1 (1575.42MH2) Coarse-
`Acquisition (CIA) code Global Positioning signal from an
`antenna (via a low-noise pro-amplifier). The output is 2—bit
`quantised for subsequent signal processing In the digital
`domain. The GP2010contains an on-chip synthesiser, mixers,
`A60 and a quantiser which provides Sign and Magnitude
`digital outputs. A minimum of external components is required
`to make a complete GPS front—end.
`
`The device has been designed to operate with the GP2021
`12-channel Global Positioning Correlator. and DW9255 SAW I
`filter, both also available from GEC Plessey Semiconductors.
`
`FEATURES
`
`I Low Voltage Operation (3V - 5V)
`
`I Low Power — 200thyp. (3V supply)
`
`I CIA Code Compatible
`
`I On-chip PLL including Complete VCO
`
`I Triple Conversion Receiver
`
`I 44-Lead Surface Mount Quad Flat—Pack Package
`
`I Sign and Magnitude Digital Outputs
`
`I Compatible with GP2021 CMOS Correlator
`
`APPLICATIONS
`
`I CIA Code Global Positioning by Satellite Receivers
`I Time Standards
`
`I Navigation
`
`I Surveying
`
`ORDERING INFORMATION
`The GP201 0 is available in 44 pin Quad Flat pack (guilwing
`formed leads) in both Commercial (0°C to +70°C) and Indus-
`trial (-40°C to +85°C) grades. The ordering codes below are
`for standard screened devices.
`
`GP2010 IG GPBR Industrial — Plastic 44-pin PQFP
`
`Fig. 1 Pin connections - top View
`
`RELATED PRODUCTS AND PUBLICATIONS
`Data
`
`35.42MH2 SAW Filter
`
`Twelve-Channel Correlator
`
`D83861
`
`084057
`
`054004
`
`ORDERING CODE
`GP2010 CG GPBR Commercial . Plastic 44-pin PQFP
`
`GPSBuilder Twelve-Channel GPS receiver
`
`development system
`
`Escort Ex. 2076, pg. 2
`
`Escort Ex. 2076, pg. 2
`
`

`

`GP2010
`
`ABSOLUTE MAXIMUM RATINGS
`(Non-simultaneous)
`W
`Max. Supply Voltage
`+15dBm
`Max. RF Input
`VchD + 0.5V
`Max. voltage on any pin
`except LD (pin 19) and PReset (pin 9), which are 55'};
`Min. voltage on any pin
`VEE - 0.5V
`Storage Temperature
`65°C to +150°C
`Operation Junction Temperature
`-40°C to +150°C
`10MHz Reference Input
`1.5V pk -pk
`
`ESD PROTECTION
`the most
`The GP2010 device is static sensitive.
`sensitive pins withstand a 750V test by the human body
`model. Therefore. ESD handiing precautions are essential to
`avoid degradation of performance or permanent damage to
`this device.
`
`PRODUCT DESCRIPTION
`The GP2010 is a complete front-end down-converter
`for Global Positioning System (GPS) receivers.
`It is a state-
`of‘the-art design combining an on-chip PLL synthesiser at
`1400MH2. a low-noise amplifier. 3 mixers, and a 2—bit A to D
`converter. The GP2010 receives the 1575.42MHz signal
`transmitted by GPS satellites and converts it to a 4.309MH2
`IF, using a triple down—conversion. The 4.309MH2 IF is
`sampled to produce a 2-bit digital output. It the GP2010 is
`used in conjunction with the GP2021 correlator, then the
`GP2021 provides a sampling clock of5.71 4MHz. This converts
`the IF to a 1.405MHz 2-bit digital output at TTL levels.
`The GP2010 can operate from a single supply from
`+3V (nominal) to +5V (nominal).
`
`A block diagram of the circuit is shown in figure 2.
`
`IF STRIP
`
`The input signal to the GP2010 is the GPS L1 signal
`received via an antenna and a suitable LNA. The L1 input is
`a spread spectrum signal at 1575.42MHz with 1.023Mbps
`BPSK modulation. The signal level at the antenna is about
`-130dBm. spread overa2.046MHz bandwidth, sothe wanted
`signal is actually buried in noise. The high RF input compression
`point of the GP2010 means that with subsequent IF filtering
`it is possible to reject large out of band jamming signals, in
`particular 900MHz as used by mobile telephones.The on-chip
`PLL generates the first Iocal-oscillatorfrequency at 1400MHz.
`The output of the front-end mixer (Stage 1) at 175.42 MHz can
`then be filtered before being applied tothe second stage. The
`double-balanced stage 1 mixer outputs are open-collectors,
`and require external dc bias to Vcc-
`_
`The second stage contains further gain and a mixer
`with a local osciiiator signal at 140 MHz giving a second IF at
`35.42 MHz. The second stage mixer is also double-balanced
`with open-collector outputs requiring external dc bias to Voc-
`The signai from stage 2 is passed through an external
`filter with a 1 d B bandwidth of 1 .9MH2. The performance ofthis
`fitter is critical to system performance and it is recommended
`that a SAWfilter is used (part number DW9255. also available
`from GEC Plessey Semiconductors). The output of the filter
`then feedsthe main IF amplifier.This includesz AGC amplifiers
`and a third mixer with a local oscillator signal at 31.1 11 MHz
`giving a final IF at 4.309 MHz. There is an on-chip fitter after
`the third mixer which provides filtering centred on 4.309 MHz.
`The IF output, which has 1m output impedance, Is provided
`for test purposes. All of the signals within the IF amplifier are
`differential inciuding the filter inputs and outputs, except the
`IF output (pin 1), to reduce any common mode interference.
`
`{75fi2MH1 FiLTER
`351251141 FILTER
`[11.54) g .....v iflilf‘l‘” . ..
`.. 1341"“
`
`.
`
`'an
`
`RF hput
`
`I
`
`(1575.1?th
`
`FRW
`END
`MIXER
`
`2!!!
`STAGE
`MIXER
`
`AIGC CAPACITOR
`
`"5.13..
`
`.521—...........................
`
`.....................................1
`
`i
`
`.
`
`IEcupu
`(4.3mm)
`
`POWER
`
`PLLFIEFUP
`1WH¢(HEF2}
`
`j“,
`.
`1
`
`PLL
`REFERENCE
`osCILLA'ron
`
`REF 1 UP
`[FDRHEIIM
`muster
`mo
`
`;
`:
`
`(Mrs:
`
`4WHZ CLOCK DIP
`(FOR CORRELATOR
`CHiP)
`{OPCIK u")
`
`its:
`
`BITE
`{TESTI
`
`PWEH-w
`REFERENCE
`liP
`(PREP)
`
`DOWN VF
`“30")
`
`POWER-ON
`RESET UP
`[PRESE‘I‘]
`
`me
`: more
`
`SAMPLE
`CLCXL‘K In'P (CLK)
`{5.7mm m;
`
`Fig. 2 Block diagram of GP2010
`
`Escort Ex. 2076, pg. 3
`
`Escort Ex. 2076, pg. 3
`
`

`

`The IF output is fed to a 2-bit quantiser which provides
`sign and magnitude (M88 and LSB) outputs. The magnitude
`datacontrols the AGC loop, such thaton averagethe magnitude
`bit is set (high) 30% of the time. The AGC time constant is set
`by an external capacitor.
`The sign and magnitude data, SIGN (pin 13) and MAG (pin
`12), are latched by the rising edge of the sample clock, CLK
`(pin 11). which is normally derived from the correlator; the
`GP2021 provides a 5.714MH2 (=40/7) clock, giving a sampled
`IF centred on 1.405MH2.
`The Digital interface circuits use a separate power-supply.
`VDD(IO), which would normally be shared with the correlatorto
`minimise crosstalk between the analog and digital sections of
`the device.
`
`ON-CHIP PHASE-LOCKED LOOP SYNTHESISEH
`All of the local oscillator signals are derived from an on
`chip phase locked loop synthesiser. This includes a 1400MH2
`VCO complete with on-chip tank circuit. dividers and phase
`detector, with external loop filter components, A 10.000MHz
`reference frequency is required for the PLL. This can be
`achieved by attaching an external 10.000MH2 crystal to the
`on-chlp PLL reference oscillator (see figure 5). However in
`most applicationsthe userwill need an external source, such
`as a TCXO, to provide greater frequency stability (see figure
`6). An external reference should be ac coupled to REF2 (pin
`24); REF 1 (pin 25) should be left open circuit.
`The three local oscillator signals 1400MH2, 140.0MH2
`and 31.11MHz are derived from the 14OOMHz synthesiser
`output. The synthesiser also provides a 40 MHz balanced
`differential output clock (pins 14 & 15) which can be used to
`clock the GP2021 correlator. The clock is a low levelditferential
`
`signal which helps minimise interference with the analog
`areas of the circuit. A PLL lock—detect output, LD (pin 19). is
`also provided, which is logic high when the PLL is phase-
`Iocked to the 10.000MH2 reference signal.
`The VCO power-supply incorporates an on—chip
`regulator to improve the noise-immunity of the PLL. This
`feature is only available when operating with a 5 volt (nominal)
`supply which is regulated to 3.3 volts internally. This internal
`regulated supply is referenced to VCC(OSC) (pin 5). Figure 7
`shOWs the required connections for both 3 volt and 5 volt
`operation.
`Afurtherfeature ofthe circuit isthe TEST input (pin 18).
`When this input is held high the PLL is unlocked with the VCO
`at its maximum frequency.
`
`GP2010
`
`POWER-DOWN CAPABILITY
`
`A power down function is provided on the GP2010, to
`limit power consumption. This powers down the majority of
`the circuit except the "power-on reset” function (see below).
`If the power down feature is not required, the Power-
`down input, P0,, (pin 17). should be connected to 0V dc
`(=Vee/Ground).
`
`POWER-0N RESET FUNCTION
`The GP2010 includes a voltage detector which
`operates from the digital interface supply. This circuit is used
`to produce a TTL logic low output while the GPS receiver
`power supply is switching on, and produces a logic high
`output when the pOWersupply voltage has achieved a nominal
`value. This output can be used to disable the GP2021
`correlatorwhile the power supply is switching on. An internal
`bandgap reference of approximately +1.21V is compared
`with the voltage on a sense pin, PFIEF (pin 8); when the
`voltage on this pin exceeds the reference, a TTL logic high
`level appears at the Power—on Reset output, PFIESET (pin 9).
`Thus, if the sense input voltage is derived from an external
`resistive divider from the Digital Interface supply, VDD(IO) (pin
`15), Such thatthe sense voltage at nominal Vcc is VS, then the
`supply threshold, Vcc(thresh), at which the PRESET output
`goes to logic high is:-
`
`Vs = Vcc (nom) x 1.21
`
`Vcc (thresh)
`
`For a Vcc (nom) of 5.0V, VCC (thresh) may be set to approx.
`4.0V, giving VS of 1.5V.
`
`For a Vcc (nom) of 3.0V, VCC (thresh) may be set to approx.
`2.4V, giving V5 of 1.5V.
`
`ADDfTIONAL INFORMATION
`All the digital inputs and outputs can use a separate
`power supply to help prevent digital switching transitions
`interacting with the analog sections of the device, and as an
`additional precaution, the digital inputs and outputs are on
`the opposite side of the device to the critical analog pins.
`
`ii
`
`Escort Ex. 2076, pg. 4
`
`Escort Ex. 2076, pg. 4
`
`

`

`GP2010
`
`ELECTRICAL CHARACTERISTICS
`The Electrical Characteristics are guaranteed over the following range of operating conditions (see Fig. 3 for test circuit):
`TAMB = 0°C to +70°C
`Commercial (0) grade:
`T
`- -40°C to +85°C
`ave “
`Industrial (i) grade:
`Vcc and Voo = +2.7V to +5.5V (both grades)
`Supply voltage:
`Test conditions (unless otherwise stated):
`VCC = +2.7V and +5.5V, VDD = +2.7V and +5.5V
`Supply voltages:
`+25°C
`Commercial (C) grade product:
`Test temperature:
`+25°C
`Industrial (I) grade product:
`
`Characteristic
`
`Conditions
`
`SUPPLY CURRENT
`Normal mode — Analog interface
`- Digital interface '
`Power down mode - Analog interface
`- Digital interface
`Power Supply Differential
`Power down Response time
`
`Pins 5, 23, 26, 32, 35, 42
`Pin 16
`Pine 5, 23, 26, 32. 35, 42
`Pin 16
`Between any Vcc/Vno pins (Note 7)
`(Note 7)
`
`tokHz Loop Bandwidth
`
`IF STRIP
`Front EndfMixer 1
`Conversion Gain (G1)
`
`Noise Figure
`Input Compression (1dB)
`Input Impedance
`
`Differential Output Impedance
`
`RF Input Image Rejection
`
`Stage 2/Mixer 2
`Conversion Gain (G2)
`input Compression (IdB)
`Differential Input Impedance
`
`Differential Output Impedance
`
`Stage 3
`High Gain (In terms of total strip)
`High Gain (GB)
`Gain Control Range
`Differential Input Impedance
`IF Output amplitude
`IF Output impedance
`4.3MHz Fiiter Response
`Flatness 4.3 i 1MHz
`Rejection @ 0.5MH2
`@ SOMHz
`
`2 BIT QUANTISER
`Sign Duty Cycle
`Mag Duty Cycle
`AGC Time Constant
`
`0N_CHIP PLL SYNTHESISER
`Phase Noise
`i IkHz
`: ‘IOkHz
`:t TOOkHZ
`i 50MH2
`
`no = soon (Note 2)
`FIN = 1575.42MHZ
`23 = 509 (Note 7)
`
`Pin 29 (Notes 1 and 7)
`(Notes 1 and 7)
`Pine 33 & 34 (Note 8)
`(Note 12)
`
`FIN = 175.42MHZ
`
`Pins 36 & 37 (Note 8)
`(Note 12)
`Pins 40 & 41 (Note 8)
`(Note 12)
`
`(Note 6)
`FM = 35.42MHZ
`
`Pins 43 8: 44 (Note 8)
`CW input (Note 3)
`Pin 1(Note 8)
`
`(Note 7 and 9)
`
`} (Note 10)
`
`Case = 100nF (Note 12)
`
`PLL Spurs
`
`Escort Ex. 2076, pg. 5
`
`Escort Ex. 2076, pg. 5
`
`

`

`GP2010
`
`240 MHz/V
`
`
`
`(Note)4)
`
`
`—alue
`—WW-
`Characteristic
`
`
`“-
`
`
`VCO regulator output voltage
`
`VCO Gain
`
`
`Phase Detector Gain
`
`
`10MHz Reference Input
`
`10MHz Reference input impedance
`
`
`
`
` From Power up (Note 7)
`PLL Lockup Time
`
`(Note 7)
`PLL Loop Gain
`
`
`
`
` 'IGITAL INTERFACES
`Pins 11, 17, 18
`Sample Clock, Power Down,
`
`Test Inputs.
`
`
`
`
` VIH = Voo
`input Current High lIH
`
`
`VIL = VEE
`Input Current Low llL
`
`
`Pins 13, 12
`Sign/Mag Outputs
`
`‘0 = -0.5mA
`IO = 0.5mA
`
`
`CL = 15pF, RL = 15kt) (Note 7)
`Sample Clock to Sign/Mag Delay
`
`
`40MH2 Clock Output
`
`
`Pins 14 & 15
`High Level (VOH)
`
`
`
`(Note 5)
`Low Level (VOL)
`
`
`
`01. = 15pF (GND) (Note 7)
`Output (differential)
`CL
`5 F(Dilf) (Note 7)
`
`=
`P
`
`Duty Cycle
`
`
`
`Pins 19 and 9
`
`
`LD (PLL Lock)/PRESET Outputs
`Low Level (VOL) (UNLOCKED)
`
`
`High Level (VOH) (LOCKED)
`IO = “1 OHA
`
`
`
`
` Pin 8
`Power-on reset comparator input
`Power Reset Threshold Level
`
`
`Power Reset Reference Input Current
`
`
`
`
`Notes On Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output
`impedances, such as balun transformers. and levels refer to matched 500hm ports (see figure 3 for test circuit)
`
`P’P‘PPNT‘
`
`RF input impedance (series) without input matching components connected.
`Input matched to SOohrn. output loaded with (5000th differential
`Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms.
`VCO regulator voltage measured with respect to Vcc (OSC) - pin 5.
`The processor clock outputs are differential and are referenced to Voo-
`Minimum galn requirement expressions:
`
`-7dBm <174dBrn/Hz +19dB + G1 + G2 + G3- 21dB + 53dB
`where ~7dBm = typical lF Output level with AGC active
`-174dBm/Hz = background noise level at RF input
`19dB = sum of LNA gain and noise figure
`~21dB = total loss in 175MHz and 35MHz filters
`BSdB = summation of noise over a 2MHz bandwidth
`
`7.
`
`Rearranging the above expression gives (31 + G2 + G3 > 106dB.
`This parameter is not production tested.
`8. This impedance is toleranced at +/-30% and is not production tested.
`9. Roll off occurs in on~chip capacitive coupling IF Output to input of ADC circuit. Not measurable at [F Output.
`10. CW input on pins 43 at 44 of 35.42MH2 at 7mV ms.
`11. This input impedance applies to the typical input level. The impedance is level dependent and is not tested orguaranteed.
`12. This parameter is not yet characterised.
`Escort Ex. 2076, pg. 6
`
`5
`
`Escort Ex. 2076, pg. 6
`
`

`

`GP2010
`
`PIN DESCRIPTIONS
`All VEE and Vac/V00 pins should be connected to ensure reliable operation
`
`
`
`1
`
`lFOutput
`
`Output
`
`Connected to the bias network within the on-chip VCO. An
`external PLL loop fitter network should be connected between
`this pin and PLL Filt 2 (see below).
`
`
`
`Negative supply to the on-chip VCO. (See Note 1)
`
`
`
`IF Test output.
`Connected to output of Stage 3 prior to the A to D converter.
`A series 1k!) resistor is incorporated for buffering purposes.
`
`PLL Filter 1.
`
`
`
`PLL Filter 2.
`
`
`Connected to the varactor diodes within the onvchip VCO. An
`external PLL loop filter network should be Connected between
`
`
`this pin and PLL Filt 1 (see above).
`
`
`
`
`
`
` Power-on Reset Output.
`
`
` Magnitude bit data output.
`
`
`
`
`
` 40MHz Clock output - inverse phase.
`
`
`
`
`
`
`
`
`
`
`
`PLL Fm
`
`PLL Filt2
`
`Output
`
`VEE (080)
`
`Vcc (OSC) _nput
`
`
`
`l__put
`VEE(REG)
`
`PREF _nput
`
`-CLKPRESET_ VEE (10)
`
`
`
`
`
`
`
`
`
`input
`
`SIGN
`
`0P0”?
`
`open“
`
`
`
`Positive supply to the on-chip VCO.
`
`NegativesupplytotheVCOregulator.
`Power-onResetReferenceinput.
`
`This must be connected to GND.
`
`
`
`An on-chip comparator produces a logic Hl when the PRef
`input voltage exceeds +1 .21V.
`
`A TI'L compatible output controlled by the Power—on reset
`comparator (See above). This output remains active even
`when the chip is powered down. (See pin 17 - PDn).
`
`Negative supply to the Digital Interface. (See Note 2)
`Sample Clock input from the correlator chip.
`A TTL compatible input (which operates at 5.714MH2 if used
`with GP2021 correlatordevice) used to clock the MAG & SIGN
`output latches, on the rising edge of the CLK signal.
`
`
`
`A TTL compatible signal, representing the magnitude of the
`mixed down IF signal. Derived from the on—chip 2-bit A to D
`converter, synchronised to the CLK input clock signal.
`
`Sign bit data output.
`A Tl'L compatible signal. representing the poiarityof the mixed
`down IF signal. Derived from the on-chip 2-bit A to D converter,
`synchronised to the CLK input clock signal.
`
`
`
`One side of a balanced differential output clock, with opposite
`polarity to Pin 15 - OP Cit-u». Used to drive a master-clock signal
`within the correlator chip.
`
`4OMHz Clock output - true phase.
`Other side of a balanced differential output clock set, with
`opposite polarity to Pin 14 - OPClk-. Used to drive a master-
`clock signal within the correlator chip.
`
`Positive supply to the Digital Interface. (See Note 2)
`
`Escort Ex. 2076, pg. 7
`
`Escort Ex. 2076, pg. 7
`
`

`

`
`
`17
`
`Input
`
`
`
`
`m Signal Name
`
`input/Output
`
`Description
`
`GP2010
`
`Power-Down control input.
`
`
`A TTL compatible input. which when set to iogic high, will
`
`disable ALL of the GP201 0 functions, except the power-on
`
`reset block. Useful to reduce the total power consumption of
`
`
`the GP2010. If this feature is not required, the pin should be
`
`
`connected to 0V (VEE/GND).
`
`
`
`Test control input ~ Disable PLL.
`
`A TTL compatible input, which when set to logic high. will
`
`disable the on—chip PLL, by disconnecting the divided~down
`VCO signal to the phase-detector. The VCO will free run at its
`upper range of frequency operation. If this feature is not
`required, the pin should be connected to 0V (VEE/GND).
`
`
`
`I
`
`
`
`
`18
`
`TEST
`
`Input
`
`LD
`
`Output
`
`— VEE (DIG)
`
`21
`
`22
`
`A60
`
`Output
`
`AGC+
`
`Output
`
`
`
`_ Vcc (DIG)
`
`24
`
`REF 2
`
`input
`
`‘
`
`25
`
`REF 1
`
`input
`
`
`
`26, 32
`
`Vcc (RF)
`
`input
`
`VEE (RF)
`
`Input
`
`27, 28,
`30, 31
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PLL Lock Detect output.
`A TTL compatible output, which indicates if the PLL is phase—
`iocked to the PLL reference oscillator. Will become logic high
`only when phase-lock is achieved.
`
`Negative supply to the PLL and A to D converter.
`
`AGC Capacitor output - inverse phase.
`One side of a balanced output from the AGC block within lF
`Stage 3, to which an external capacitor is connected to set the
`AGC time-constant.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`AGC Capacitor output - true phase.
`One side of a balanced output from the AGC block within iF
`Stage 3,10 which an external capacitor is connected to set the
`AGC time-constant.
`
`Positive supply to the PLL and A to D converter.
`
`10.000MH2 PLL Reference signal input .
`Input to which an externally generated 10.000MH2 PLL
`reference signal should be ac coupled. if an external PLL
`reference frequency source (e.g TCXO) is used (see fig. 6).
`If no external reference is used, this pin forms part of the on-
`chip PLL reference oscillator, in conjunction with an external
`10.000MHZ crystal (see fig. 5).
`
`
`
`
`
`
`
`
`
`
`
`
`PLL reference oscillator auxiliary connection.
`Used in conjunction with Pin 24 (REF 2) to allow a 10.000MH2
`external crystal to provide the PLL reference signal it no
`external PLL reference frequency source (e.g TCXO) is used.
`
`
`This pin should NOT be connected if an external TCXO is
`being used (see fig. 5).
`
`
`
`Positive supply to the RF input and Stage 1 IF mixer.
`Both pins 26 & 32 (Vcc (RF)) are connected internally, but
`must both be connected to VCC externally, to keep series
`inductance to a minimum.
`
`
`
`
`
`
`
`
`
`
`
`
`Negative supply to the RF input and Stage 1 IF mixer.
`Pins 27, 28, 30 & 31 are all connected internally, but must ALL
`be connected to 0V (VEE/GN D) externally, to keep series
`inductance to a minimum.
`
`Escort Ex. 2076, pg. 8
`
`7
`
`Escort Ex. 2076, pg. 8
`
`

`

`GP201 0
`
`m Signal Name
`
`Input/Output
`
`29
`
`RF Input
`
`Input
`
`CUP 1-
`
`O/P 1+
`
`Output
`
`
`
`
`
`
`
`—n_nput
`UP 2- —nput
`
`
`:- UP2+
`
`
`
`38, 39
`
`VEEt IF)
`
`O/P 2-
`
`Output
`
`Description
`
`
`
`
`
`
`
`
`
`
`
`FiF input.
`The GPS RF input signal @ 1575.42MH2 from an external
`
`antenna with LNA and filter is connected to this pin via an
`
`
`input-matching network (see fig.4).
`
`
`
`Stage 1 mixer output @ 175.42MH2 — inverse phase.
`One of a balanced output from first stage IF mixer, to which
`
`one input of an external balanced 175MHz bandpass filter is
`connected. External dc biasing is required via an inductor
`connected to VCC(RF) - the value of which is dependent on the
`filter used.
`
`
`
`
`
`
`
`
`
`Stage 1 mixer output @ 175.42MHz - true phase.
`Second of a balanced output from first stage iF mixer, to which
`the second input of an external balanced 175MHz bandpass
`tiiter is connected. External dc biasing is required via an
`inductor connected to Vcc(FtF) -the value otwhich isdependent
`on the filter used.
`
`Positive supply to the Stage 2 IF mixer.
`Stage2 mixer input@ 175.42MHZ - inverse phase.
`
`
`
`One of a balanced inputto the second stage IF mixer, to which
`one of the balanced signal outputs from the external 175MHz
`bandpass filter is connected.
`
`
`
`
`
`
`
`Stage 2 mixer input @ 175.42MH2 - true phase.
`Second of a balanced input to the second stage IF mixer, to
`which the second of the balanced signal outputs from the
`external 175MHz bandpass filter is connected.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Negative supply to the Stage 2 IF mixer, and Stage 3 IF block.
`
`Stage 2 mixer output @ 35.42MHz - inverse phase.
`One of a balanced output from second stage IF mixer,to which
`one input of an external balanced 35.42MH2 bandpass filter is
`connected. External dc biasing is required via an Inductor
`connected to Vcc.
`(See Note 3)
`
`Stage 2 mixer output @ 35.42MH2 — true phase.
`Second of a balanced output from second stage IF mixer, to
`which the second input of an external baianced 35.42MH2
`bandpass filter is connected. External dc biasing is required
`via an Inductor connected to Vcc.
`(See Note 3)
`
`O/P 2+
`
`Output
`
`
`
`
`Stage 3 mixer input @ 35.42MH2 - inverse phase.
`
`
`One of a balanced input to the third stage IF mixer, to which
`one otthe balanced signaloutputs from the external 35.42MHz
`bandpass filter is connected.
`(See Note 3)
`
`
`
`Stage 3 mixer input @ 35.42MH2 - true phase.
`Second of a balanced input to the third stage IF mixer, to which
`
`
`the second of the balanced signal outputs from the external
`
`35.42MHz bandpass filter is connected. (See Note 3)
`
`
`
`Escort Ex. 2076, pg. 9
`
`Escort Ex. 2076, pg. 9
`
`

`

`Notes on Pin Descriptions
`1). Both pins 4 & 6 (VEE (080)) are connected internally, but must both be connected externally. If the VCO regulator is used
`(Vcc = +5.00V nominal) then pins 4 & 6 must be left floating with a 100nF capacitor to VCC(OSC). In this configuration, the
`dc output level of the regulator can be monitored from VEE(OSC), with respect to_Vcc(OSC) - NOT ON (VEE/GND). For
`operation at Vcc <+4.0V, the VCO regulator cannot be used, and both VEE (030) pins must be shorted to VEE (REG) (Pin
`7) - see Fig. 7.
`
`2). The Dig ita! interface supply is independent from all the other supply pins, allowing supply separation to reduce the likelihood
`of undesirable digital signals interfering with the IF strip.
`
`3). The 35.42MH2 Bandpass filter should have a bandwidth of approx 2.0MH2. Ideally. this should be a DW9255 SAW filter.
`
`GP2010
`
`CONTROL SIGNALS
`
`
`
`
`
`_——
`Power Down
`Normal Operation
`Powered Down
`
`
`Normal Operation
`
`Test
`
`TEST
`
`Stage 1
`Output
`175 MHz
`
`M1 - 4 = Matching
`Networks, incorporating
`Balun transformers
`
`PFIESET PREF
`
`2
`
`9
`
`PLL
`SYNTHESISER
`
`a
`
`14 I'Mo
`o o
`o
`o
`OPClk
`LD REF 2
`
`o
`TEST
`
`PDn
`
`= 470nF
`C1
`= lGnF
`C2
`: 270‘}
`Flt
`Cagc = tOOnF
`Cs
`= SpF
`Op
`= 1.5pF
`
`Fig. 3 GP2010 test circuit
`
`OPERATING NOTES
`A typical application circuit is shown in figure 4 with the
`GP2010 front-end interfaced to the GP2021 12 channel
`correlator integrated circuit. The RF input has an unmatched
`input impedance (see page 4). The RF input matching com-
`ponents Cs and Co should be mounted as close to the RF
`input as possible: also the Vee(FlF) tracks must be kept as
`short as possible. A SAW may be used as a 175.42MHztilter,
`but this can be replaced by a simpler coupled-tuned LC fiiter
`if there is no critical out-of band jamming immunity require-
`ment. The DC bias to mixer 1 is provided via inductors L1 and
`L2, which may form part of the 175.42MH2 filter. The output
`of mixer 2 requires an external dc bias, achieved with inductors
`L3 and L4,whict1 also serve to tune out the input capacitance
`ofthe DWQQSS SAWfilter. The output ofthe SAW is tuned with
`inductor L5. The AGC capacitor (Cagc) determines the AGC
`time-constant. The PLL loop filter components are selected to
`give a PLL loop bandwidth of approx. 10kHz. The IF Output
`is normally used fortest-purposes only, but is available to the
`user if required. In this configuration the device wiil operate
`with an input spectral noise density up to -130dBm/Hz. over
`the L1 CIA spread-spectrum bandwidth of 2 MHZ. Typically a
`
`low noise preamplifier (gain >+15dB) is used, and may be
`located with a remote antenna.
`
`QUALITY AND RELIABILITY
`At GEC Plessey Semiconductors, quality and reliabil—
`ity are built into products by rigorous control of all processing
`operations. and by minimising random, uncontrolled effects in
`all manufacturing operations. Process management involves
`full documentation of procedures, recording of batch-by-
`batch data, using traceability procedures. and the provision of
`appropriate equipment and facilitiesto perform sample screen-
`ing and conformance testing on finished product.
`Acommon information management system is used to
`monitor the manufacturing on GEC Plessey Semiconductors
`CMOS and Bipolar processes. All products benefit from the
`use of an integrated monitoring system throughout all manu-
`facturing operations. leading to high quality standards for all
`technologies.
`Further information is contained in the Quality Bro-
`chure, available from GEO Plessey Semiconductors' Safes
`Offices.
`
`Escort Ex. 2076, pg. 10
`
`9
`
`
`
`Escort Ex. 2076, pg. 10
`
`

`

`GP2010
`
`VALUES FOR L1 AND L2 AFIE
`DEPENDENT ON FILTER USED
`
`RF INPUT
`MATCHING
`Cs = 4.?pF
`Cp = 1.5pF
`
`H4, H5 = 4709
`R6 = 1.5m
`
`FILTER
`
`36 37
`
`4D 41
`
`GP2010 FRONT-END
`44 PIN
`
`0)
`
`(was
`
`
`
`>110dWVSa:
`
`x001‘I‘IdSI
`
`
`
`0009uamoaru
`
`GP2021 CORRELATOR
`80 PIN
`
`Fig. 4 GP2010 typical application
`
`Vcc
`
`|
`
`Greg = 0.1UF
`(Vcc 2 +5.0V only)
`
`FIEFZ
`1OMHz UP
`
`PLL LOOP
`FILTER
`C1 = 0.47uF
`F11 z 2700
`
`POWER—ON
`REF
`LADDER
`
`RS =2.7k
`Hz = 2.?k (Vcc : +3.0V)
`
`10.000MHZ
`CRYSTAL
`
`= 6.8k (Vcc = +5.0V)
`
`
`
`Fig. 5 Crystal Reference connections
`
`10
`
`Escort Ex. 2076, pg. 11
`
`
`
`Escort Ex. 2076, pg. 11
`
`

`

`GP201D
`
`GP2010
`
`1 CLOOOM Hz
`
`TCXO
`
`RA 81 RB SET TO REDUCE TCXO
`
`Hg. 6 TCXO Reference connections
`
`O/P TO REQUIRED LEVEL
`Using VCO regulator with Vcc > +4.0V
`
`(5)
`
`GP201O
`
`(7)
`
`(4)
`
`(6)
`
`0V
`
`No VCO Regulator needed
`
`GP2010
`
`(7)
`
`0V
`
`Fig. 7 VCO power-supply connections
`
`Escort Ex. 2076, pg. 12
`
`11
`
`
`
`Escort Ex. 2076, pg. 12
`
`

`

`GP2010
`
`PACKAGE DETAILS
`Dimensions are shown thus: mm (in).
`
`PIN 1 IDENT
`
`900110-10
`.
`, .
`(oaegérsea)
`
`3-00 0315
`N M.
`
`I
`
`129503-45
`(0-510l0-530)
`
`“ii/L
`
`0-1 SIG-20
`(O'OOGIG-OOB)
`
`1 .9020?
`(Demo-001 )
`
`2.45 (0.095)
`MAX.
`
`0‘73!1 '03
`(002910-04 1)
`
`44-LEAD PLASTIC QUAD FLATPACK —- GP44
`
`,
`,
`0 30:0 45
`(001210073)
`
`144 LEADS AT
`0-50 (0.031}
`NOM. SPACING
`
`,
`_
`0 25Mm"010)
`
`NOTES
`1. Controlling dimensions are millimetres.
`2. This package outline diagram is for guidance only.
`Please contactyour GEC Plessey Semiconductors
`Customer Service Centre for further information.
`
`GEC PLESSEY
`
`
`
`L .—
`HEADQUARTERS OPERATIONS
`GEC PLESSEY SEMICONDUCTORS
`Cheney Manor. Swindon,
`Wiltshire SN2 20W. United Kingdom.
`Tel: (01793) 518000
`Fax: (01793) 518411
`
`CUSTOMER SERVICE CENTRES
`- FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax : (1) 64 46 06 07
`- GERMANY thioh Tel: (089) 3609 06-0 Fax : (089) 3609 06-55
`e
`ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
`JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
`NORTH AMERICA Sootts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023.
`SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
`SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
`GEC PLESSEY SEMICONDUCTORS
`TAIWAN. ROC Taipei Tel: 886 2 5461260. Fax: 886 2 7190260
`PO. Box 560017
`UK, EIRE, DENMARK, FINLAND a. NORWAY
`1500 Green Hills Road.
`Swindon Tel: (01793) 5185270518566 Fax :(01793) 518582
`Scotts Valley. California 95067-0017,
`These are supported by Agents and Distributors in major countries worldwide.
`United States of America.
`© GEC Plessey Semiconductors 1995 Publication No. 084056 Issue No. 2.4 June 1995
`Tel: (408) 438 2900
`TECHNICAL DOCUMENTATION . NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
`Fax: (408) 438 5576
`
`Thispublioation isissued to provide information only which (unless agreed by the Company in writing) may not be used. applied or reproduced tor any purpose narformpert of any order oroomrect earlobe regarded
`as a representation relating tothe products or services concerned No warranty arguarentee express orirnphed is made regarding thecepability, oerforrnanceor suitability of any pdeUdt or service. The Company
`reserves the right to alter without prior notice the spedlicadon, design or price at any product or service.
`Information conoernl rig possible methods of use is provided as a guide only and does not constitute any
`guarantee that such methods at use will be eatist'aclory in a specific piece 01 equipment.
`It is the user‘s responsibility 10 fully determine the periormence and suitability or any equipment using such intermation and
`to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to per-term may result in significant injury
`or death to the user. All products and materials are sold and services provided subject to the Company's oohdifions of sale. which are available on request.
`
`Escort Ex. 2076, pg. 13
`
`Escort Ex. 2076, pg. 13
`
`

`

`The WWW Speedtrap Registry
`
`httpflwww.Nashvilla.NeUspeedtrap
`
`.
`
`3 idealism5-websitie‘fi5r
`infirmon.{team
`an detectionmm
`
`flaImemisfit;lmhle.
`
`Netscape Version 2.0 users can now use the
`JavaScript Enhanced Version
`m
`
`Welcome! to The W Speedtrap Registry. This registry was started in Feb. '95 in an effort to cut
`down the number of speeding tickets resulting from speed traps. The Registry is not meant to be a tool to
`undercut the efforts of law enforcement to keep our roads safe. The Registry is a resource to help drivers
`know where they might encounter speed enforcement so they can adjust their speed to the conditions.
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`
`% D
`
`ue to all of the recent publicity I have a large back log of traps to add. I hope to enlist the help of some
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`%
`
`The WWW Speedtrap Registfl Information Repositofl
`
`% A
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`LABAMA
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`ARKANSAS
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`1 of 5
`
`Escort Ex. 2076, pg. 14
`
`04l22lQG 16:03:12
`
`Escort Ex. 2076, pg. 14
`
`

`

`The W Speedtrap Registry
`
`httpfllwww.Nashville.Net/speedtrap.
`
`CALIFORNIA
`
`MADE).
`
`W p
`
`_._c_,;
`
`DELAWARE
`
`FLORIDA
`
`EMA.
`
`HAWAH
`
`
`IDAHO
`
`.
`
`INDIANA
`
`ILLINOIS
`
`IOWA
`
`KANSAS
`
`KENTUCKY
`
`LOUISIANA
`
`MAINE
`
`W
`
`MASSACHUSETTS
`
`MICHIGAN
`
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`
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`
`MISSOURI
`
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`
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`
`2 of 5
`
`Escort Ex. 2076, pg. 15
`
`04/22/96 16:03:15
`
`Escort Ex. 2076, pg. 15
`
`

`

`TheW Speedtrap Registry
`
`http:/lwww.Nashville.Net/speedtrap
`
`W N
`
`EW JERSEY
`
`NEW MEXICO
`
`NEW YORK
`
`NORTH CAROLINA
`
`NORTH DAKOTA
`
`0—11.12
`
`W O
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`REGON
`
`PENNSYLVANIA
`
`RHODE ISLAND
`
`W w
`
` TENNESSEE
`
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`
`TEXAS
`'
`UTAH
`
`VERMONT
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`VIRGINIA
`
`WASHINGTON
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`WEST VIRGINIA
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`W W
`
`YOMING
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`ARGENTINA
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`AUSTRALIA
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`3 of 5
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`.
`
`04192196 16:03:16
`
`Escort Ex. 2076, pg. 16
`
`Escort Ex. 2076, pg. 16
`
`

`

`http:/fwww.Nashville.Newspeedtrap
`
`The WWW Speedtrap Registry
`
`'
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`
`'
`no!
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`NETHERLANDS
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`sum
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`UNITED KINGDOM
`
`% T
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`
`his page is n