(12) Un1ted States Patent
`(10) Patent No.:
`US 7,462,552 B2
`
`Tong et a].
`(45) Date of Patent:
`Dec. 9, 2008
`
`USOO7462552B2
`
`(54) METHOD OF DETACHABLE DIRECT
`BONDING AT LOW TEMPERATURES
`
`(75)
`
`_
`.
`h
`_
`_
`.
`Inventors gfi'YlT‘l’rnthmlr 211111 §C (118),]???
`(Ulsgnan 0““ am’
`r" oungsw 6’
`'
`
`(73) Assignee: Ziptronix, Inc., Morrisville, NC (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U30 1540’) by 302 days~
`
`(21) Appl.No.: 11/134,359
`
`(22) Filed:
`
`May 23, 2005
`
`(65)
`
`Prior Publication Data
`US 2006/0264004 A1
`NOV. 23, 2006
`
`(51)
`
`Int. Cl.
`(2006.01)
`H0IL 21/46
`(52) us. Cl.
`.............................. 438/458; 257/E2l.567;
`438/455; 438/459
`(58) Field of Classification Search .......... 257/E2l.567;
`438/455, 458, 459
`See application file for complete search history.
`
`(56)
`
`References Cited
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`Primary ExamineriAsok K Sarkar
`(701411077104 Agent, 0” Fir”140131011: Spivak, McClelland,
`Maier & Neustadt, PC.
`
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`ABSTRACT
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`
`A method for detachable bonding that forms an amorphous
`silicon layer, or a silicon oxide layer with a high hydrogen
`content, on an element such as a carrier substrate. A second
`element, such as a substrate,
`is bonded to the amorphous
`silicon layer or silicon oxide layer, and the second element
`may then have a portion removed. A third element, such as a
`host or carrier substrate, is bonded to the second element or to
`the remaining portion ofthe second element to form a bonded
`structure. The bonded structure 15 then heated to cause the first
`element to detach from the bonded structure.
`
`78 Claims, 5 Drawing Sheets
`
`5
`
`5
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`US 7,462,552 B2
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`Page 2
`
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`and Dihydride Species on Silicon Surfaces”, The American Physical
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`
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`US 7,462,552 B2
`Page 3
`
`L. Di Cicoccio et al., “Silicon carbide on insulator formation by the
`Smart-Cut process”, Materials Science Engineering B46, PP. 349-
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`6.3.2, pp. 161-169, Published by John Wiley & Sons, 1999.
`
`* cited by examiner
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`TSMC-1001
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`US. Patent
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`Dec. 9, 2008
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`Sheet 1 of5
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`US 7,462,552 B2
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`
`
`FIG. 1A
`
`FIG. 1B
`
`
`
`3 _2
`1 _
`
`FIG. 2A
`
`3 _ 4
`
`
`
`
`_ F
`
`IG. 28
`
`2 1
`
`4 1
`
`3 — 2
`
`
`
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`TSMC-1001
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`— F
`
`IG. 2C
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`

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`US. Patent
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`Dec. 9, 2008
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`Sheet 2 of5
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`US 7,462,552 B2
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`3A
`
`5
`
`3A _
`
`2 _ 2 —
`
`FIG.3A
`
`FIG.4A
`
`5
`
`3A
`
`2
`
`6
`
`3A ; 6
`
`— 4 _ 4
`
`2
`
`
`1 _ 1 -
`
`FIG. 3B
`
`FIG.4B
`
`3A
`3A — 6
`_ 2
`
`4
`
`
`4
`
`2
`
`FIG. 30
`
`FIG. 40
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`3A\—
`
`3A — 6
`s - 5-
`
`FIG. 6A
`
`FIG. GB
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`TSMC-1001
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`US. Patent
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`Dec. 9, 2008
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`Sheet 3 of5
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`US 7,462,552 B2
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`TSMC-1001
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`US. Patent
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`Dec. 9, 2008
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`Sheet 4 of5
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`US 7,462,552 B2
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`TSMC-1001
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`US. Patent
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`Dec. 9, 2008
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`Sheet 5 of5
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`US 7,462,552 B2
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`
`
`
`
`BondingEnergy(mJ/m2)
`
`3000
`
`NU1 0O
`
`NOOO
`
`.— (AOO
`
`.— OOO
`
`500
`
`0
`
`50
`
`100
`
`150
`
`200
`
`250
`
`Annealing Temperature (C)
`
`FIG. 9
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`US 7,462,552 B2
`
`1
`METHOD OF DETACHABLE DIRECT
`BONDING AT LOW TEMPERATURES
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This application is related to US. application Ser. No.
`10/505,283 filed on Feb. 16, 2000, entitled “Method for Low
`Temperature Bonding and Bonded Structure,” the entire con-
`tents of which are incorporated herein by reference.
`
`DISCUSSION OF THE BACKGROUND
`
`1. Field of the Invention
`This invention relates to a method of detachable direct
`bonding at low temperatures used for thin wafer or die layer
`transfer and the application of such techniques in materials,
`devices, and 3-D (three-dimensional) device integration.
`2. Background of the Invention
`As the scaling limits ofthe conventional bulk silicon device
`are approaching, there is a strong demand to monolithically
`combine a variety of materials to form integrated materials
`for integrated circuits (ICs) with enhanced performances. For
`system-on-a chip (SOC) preparation, a variety of functions
`are required on a chip. Many functions are usually best made
`from their respective materials other than silicon. Therefore,
`integrated materials that combine thin films of dissimilar
`materials on a single wafer are highly desirable. Wafer or die
`direct bonding is one technology to achieve this goal. Usually,
`wafers or dies with thickness that are sufficient for handling
`are bonded at room temperature followed by annealing at
`elevated temperatures to enhance the bond. In order to bond
`dissimilar materials having different thermal expansion coef-
`ficients, low temperature bonding is utilized. Low tempera-
`ture bonding is also crucial for materials having a low decom-
`position temperature or for materials that are temperature
`sensitive even though such materials can be thermally
`matched.
`
`Moreover, wafers or dies of dissimilar materials that are
`bonded to the host substrate are preferably thinned to a thick-
`ness that is less than a critical value for the respective mate-
`rials combination to avoid generation ofmisfit dislocations in
`the layer and to prevent sliding or cracking ofthe bonded pair
`during subsequent thermal processing steps. Transfer of dis-
`similar layers of different types onto a host wafer can be
`accomplished for example by the following steps: (1) bond a
`full thickness wafer or dies to a carrier substrate, (2) thin the
`bonded wafer or dies by grinding, CMP (chemo-mechanical
`polishing), etching or splitting, (3) subsequently bond the
`thinned wafer or dies which are bonded to the carrier substrate
`
`to a host wafer, and then (4) remove the carrier substrate.
`Design of processes needed to produce different functions
`on the same chip of integrated materials can be difficult and
`hard to optimize. Also, resultant SOC chips may get too large,
`leading to a low yield. Therefore, one alternative approach is
`to interconnect different IC layers that are fully processed and
`tested to form stacking ICs or three-dimensional system-on-a
`chip (3 -D SOC) by wafer bonding and layer transfer. Ramm
`et al in US. Pat. No. 5,563,684, the entire contents of which
`are incorporated by reference, describe such integration.
`Since wafer direct bonding and layer transfer is Very Large
`Scale Integration (VLSI) compatible, flexible and manufac-
`turable technology, using direct bonding to form 3-D SOC is
`highly favorable to other bonding methods such as adhesive
`bonding or anodic bonding. The 3-D SOC approach is also
`complementary to the materials integration method because
`the processed functional layers can be considered as unique
`
`10
`
`15
`
`20
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
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`60
`
`65
`
`2
`
`dissimilar materials layers. In many cases it is desirable that
`the thin device dies that are transferred onto a host wafer are
`
`top-up. This can be realized by the layer transfer procedures
`mentioned above.
`
`Transfer of a device layer from its host substrate to a
`desired substrate can significantly improve device perfor-
`mance. Workers in the field have shown that, by device layer
`transfer from its host silicon wafer to a glass substrate, an ultra
`low power RF bipolar IC was realized. Furthermore, the
`transfer of a power device layer from a host silicon wafer to a
`highly thermally conductive substrate is expected signifi-
`cantly increase device power capability. In general, device
`layer transfer provides opportunities for device performance
`enhancement.
`
`Traditionally, mechanical grinding, polishing or selective
`etching are employed to remove the handle substrate in the
`final step of the layer transfer procedures mentioned above.
`However, these methods are time consuming, environmen-
`tally unfriendly and result in a low thickness uniformity ofthe
`remaining layer. A detachable bonding technology that can
`separate the carrier wafer itself at step (4) is desired. A few
`methods of detachable bonding methods have been sug-
`gested; such as for example water-enhanced de-bonding, gas
`or water jet de-bonding, using a water-soluble or solvent-
`soluble adhesive bonding layer, wax bonding, plasma
`removal of a polyimide bonding layer, and laser ablation of
`polymeric adhesive bonding layer or a hydrogenated amor-
`phous silicon (a-SizH) bonding layer. These methods have
`drawbacks.
`
`In water-enhanced de-bonding, the bonding energy of the
`bonded wafers has to be very low (~100 mJ/mz) and there-
`fore, is not sufficient for the layer transfer process steps. The
`low bonding energy makes water-enhanced de-bonding use-
`ful only for wafer surface protection by wafer bonding. In gas
`or water-j et debonding, in order to avoid damaging the sepa-
`rated wafer surfaces, the bonding energy of the bonded pairs
`is limited to below 750 mJ/m2 and practically can only work
`at a wafer level. Meanwhile, water or solvent debonding is
`based on water- or solvent-soluble adhesive bonding tech-
`nologies that are suspect if a strong, reliable and uniform
`bonds are needed. Water or solvent-de-bonding also relies on
`the lateral reaction between the water or solvent and the
`
`adhesive bonding layer at the bonding interface is time con-
`suming and limits the size of the bonded pairs.
`For wax bonding, Apiezon® wax is employed as either the
`substrate itself or a bonding layer. For the latter, wax bonding
`has similar problems as in water-soluble bonding. For the
`former, Apiezon wax is not strong enough for processes in a
`layer transfer procedure. Plasma removal of a polyimide
`bonding layer is similar to the water soluble process except
`the plasma removal is a dry process. In laser ablation, the
`carrier wafer must be transparent to the incident laser such as
`a glass wafer. This method requires ablation of the polymer
`layer or the a-Si:H layer at the film/substrate interface, and is
`based on the explosive release and accumulation of gas from
`the film/substrate interface. Exciter laser pulses with energy
`>400 mJ/cm2 are required.
`Hence, prior art techniques for bonding and release present
`numerous drawbacks and disadvantages.
`
`SUMMARY OF THE INVENTION
`
`The present invention is directed to a bonding method
`having steps of forming a structure consisting of a first ele-
`ment, an amorphous silicon layer disposed on the first ele-
`ment, and a second element disposed on the layer, bonding
`the second element to a third element to form a bonded
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`US 7,462,552 B2
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`3
`structure, and heating the bonded structure at a temperature to
`detach the first element from the bonded structure.
`
`The first element may detach from the bonded structure at
`an interface between the amorphous layer and the first or
`second element.
`
`5
`
`4
`
`first surface, detached from one ofa silicon oxide layer and an
`amorphous silicon layer each containing about 5-20 at %
`hydrogen.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`10
`
`30
`
`35
`
`The amorphous layer may be comprised of silicon, silicon
`oxide, or silicon nitride.
`The second element may be processed after bonding. For
`example, the second element may be thinned.
`The method may also include a step of removing a sub-
`stantial portion of the second element after bonding the sec-
`ond element to the amorphous layer. The removing step may
`include at least one of grinding and polishing. The second
`element may be a device substrate with a device layer, and a
`substantial portion of the device substrate may be removed to 15
`leave the device layer.
`The amorphous layer may have impurities added, such as
`H, deuterium, He, Ne, Kr and Xe. The bonded structure may
`be heated at a temperature where the impurities in the amor-
`phous layer are released. The amorphous layer may be 20
`formed below a temperature at which the impurities in the
`amorphous layer are released.
`The amorphous layer may be a hydrogenated amorphous
`silicon layer. The hydrogenated amorphous silicon layer may
`have about 5-20 at. percent hydrogen concentration. The
`hydrogenated amorphous silicon layer is preferably formed
`below a temperature at which hydrogen releases from the
`amorphous silicon layer.
`The amorphous layer may be a hydrogenated amorphous
`silicon oxide layer. The hydrogenated amorphous silicon
`oxide layer may have about 5-20 at. percent hydrogen con-
`centration. The hydrogenated amorphous silicon layer is pref-
`erably formed below a temperature at which hydrogen
`releases from the amorphous silicon layer.
`The method may also include a step of using released
`hydrogen to detach the first element from the bonded struc-
`ture. Hydrogen can be accumulated at an interface between
`the first or second element and the hydrogenated amorphous
`layer, form hydrogen bubbles, and detach the first element
`from the bonded structure.
`
`40
`
`Nucleation sites may be formed on the second element, or
`on the first element prior to forming the amorphous layer.
`Forming the nucleation sites may be accomplished by one of
`roughening the surface ofthe first or second element, forming
`a hydrocarbon layer on the surface, or exposing the surface to
`a plasma. The surface may be exposed one of an N and Ar
`plasma in reactive ion etch mode. The splitting plane will be
`the surface on which the nucleation sites are formed.
`
`45
`
`All the elements can be bare substrates or substrates cov- 50
`ered with a bonding layer such as an oxide layer.
`Boron may be added to an amorphous silicon layer to a
`concentration of about l><1016 cm‘3 to l><1021 cm‘3. Also,
`one of In, Ga and Al may be added to a hydrogenated amor-
`phous silicon layer.
`The present invention is also directed to a bonding method
`including the steps of forming a structure consisting of a first
`element, a silicon oxide layer having about 5-20 at % hydro-
`gen disposed on the first element, and a second element
`disposed on the layer, bonding the second element to a third 60
`element to form a bonded structure, and heating the bonded
`structure at a temperature to detach the first element from the
`bonded structure.
`
`55
`
`The present invention is further directed to a bonded struc-
`ture having a first element and a substrate portion having a 65
`first surface bonded to the first element, directly or through an
`intervening bonding layer, and a second surface, opposing the
`
`A more complete appreciation of the present invention and
`many attendant advantages thereofwill be readily obtained as
`the same becomes better understood by reference to the fol-
`lowing detailed description when considered in connection
`with the accompanying drawings, wherein:
`FIGS. 1A and 1B are schematic illustrations of first and
`
`second substrates having an amorphous silicon layer;
`FIGS. 2A, 2B and 2C illustrate bonding the first and second
`substrates with no bonding layer (2A) and with a bonding
`layer (2B, 2C), respectively;
`FIGS. 3A, 3B and 3C illustrate thinning of the backside of
`the second substrate;
`FIGS. 4A, 4B and 4C illustrate bonding of the thinned
`second substrate to a host wafer with no bonding layer and
`with a bonding layer, respectively;
`FIGS. 5A-5F illustrate separating the first substrate from
`the bonded structure, without and with a bonding layer,
`respectively;
`FIGS. 6A and 6B illustrates the structure after separation;
`and
`
`FIGS. 7A and 7B illustrate bonding a plurality of bonded
`structures to a substrate
`
`FIGS. 8A and 8B illustrate the plurality of bonded struc-
`tures after separation; and
`FIG. 9 is graph depicting the bonding energy of a bonded
`pair of an amorphous silicon layer covered silicon wafer and
`PECVD oxide covered silicon wafer as a function of anneal-
`
`ing temperature.
`
`DETAILED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Referring now to the drawings, wherein like reference
`numerals designate identical or corresponding parts through-
`out the several views, the embodiments of the invention will
`be described. The present invention, in a preferred embodi-
`ment, minimally involves three types of substrates, wafers or
`dies: a carrier or handle substrate, wafer or die; a second
`substrate, wafer or die to be bonded to the carrier or handle
`substrate, wafer or die and from which a thin layer is to be
`transferred; and a third host substrate, wafer or die to which
`the thin layer is transferred.
`FIGS. 1A and 1B illustrate a first embodiment ofthe inven-
`
`tion. Here, an amorphous silicon layer 2 is formed on a
`element 1, which may be made of any solid material, such as
`silicon, quartz, glass, ceramic, et al., that can provide support
`for layer 2 (or donor workpiece 3 and layer 2) and handling
`capability for subsequent processing steps described below,
`and preferably a carrier or ho st wafer or substrate, or on donor
`workpiece 3, which is any material from which a thin layer is
`to be transferred, as described below, and is preferably a
`substrate. The amorphous silicon layer 2 is of a thickness
`suitable for any needed polishing and/or etching to planarize
`and smooth the surface (as described below) typically in the
`range of 0.5 to 10 microns. Substrate 3 may also be a device
`wafer with a device layer to be transferred. For ease of expla-
`nation, element 1 and donor workpiece 3 are referred to
`hereafter as substrates 1 and 3. The amorphous silicon layer is
`preferably a hydrogenated amorphous silicon layer (a-SizH).
`The a-Si:H layer is preferably deposited on substrate 1 or 3 by
`a chemical vapor deposition (CVD) process, but may also be
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`5
`formed by sputtering deposition. For a-Si:H deposition, as
`discussed below, the wafer temperature during deposition
`should be kept below the critical temperature at which hydro-
`gen releases from the a-Si:H layer. Selection of this tempera-
`ture (below the critical temperature) may take into consider-
`ation other
`factors
`such as
`the advantages of lower
`temperature deposition, the desired composition or structure
`of the layer, and the quality of the structure of the layers.
`Substrate 3 from which a thin layer is to be transferred is
`directly bonded to substrate 1 Via layer 2, at temperatures
`below the critical temperature at which hydrogen releases
`from the a-Si:H layer to obtain a bond strength sufficient to
`allow for subsequent processing such as, for example, CMP
`(Chemical Mechanical Polish), grinding, etching, dicing and
`splitting. Substrate 3 may be any material from which a thin
`layer is desired to be transferred to another wafer. Also, sub-
`strate 3 may be a device wafer having a device layer to be
`transferred. The surface of either substrate 1 or 3 that does not
`
`have layer 2 may be covered with a layer to promote bonding,
`preferably an oxide and more preferably a deposited silicon
`oxide, such as a PECVD (Plasma Enhanced CVD) silicon
`oxide, and also is preferably planarized and/or smoothed, in
`the manner as described above. This is illustrated in FIG. 2B,
`where layer 4 is disposed on substrate 3 and layer 4 is pla-
`narized and/or smoothed, as needed, and bonded to layer 2.
`Alternatively, layer 2 may be formed on substrate 3 and
`layer 4 may be formed on substrate 1 (see FIG. 2C). If either
`substrate 1 or substrate 3 are not sufficiently planar, layers 2
`and 4 are preferably sufficiently thick to allow a sufficient
`planarization with CMP.
`After bonding, as shown in FIG. 3A, substrate 3 is thinned
`to a desired thickness by, for example, CMP, polishing, grind-
`ing, etching, splitting (such as B+H co-implantation induced
`splitting) and/or peeling, or a combination of these tech-
`niques, to leave portion 3A. The resulting surface of portion
`3A is planarized and/or smoothed, as needed. The thickness
`of the remaining portion will vary based on the layer desired
`to be transferred. Also, a layer (see layer 6 in FIGS. 3B and
`3C) may be deposited on the resulting surface of portion 3A,
`either before or after portion 3A is planarized and/or
`smoothed, and the layer may be planarized and/or smoothed,
`as needed. Layer 6 may be formed of the same materials as
`layer 4 and promotes subsequent bonding of portion 3A. It is
`noted that layer 6 may also be used in a structure without layer
`4, such as the structure ofFIG. 3A. Layers such as 4 and 6 may
`be included as need in the structure.
`
`The surface of portion 3A, or the layer 6 formed on the
`surface of portion 3A, is directly bonded to element 5, which
`may be made of any solid material, such as silicon, quartz,
`glass, ceramic, et al., that can provide support for portion 3A,
`layer 2 and substrate 1 and handling capability for subsequent
`processing steps described below, and is preferably a host or
`carrier substrate or wafer (hereinafter referred to as substrate
`5 for ease of explanation), at temperatures below the critical
`temperature at which hydrogen releases from the a-Si:H
`layer, as shown in FIGS. 4A-4C. The surface of substrate 5
`bonded to portion 3A may also be covered with a bonding
`layer, preferably an oxide and more preferably a deposited
`silicon oxide, such as a PECVD (Plasma Enhanced CVD)
`silicon oxide, and may be planarized and/or smoothed, as
`needed, prior to bonding. Subsequently, the bonded structure
`is subjected to thermal treatment at a temperature above that
`at which the impurity, H in the case of a-Si:H, releases. The
`impurity accumulates to create pressure sufficient to split the
`substrates, preferably at the interface of layer 2 and portion
`3A, as shown in FIGS. 5A-5C. Splitting at this interface
`minimizes the need to remove any residual portion of layer 2
`
`10
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`15
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`20
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`6
`remaining on portion 3A. It is also possible to split the sub-
`strates at the interface between substrate 1 and layer 2, if
`desired (see FIGS. 5D-5F). FIGS. 6A and 6B illustrate the
`substrates after splitting and removal (if needed) of layer 2.
`Layer 2 may be removed by chemical or mechanical tech-
`niques, such as touch polishing, dry etching or wet etching, or
`a combination of such techniques.
`A combination of thermal treatment and mechanical peel-
`ing of the bonded structure containing substrates 1 and 3 and
`the substrate 5 can also be used to separate the portion 3A
`from the substrate 1. For example, after a thermal treatment
`that is not sufficient to split the substrate 1 from the bonding
`interface, a thin wedge could be used to insert into the bond-
`ing interface to separate them. A gas or water jet that is
`aligned to the bonding interface can also be used for this
`purpose.
`These separation techniques apply also in the case of die-
`to-wafer bonding. In this case the thinned bonded wafer of
`substrate 1 and 3A is diced up into dies after planarizing and
`smoothening the surface ofthinned substrate 3A. The dies are
`then aligned as needed and bonded to the ho st wafer, substrate
`5. After thermal treatment, the handle substrate of all the dies
`is split off and device layers from all bonded dies have been
`transferred onto the ho st wafer. This is illustrated in FIGS. 7A
`
`and 7B showing bonded pairs of substrate 1 and portion 3A,
`after dicing, bonded to substrate 5 without and with a bonding
`layer 6, respectively. Only two bonded pairs are shown, but
`the invention is applicable to any number of pairs. FIGS. 8A
`and 8B show the transferred portions 3A after splitting off of
`substrates 1. Any remaining portion of layer 2 on surface of
`layer 3A may be removed by chemical or mechanical tech-
`niques, such as touch polishing, dry etching or wet etching, or
`a combination of such techniques.Also, the bonded pairs may
`be of different materials, may contain different devices, or
`both. The invention allows for combining any type of devices
`and/or layers ofmaterials on a substrate. Layers such as layers
`4 and 6 may be incorporated, as needed, into the die to wafer
`structure.
`
`The thermal treatment may enhance the bond strength of
`the bond between portions 3A and substrate 5 but at the same
`time it introduces sufficient amount of hydrogen at the inter-
`face between substrates 1 and layer 2 to build up a sufficient
`internal pressure to split the wafer or dies from the handle
`wafer or substrate 1.
`
`After detaching, the surface of substrate 3A may contain
`a-Si:H residues. These residues may be removed with a brief,
`low pressure polish that may also further result in a smooth
`surface of substrate 3. A brief dry etch using, for example, an
`SF6-based etch, can also be used to remove a-Si:H residues.
`As discussed above, a-Si:H is preferably used for the amor-
`phous silicon layer. To enhance the adhesion between depos-
`ited a-Si:H layer and the surface ofthe portion 3A or substrate
`1, many approaches known in the art can be employed. For
`example, sputtering of the carrier substrate surface prior to
`a-Si:H layer deposition may be used to significantly increase
`the adhesion. In general, the removal of native oxide from
`surfaces, such as silicon, by chemical etching or anAr or other
`gas plasma sputtering before a-SizH layer deposition will
`enhance adhesion. The surface treatment can also introduce
`
`nucleation sites (discussed in more detail below) on the sur-
`face and enhance hydrogen trapping. Also, a thin film may be
`deposited on substrate 1 as an adhesion promoter, such as a
`silicon nitride or Ti layer.
`Hydrogen in a-Si:H layer exists mostly as SiiHn where
`n:l, 2 and 3. The wafer or die temperature during a-Si:H
`layer deposition must be kept below the critical temperature
`at which hydrogen releases from SiiHn in a-Si:H layer. The
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`US 7,462,552 B2
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`7
`release of hydrogen has been demonstrated to start at about
`367° C. from SiiH2 and at about 447° C. from SiiH