‘549 Prosecution history summary
`Summary
`Date
`2002-10-04 Application Filed. Claims 1-11, “controller chip” for coupling a
`computer system with a flash storage system, the controller chip
`comprising “an interface mechanism for determining whether the
`flash storage system had a controller;” the controller chip having
`an adapter allowing the computer system to communicate with
`the flash storage system. Claims 12-16, were directed to a “flash
`storage system” comprising a medium ID section where a medium
`ID contains specifications of the medium ID. Claim 5 requires the
`computer system to manage error correction; Claim 6, it is
`firmware in the computer system; Claim 7, it is driver software;
`and in claim 8, it is the combination of firmware and driver
`software that manages error correction.
`2004-01-29 Restriction Requirement. I: Claims 1-11; II: Claims 12-16.
`2004-03-24 Elected Group I
`2004-05-04 Office Action. Claims 1-11 are rejected as anticipated by
`Kobayashi, US 6199122 (Fig. 12, below). The examiner states
`that Kobayashi provides a “controller 12” between a computer
`system 11 and a flash card system 13. The controller 12 includes
`a controller chip 122. The controller 12 [not the claimed chip]
`includes means, e.g., sensor 133, for detecting whether the flash
`storage system has a controller. The flash storage has a medium
`ID. Action at 4. All error management claims were rejected over
`Figs. 9-12 and in particular col. 11:37-45.
`
`HP 1015
` Pages
` 1-210
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`294-297
`298-301
`316-325
`
`
`Kobayashi discloses that the computer system 11 managed error
`correction. The computer system was construed to include
`controller 12.
`
`
`2004-08-10 Amendment. Claims 1-16 canceled. Claim 17-32 added.
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`357-364
`1
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` 374-382
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`394-395,
`400
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`386-393
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`403-406
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`408-410
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`411-421
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`2005-02-10
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`2004-10-28
`
`Independent Claims 17 (flash adapter), 23 (method) and 27
`(system) are directed to a flash adapter that has “firmware” “to
`manage error correction of the flash section, comprising bad block
`mapping.” Cancelled: limitations regarding “an interface
`mechanism to determine whether the flash storage system had a
`controller.”
`Kobayashi, it is argued, does not disclose bad block mapping.
`The examiner objected that the new claims were not directed to
`the elected “controller chip” group.
`2004-11-17 Examiner Interview: “Briefly discussed a proposed new Claim 33
`[that would] incorporate previous Claim 1 with further limitations
`to the adapter to overcome the outstanding requirements. Such
`would be an acceptable solution” [to comply with the restriction
`requirement and the election of group I, claims 1-11.]
`2004-11-22 Amendment. Claims 1-32 are canceled. New claims, 33-48,
`directed to a “controller chip” are added. The claims restore to
`just claim 33, “a controller chip comprising: … an interface
`mechanism to determine whether the flash storage system includes
`a controller.” In other respects however, the claims correspond to
`Claim 17-32. In particular, claims 39 (claim 7) and 43 (11) have
`no such limitation. They only require using “firmware” in a
`“flash adapter” of the controller chip “to manage error correction of
`the flash section [of the flash storage system], … compris[ing] block
`mapping….”
`The examiner objected that the 2004-11-22 amendment is
`nonresponsive because it has no arguments concerning the prior
`art.
`2005-03-14 Amendment. The arguments presented in the 2004-08-10
`amendment are re-stated, in particular that the Kobayashi
`reader/writer 12 (previously controller 12) does not disclose
`“firmware to perform operations comprising comprise [sic] bad block
`mapping of the flash section to manage error correction of the flash
`section, as claimed.” [Sic]
`2005-06-03 Final office action. The examiner rejects the independent claims
`over Kobayashi in view of Hashbun et al. (US 5,740,349). The
`examiner repeated his description of Kobayashi from the first
`action (2004-05-04), including that Kobayashi had an interface
`mechanism, 133, for determining whether the flash storages
`system had a controller. [This was pertinent only to claim 1.]
`Regarding error correction, the reader reported the fact of errors
`to the computer system. The computer system used a
`combination of firmware and software to correct errors. The
`computer system was construed to include the reader because “no
`claim language prohibits combining the computer (11) and the
`reader/writer (12)….”
`The examiner however concluded that because Kobayashi did not
`disclose a type of error correction, “’bad block mapping’ is not set
`forth”
`The examiner cited Hashbun (Fig. 6, below) for showing a
`controller that conducted bad block mapping using firmware.
`Hasbun disclosed a controller 24, Figs. 2 and 6, that interfaced a
`host and flash memory 20. The controller 24 employed a
`microprocessor 25 to conduct bad block mapping. See, “bad
`
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`2
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`block table” 31. The microprocessor used using firmware 26.
`The examiner argued that it would be obvious to modify
`Kobayashi’s controller chip 122 and its firmware 123 (first line of
`page 7) in reader/writer 12 to incorporate Hasbun’s functionality
`because it is the controller chip 122 that determined the presence
`of error conditions.
`
`
`2005-11-07 Applicant amended the claims to limit the location of the firmware
`that conducted error correction, including bad block mapping to
`being “in the flash adapter.”
`The applicant then argued Kobayashi could not be modified to
`include the Hasbun functionality because Kobayashi transmitted
`error status to the computer. This “prevent[ed] the reader/writer
`… from being modified to include firmware in the flash adapter to
`perform operations comprising bad block mapping of the flash
`section to manage error correction of the flash section, as
`amended.” [Sic.]
`Hasbun was distinguished because, “Unlike the claimed
`invention, Hashbun discloses a controller residing not on the
`flash adapter, but in the flash memory. In fact there is no
`mention all of a flash adapter in Hashbun.”
`2006-01-27 Non-final rejection. The examiner construed the arguments to
`assert that Hasbun controller resided “on the flash memory” and
`not on a “flash adapter.” However, the examiner said that
`Hasbun’s controller 24 was a separate ASIC chip, per Fig. 6,
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`487-494
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`499-509
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`3
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`2006-05-30
`
`
` was a that
`could not be mounted on “on the flash memory [20]” because
`ASICs were too large. He then concluded that in modifying
`Kobayashi, the Hasbun ASIC would reside on its “element 12” [its
`reader/writer] and not on the flash memory. Further, he said,
`incorporating bad block mapping functionality into Kobayashi’s
`controller was clearly technically possible.
`
`The examiner then repeated his rejection over Kobayashi in view
`of Hashbun.
`Examiner interview: “Applicant inquired how to better distinguish
`the instant application over the prior art. Examiner explained
`[his] position based on [the] Office Action submitted on
`01/27/2006, suggested adding language to claims to detail the
`adapter been able to accept multiple cards via multiple ports and
`particularly more into how the error correction/mapping is
`achieved.”
`2006-06-02 Amendment. The applicant added to claim 39 (patent claim 7),
`with a corresponding change to 43 (patent claim 11) that the
`“flash storage system” be “with or without a controller;”
`“determining whether the flash storage system includes a controller
`for error correction;” and “in the event where the flash storage
`system does not have a controller for error correction” using
`firmware … to manage bad block mapping, etc. The limitation to
`“determining … controller” was present in claim 1 as filed, but not
`included in claim 39 (7) or 43 (11) until this amendment.
`
`The applicant argued, at 7, that neither Hashbun nor Kobayashi
`taught “an interface mechanism capable of receiving flash storage
`systems with controller’s and flash storage systems without
`controllers.” [Comment: This was certainly true of Hasbun.
`Regarding, Kobayashi, it disclosed two controller chips, 122 and
`124 in its reader 12. HP 1005, 6:5-43. Controller chip 122
`disclosed the use of firmware 123, id. at 23-24. It was this chip
`that the examiner had repeatedly cited as the claimed controller
`chip, in part, because this chip used firmware 123 while A/T
`controller 124 did not. The examiner said it would be obvious to
`modify controller chip 122 per Hasbun to manage bad block
`
`
`
`532-534
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`518-525
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`4
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`

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`mapping. The applicant argued that it would not be obvious to
`modify Kobayashi to include the Hasbun functionality. HP 1005
`12:58-13:8]
`2006-09-05 Notice of allowance. The examiner, Alan S. Chen, allowed the
`claims because they particularly required “a controller chip and
`method to determine whether a flash storage system includes a
`controller for error correction via a detector, and if it is determined
`that there is no controller for error correction, then using
`firmware in a flash adapter to manage error correction of a flash
`section including bad block mapping of the flash section.”
`
`Reissue
`2011-2013 Over six actions, the examiner, Alan S. Chen, the same examiner
`who allowed the patent, repeatedly re-allowed the originally
`patented independent claims, 1, 7 and 11 over six office actions:
`2011-01-06, 2011-07-13, 2011-12-23, 2012-08-30, 2012-11-15,
`and 2013-01-04. The applicants voluntarily cancelled claims 1-6.
`A notice of appeal was filed on 2013-05-01.
`
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`538-551
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`5