IPR 2013-00217
`
`Hewlett-Packard Company
`Petitioner
`
`Lead Counsel: Robert L. Hails, Jr.
`Backup Counsel: T. Cy Walker
`
`
`
`Hewlett-Packard Company
`Petitioner
`
`Lead Counsel: Robert L. Hails, Jr.
`Backup Counsel: T. Cy Walker
`
`
`
`Introduction
`
` MCM Arguments in Patent Owner’s Response:
` Seventh Amendment: “The Board lacks subject matter jurisdiction.”
`MCM Resp., pp. 1‐13
`
` “Claims 7 and 11 both require a controller chip.”
`MCM Resp., pp. 14‐24
` MCM’s Response Makes No Other Arguments for Patentability.
` “does not challenge HP’s showing that prior art shows all functionality of
`challenged claims.”
` “offers no arguments or evidence to explain why a single chip system
`would not be predictable over the prior art.”
` “no evidence of secondary considerations.”
`
`HP Reply, pp. 1‐2
`
`Arguments for patentability not raised in the Patent Owner’s Response are
`deemed waived.
`Sched. Order, p. 2
`
`2
`
`
`
`Claim 7
`
`7. A method comprising:
`using a controller chip to interface a flash storage system with or
`without a controller to a computing device, the controller chip
`comprising a flash adapter, wherein the flash storage system
`comprises a flash section and at least a medium ID;
`determining whether the flash storage system includes a
`controller for error correction; and
`in an event where the flash storage system does not have a
`controller for error correction, using firmware in the flash adapter to
`perform operations to manage error correction of the flash section,
`including bad block mapping of the flash section in the flash storage
`system that is coupled to the flash adapter section.
`
`3
`
`
`
`Claim 11
`
`11. A system comprising:
`a computing device;
`a flash storage system comprising a flash section and at least a portion
`of a medium ID; and
`a controller chip coupled between the computing device and the flash
`storage system to interface the flash storage system to the computing
`device, the controller chip comprising an interface mechanism capable of
`receiving flash storage systems with controller and controllerless flash
`storage systems, a detector to determine whether the flash storage system
`includes a controller for error correction and a flash adapter which
`comprises firmware to perform, in an event where the flash storage
`system does not have a controller for error correction, operations to
`manage error correction of the flash section, including bad block mapping
`of the flash section in the flash storage system that is coupled to the flash
`adapter section.
`
`4
`
`
`
`MCM: “Chip”
`
` KSR: A “predictable use of prior art elements according to their
`established functions [is] an obvious improvement.”
`Dec. Inst., p. 16
` Claim Language:
`Claim 7:
`using a controller chip to interface a flash storage system with or
`without a controller to a computing device
`Claim 11:
`a controller chip coupled between the computing device and the
`flash storage system to interface the flash storage system to the computing
`device
` MCM:
` Does “not challenge HP’s showing that prior art shows all functionality of
`challenged claims.”
`HP Reply, pp. 1‐2
` “HP effectively reads ‘chip’ out of the claims by reading the claims on the
`Kobayashi reader 12 as a whole, an apparatus that has multiple chips that
`perform distinct functions.”
`MCM Resp., p. 14
`
`5
`
`
`
`The Prior Art Teaches Use of a Single Chip
`
` Kobayashi:
`“Kobayashi describes a system with
`a reader/writer 12, which includes a
`conversion controller 122, an ATA
`controller 124, and ROM 123 to
`interface flash memory cards 13 to a
`computer 11.”
`HP Pet., p. 43
`“The conversion controller 122 is
`configured of a one‐chip
`microprocessor or the like and
`operates in accordance with the
`program stored in the ROM 123.”
`HP 1005, Col. 6:12‐14
`HP Reply, p. 4
`“Does not describe any hardware
`implementation for the second
`controller 124.”
`HP Reply, p. 4
`
`Kobayashi, FIG. 11 (HP 1005)
`
`6
`
`
`
`The Prior Art Teaches Use of a Single Chip
`
` Kikuchi: Controller 10
` “a one‐chip controller”
`HP Reply, p. 3
` “constituted by a CPU, a ROM, a RAM, an input/output interface circuit and
`the like”
`HP Pet., p. 49
` “includes several other controllers and processors, including an error
`controller 32, a flash table controller 28, a command processor 26 and a
`reset processor 22”
`HP Reply, p. 3
`
`Kikuchi, FIG. 15A (HP 1007)
`
`Kikuchi, FIG. 2 (HP 1007)
`
`7
`
`
`
`The Prior Art Teaches Use of a Single Chip
`
`ONE CHIP CONTROLLER
`
`Kikuchi, Fig. 2 (HP 1007)
`
`ONE CHIP
`CONTROLLER
`
`Kobayashi, Fig. 11
`(HP 1005)
`
`8
`
`
`
`Possible Rebuttal Slides
`
`
`
`Claim 7
`
`
`
`A method comprising:A method comprising:
`
`10
`
`
`
`Claim 7
`
`
`using a controller chip to interface a flash storage system with or without a using a controller chip to interface a flash storage system with or without a
`
`controller to a computing device, controller to a computing device,
`
`11
`
`
`
`Claim 7
`
`
`
`the controller chip comprising a flash adapter, the controller chip comprising a flash adapter,
`
`12
`
`
`
`Claim 7
`
`
`wherein the flash storage system comprises a flash section and at least a medium wherein the flash storage system comprises a flash section and at least a medium
`
`ID;ID;
`
`13
`
`
`
`Claim 7
`
`
`determining whether the flash storage system includes a determining whether the flash storage system includes a
`
`controller for error correction; andcontroller for error correction; and
`
`14
`
`
`
`Claim 7
`
`
`in an event where the flash storage system does not have a controller for error in an event where the flash storage system does not have a controller for error
`
`correction, using firmware in the flash adapter to perform operations to manage correction, using firmware in the flash adapter to perform operations to manage
`
`error correction of the flash section, including bad block mapping of the flash error correction of the flash section, including bad block mapping of the flash
`
`section in the flash storage system that is coupled to the flash adapter section.section in the flash storage system that is coupled to the flash adapter section.
`
`15
`
`
`
`Claim 7
`
`
`in an event where the flash storage system does not have a controller for error in an event where the flash storage system does not have a controller for error
`
`correction, using firmware in the flash adapter to perform operations to manage correction, using firmware in the flash adapter to perform operations to manage
`
`error correction of the flash section, including bad block mapping of the flash error correction of the flash section, including bad block mapping of the flash
`
`section in the flash storage system that is coupled to the flash adapter section.section in the flash storage system that is coupled to the flash adapter section.
`
`16
`
`
`
`Claim 11
`
`
`11. A system comprising: 11. A system comprising:
`
`a computing device; a computing device;
`
`17
`
`
`
`Claim 11
`
`
`a flash storage system comprising a flash section and at least a portion of a a flash storage system comprising a flash section and at least a portion of a
`
`medium ID; and medium ID; and
`
`18
`
`
`
`Claim 11
`
`
`a controller chip coupled between the computing device and a controller chip coupled between the computing device and
`
`the flash storage system to interface the flash storage system the flash storage system to interface the flash storage system
`
`to the computing device, to the computing device,
`
`19
`
`
`
`Claim 11
`
`
`the controller chip comprising an interface mechanism capable of receiving flash the controller chip comprising an interface mechanism capable of receiving flash
`
`storage systems with controller and controllerless flash storage systems, storage systems with controller and controllerless flash storage systems,
`
`20
`
`
`
`Claim 11
`
`
`a detector to determine whether the flash storage system includes a controller for a detector to determine whether the flash storage system includes a controller for
`
`error correction anderror correction and
`
`21
`
`
`
`Claim 11
`
`
`a flash adapter which comprises firmware to perform, in an event where the flash a flash adapter which comprises firmware to perform, in an event where the flash
`
`storage system does not have a controller for error correction, operations to manage storage system does not have a controller for error correction, operations to manage
`
`error correction of the flash section, including bad block mapping of the flash section error correction of the flash section, including bad block mapping of the flash section
`
`in the flash storage system that is coupled to the flash adapter section. in the flash storage system that is coupled to the flash adapter section.
`
`22
`
`
`
`Claim 11
`
`
`a flash adapter which comprises firmware to perform, in an event where the flash a flash adapter which comprises firmware to perform, in an event where the flash
`
`storage system does not have a controller for error correction, operations to manage storage system does not have a controller for error correction, operations to manage
`
`error correction of the flash section, including bad block mapping of the flash section error correction of the flash section, including bad block mapping of the flash section
`
`in the flash storage system that is coupled to the flash adapter section. in the flash storage system that is coupled to the flash adapter section.
`
`23
`
`
`
`Kobayashi
`
`
`
`The Third Embodiment (FIG. 11)The Third Embodiment (FIG. 11)
`
`
`
`The Fourth Embodiment (FIG. 12)The Fourth Embodiment (FIG. 12)
`
`Petition (Paper 2) at 45.
`
`24
`
`
`
`Kobayashi
`
`
`
`Flash Memory Card Without ControllerFlash Memory Card Without Controller
`
`
`
`Flash Memory Card With ControllerFlash Memory Card With Controller
`
`Petition (Paper 2) at 56.
`
`25
`
`
`
`Kikuchi
`
`“The error controller 32 generates an ECC (Error Correcting
`Code) in a write operation, and performs ECC error control in a
`read operation. The error controller 32 also performs a block
`substituting process or the like in the event of a failure or
`error.” HP 1007, 11:17-21.
`
`Petition (Paper 2) at 49.
`
`26
`
`26
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