(12) United States Patent
`Us 6,586,838 132
`(10) Patent N0.:
`(45) Date of Patent:
`Fujiki et al.
`Jul. 1, 2003
`
`US006586838B2
`
`6,149,986 A * 11/2000 Shibata et al.
`.............. 427/571
`6,184,143 B1 *
`2/2001 Ohashi et al.
`........... 438/697
`
`6,211,570 B1 *
`4/2001 Kakamu .............. 257/760
`6,313,003 B1 * 11/2001 Chen .......................... 438/396
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`03120744 A *
`07—029905
`10—098102
`10—270554
`10—335461
`11—317454
`2000—174119
`
`5/1991
`1/1995
`4/1998
`10/1998
`12/1998
`11/1999
`6/2000
`
`* cited by examiner
`
`Primary Examiner—Eddie Lee
`Assistant Examiner—Chris C. Chu
`
`(74) Attorney, Agent, or Firm—McDermott, Will & Emery
`
`(57)
`
`ABSTRACT
`
`To provide excellent reliability and high yield of a semi-
`conductor device that has a multi-Wiring structure by using
`a fluorine-containing silicon oxide film as an interlayer
`insulating film. A fluorine-containing silicon oxide film is
`formed so as to cover a lower layer metal Wiring. A TEOS
`film is formed on the fluorine-containing silicon oxide film.
`After planarizing the TEOS film with the CMP method, an
`SiH4-based silicon oxide film that is suitable for capturing
`fluorine is formed on the TEOS film. Metal Wirings are
`formed on the SiH4-based silicon oxide film. A predeter-
`mined heat treatment is performed to capture fluorine inside
`the SiH4-based silicon oxide film. The SiH4-based silicon
`oxide film is patterned to the same pattern as the metal
`Wirings. After diffusing fluorine into the atmosphere from
`the exposed area of the TEOS film, a silicon nitride film is
`formed on the metal Wirings.
`
`5 Claims, 5 Drawing Sheets
`
`(54) SEMICONDUCTOR DEVICE
`
`(75)
`
`Inventors: Noriaki Fujiki, Tokyo (JP); Takeru
`Matsuoka, Tokyo (JP); Hiroki
`Takewaka, Tokyo (JP)
`
`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/909,781
`
`(22)
`
`Filed:
`
`Jul. 23, 2001
`
`(65)
`
`Prior Publication Data
`
`US 2002/0117755 A1 Aug. 29, 2002
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 26, 2001
`
`(JP)
`
`....................................... 2001—051172
`
`(51)
`
`Int. Cl.7 ......................... H01L 23/48; H01L 23/52;
`H01L 29/40
`
`(52) US. Cl.
`
`....................... 257/758; 257/760; 257/768;
`257/756; 257/757
`(58) Field of Search ................................. 257/758, 761,
`257/765, 756, 757, 768
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`............ 438/231
`4,419,809 A * 12/1983 Riseman et al.
`......
`438/210
`5,202,275 A *
`4/1993 Sugiura et al.
`
`......
`438/624
`5,420,075 A
`5/1995 Homma et a1.
`5,753,564 A
`5/1998 Fukada .............
`438/624
`
`5,850,102 A
`12/1998 Matsuno
`257/635
`6,057,242 A
`5/2000 Kishimoto .................. 438/692
`
`****
`
`
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`U.S. Patent
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`Jul. 1, 2003
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`Sheet 1 0f 5
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`US 6,586,838 B2
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`Fig. 1
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`PRIOR ART
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`Fig. 2
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`PRIOR ART
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`Fig. 4
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`PRIOR ART
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`U.S. Patent
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`Jul. 1, 2003
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`Sheet 2 0f 5
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`US 6,586,838 B2
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`Fig. 5
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`PRIOR ART
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`U.S. Patent
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`Jul. 1, 2003
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`Sheet 3 0f 5
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`US 6,586,838 B2
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`Fig. 8
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`Jul. 1, 2003
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`Sheet 4 0f 5
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`US 6,586,838 B2
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`Fig. 1 1
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`Jul. 1, 2003
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`Sheet 5 0f 5
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`US 6,586,838 B2
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`Fig. 15
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`FILM THICKNESS
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`Fig. 16A
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`US 6,586,838 B2
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`1
`SEMICONDUCTOR DEVICE
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a semiconductor device,
`and more specifically, to a semiconductor device having a
`structure suitable for imparting high reliability to semicon-
`ductors with a multi-layer wiring structure.
`2. Description of the Background Art
`With recent increase in integration and functions of semi-
`conductor devices, wirings have become increasingly finer,
`the number of wiring layers has increased, and the multi-
`layer wiring technique has become essential. FIG. 1 shows
`a cross-sectional view of a semiconductor device of a
`
`two-layer wiring structure formed using a conventional
`multi-layer wiring technique.
`In FIG. 1, a first interlayer insulating film 12 is formed on
`a silicon substrate 10. On the first interlayer insulating film
`12 is provided a lower layer metal wiring 14 made of
`aluminum or the like. The lower layer metal wiring 14 is
`covered with a fluorine-containing silicon oxide film 16. On
`the fluorine-containing silicon oxide film 16 is formed a
`TEOS-based silicon oxide film 18 (hereafter referred to as
`“TEOS film 18”).
`In semiconductor devices of the generation in which
`sub-quarter-micron wirings are used, especially in the ones
`for which high-speed operation is required, the capacitance
`of the interlayer insulating film must be sufficiently small.
`Since the fluorine-containing silicon oxide film 16 is more
`suitable for decrease in capacitance than a silicon oxide film
`that does not contain fluorine, the fluorine-containing silicon
`oxide film has been used as a part of the interlayer insulating
`film in such a semiconductor device.
`
`On the TEOS film 18 is formed a metal wiring 20 made
`of aluminum or the like. The metal wiring 20 is covered with
`a silicon nitride film 22 that acts as a passivation film.
`The method for manufacturing a conventional semicon-
`ductor device shown in FIG. 1 will be described below
`
`referring to FIGS. 2 to 4.
`As shown in FIG. 2, a first interlayer insulating film 12,
`and a lower layer metal wiring 14 are first formed on a
`silicon substrate 10 using the combination of the CVD
`method, the etch-back method, the CMP method or the like.
`A fluorine-containing silicon oxide layer 16 is deposited
`on the entire surface of the semiconductor wafer so as to
`
`cover the first interlayer insulating film 12 and the lower
`layer metal wiring 14. The fluorine-containing silicon oxide
`layer 16 is formed using the high-density plasma CVD
`method that uses SiH4 gas, 02 gas, and C2F6 gas as the
`reaction gases, that is, the CVD method to generate high-
`density plasma by impressing a bias voltage to the above-
`mentioned reaction gases. In such high-density plasma CVD
`method, deposition and sputter etching proceed simulta-
`neously. Therefore, the portion having a step beneath it, that
`is, the portion above the lower layer metal wiring 14 has its
`corners etched off to have a triangular shape. The fluorine-
`containing silicon oxide layer 16 is deposited until
`the
`thickness thereof becomes substantially the same as that of
`the lower layer metal wiring 14.
`As shown in FIG. 3, a TEOS film 18 is deposited on the
`fluorine-containing silicon oxide layer 16. The TEOS film
`18 is formed by, for example, the plasma CVD method that
`uses TEOS and 02 gas as reaction gases. The underlying
`shapes are exactly reflected to the surface of a silicon oxide
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`film formed by such CVD method. Therefore, the portion of
`the TEOS film 18 above the lower layer metal wiring 14 has
`a triangular shape.
`As shown in FIG. 4, the TEOS film 18 is planarized by the
`CMP method. This CMP method is performed so that the
`TEOS film 18 is left above the lower layer metal wiring 14,
`that is, so that the fluorine-containing silicon oxide layer 16
`is not exposed on the surface of the TEOS film 18. Via holes
`(not shown) to the lower layer metal wiring 14 are formed
`in the fluorine-containing silicon oxide layer 16 and the
`TEOS film 18. In the via holes are formed tungsten plugs
`(not shown). The via holes and the tungsten plugs are formed
`using the combination of photoengraving, dry etching,
`sputtering, the CVD method, or the etch-back method.
`Thereafter, a metal wiring 20 (see FIG. 1) is patterned on
`the TEOS film 18 so as to conduct to the above-described
`tungsten plugs, and a silicon nitride film 22 that acts as a
`passivation film is formed on the upper layer by the plasma
`CVD method. After a bonding pad section (not shown) is
`opened in the silicon nitride film 22,
`the semiconductor
`device having the multiple wiring structure shown in FIG. 1
`is completed.
`After the fluorine-containing silicon oxide layer 16 and
`the TEOS film 18 have been formed in the above-described
`conventional manufacturing method, the step of forming a
`tungsten film by the CVD method, the step of forming an
`aluminum film by sputtering, or the step of forming a silicon
`nitride film 22 by the plasma CVD method are performed.
`These steps are performed in high temperature atmospheres
`at about 400° C. Also in processes for manufacturing semi-
`conductor devices, after the fluorine-containing silicon
`oxide layer 16 and the TEOS film 18 have been formed, heat
`treatment at a temperature of about 400° C. may be per-
`formed for stabilizing device characteristics.
`Fluorine contained in the fluorine-containing silicon
`oxide layer 16 tends to diffuse during these heat treatments.
`The barrier effect of the TEOS film 18 against fluorine is
`low, while metal or the silicon nitride film 22 has a high
`barrier effect to prevent the diffusion of fluorine. Therefore,
`when the above-described heat treatments are performed, F
`layers 24 having a high fluorine concentration are formed in
`the vicinities of the upper surface of the lower layer metal
`wiring 14, the bottom surface of the metal wiring 20, and the
`bottom surface of the silicon nitride film 22, as shown in
`FIG. 5. These F layers 24 may cause film blistering, film
`separation, or pattern separation to occur.
`In devices of the quarter-micron generation, a metal
`wiring having a structure in which AlCu is sandwiched
`between Ti-based films are normally used. In such a metal
`wiring, when, for example, a Ti/TiN film is used, an F layer
`24 is formed in the vicinity of Ti. In this case, Ti reacts with
`F, resulting in the condition to cause film separation more
`easily.
`The above-described film blistering, film separation, or
`pattern separation causes metal wiring to be short-circuited.
`Therefore,
`the conventional structures of semiconductor
`devices, and the methods for producing such semiconductor
`devices have had problems of disadvantages to easily cause
`the lowering of product yield and the deterioration of
`reliability.
`
`SUMMARY OF THE INVENTION
`
`invention has been devised to solve the
`The present
`above-described problems, and a first object of the present
`invention is to provide a semiconductor device that realizes
`high reliability and high product yield while using a
`fluorine-containing silicon oxide film as the interlayer insu-
`lation film.
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`US 6,586,838 B2
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`3
`The above object of the present invention is achieved by
`a semiconductor device having an interlayer oxide film
`formed of a fluorine-containing silicon oxide film. The
`device includes a metal wiring formed in an upper layer of
`the fluorine-containing silicon oxide film. The device further
`includes an SiH4-based silicon oxide film existing only
`between the metal wiring and the fluorine-containing silicon
`oxide film.
`
`The above object of the present invention is also achieved
`by a semiconductor device having an interlayer oxide film
`formed of a fluorine-containing silicon oxide film. The
`device includes a metal wiring formed in an upper layer of
`the fluorine-containing silicon oxide film. The device further
`includes a passivation film formed in the upper layer of the
`fluorine-containing silicon oxide film so as to cover the
`metal wiring. The passivation film comprises a low refrac-
`tion factor silicon oxide film having a refraction factor lower
`than 1.48, and a silicon nitride film formed on the low
`refraction factor silicon oxide film.
`
`invention is further
`The above object of the present
`achieved by a semiconductor device having an interlayer
`oxide film formed of a fluorine-containing silicon oxide
`film. The device includes a metal wiring formed in an upper
`layer of the fluorine-containing silicon oxide film. The metal
`wiring has a fluorination retardant metal layer that is difficult
`to react with fluorine at a bottom thereof.
`
`Other objects and further features of the present invention
`will be apparent from the following detailed description
`when read in conjunction with the accompanying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a cross-sectional view of a conventional semi-
`
`conductor device of a two-layer wiring structure;
`FIGS. 2 through 4 are cross-sectional views for describing
`a method for manufacturing the semiconductor devise
`shown in FIG. 1;
`FIG. 5 is a cross-sectional view for describing a problem
`arising in the semiconductor device shown in FIG. 1;
`FIG. 6 is a cross-sectional view showing a major part of
`a semiconductor device according to a first embodiment of
`the present invention;
`FIG. 7 is a diagram for illustrating problems involved in
`a manufacturing method employed in the first embodiment;
`FIG. 8 is a cross-sectional view showing a major part of
`a semiconductor device according to a second embodiment
`of the present invention;
`FIG. 9 is a cross-sectional view showing a major part of
`a semiconductor device according to a third embodiment of
`the present invention;
`FIG. 10 is a cross-sectional view showing a major part of
`a semiconductor device according to a fourth embodiment of
`the present invention;
`FIG. 11 is a cross-sectional view showing a major part of
`a semiconductor device according to a fifth embodiment of
`the present invention;
`FIG. 12 is a diagram illustrating the major part of a
`method for manufacturing a semiconductor device accord-
`ing to a sixth embodiment of the present invention;
`FIG. 13 is a diagram illustrating the major part of a
`method for manufacturing a semiconductor device accord-
`ing to a seventh embodiment of the present invention;
`FIG. 14 is a diagram illustrating the major part of a
`method for manufacturing a semiconductor device accord-
`ing to a eighth embodiment of the present invention;
`
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`FIG. 15 is a diagram showing a distribution of fluorine
`concentrations employed in a ninth embodiment of the
`present invention; and
`FIGS. 16A and 16B are diagrams showing a distribution
`of fluorine concentrations employed in a tenth embodiment
`of the present invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`invention will be
`The embodiments of the present
`described below referring to the drawings. The elements
`common to the drawings are represented by the same
`reference numerals, and duplicated description will be omit-
`ted.
`
`First Embodiment
`
`FIG. 6 is a cross-sectional view showing a semiconductor
`device according to a first embodiment of the present
`invention. As shown in FIG. 6, the semiconductor device of
`the first embodiment comprises a silicon substrate 10. On the
`silicon substrate 10 are formed a first interlayer insulating
`film 12 and lower layer metal wirings 14 by the combination
`of the CVD method, etch-back method, CMP method or the
`like.
`
`interlayer insulating film 12 is formed a
`On the first
`fluorine-containing silicon oxide film 16 so as to cover the
`lower layer metal wirings 14. The fluorine-containing sili-
`con oxide film 16 is a film that is deposited by the high-
`density plasma CVD method using SiH4 gas, O2 gas, and
`C2F6 gas as reaction gases. Since deposition and sputter
`etching proceed simultaneously in the above-described
`high-density plasma CVD method,
`the portion of the
`fluorine-containing silicon oxide film 16, under which the
`lower layer metal wiring 14 is present, has a triangular
`shape. The fluorine-containing silicon oxide film 16 is given
`substantially the same thickness as the lower layer metal
`wirings 14.
`On the fluorine-containing silicon oxide film 16 is formed
`a TEOS film 18 by the plasma CVD method using TEOS and
`O2 gas as reaction gases. The underlying shapes are exactly
`reflected to the surface of the film formed by such CVD
`method. Therefore, the TEOS film 18 is deposited so as to
`have a portion thereof which lies above the lower layer metal
`wirings 14 formed into a triangular shape (see FIG. 3). The
`TEOS film 18 thus deposited becomes the state shown in
`FIG. 6 when being planarized by the CMP method.
`In the first embodiment, an SiH4-based silicon oxide film
`30 of a thickness of about 200 nm is formed on the
`
`planarized TEOS film 18. The SiH4-based silicon oxide film
`30 is a film formed by a plasma CVD method using SiH4 and
`O2 as reaction gases. The SiH4-based silicon oxide film 30
`contains more dangling bonds than the TEOS film 18, and
`has a structure to capture fluorine easily. The ratio of Si and
`O that compose the SiH4-based silicon oxide film 30 can be
`changed by conditions such as the flow-rate ratio of SiH4 gas
`and O2 gas, reaction pressure, and RF power. In order to
`increase the number of dangling bonds effective for captur-
`ing fluorine,
`it
`is preferable that
`the Si content
`in the
`SiH4-based silicon oxide film 30 is richer than the Si content
`in the stoichiometric composition. More specifically, a film
`having a refraction index n=1.5 to 1.6 (wavelength )L=63Z.8
`nm) is preferably used as the SiH4-based silicon oxide film
`30.
`
`Via holes (not shown) extending to the under layer metal
`wirings 14 are formed in the SiH4-based silicon oxide film
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`5
`30, the fluorine-containing silicon oxide film 16, and the
`TEOS film 18. In the via holes are formed tungsten plugs
`(not shown). The via holes and the tungsten plugs are formed
`by combining photoengraving, dry etching, sputtering, the
`CVD method, the etch-back method, and the like.
`Metal wirings 20 are patterned on the SiH4-based silicon
`oxide film 30 so as to conducting to the above-described
`tungsten plugs. Further on the metal wirings 20 is formed a
`silicon nitride film 22 functioning as a passivation film with
`the plasma CVD method. After opening a bonding pad
`section (not shown) in the silicon nitride film 22,
`the
`semiconductor device of the first embodiment is completed.
`Fluorine contained in the fluorine-containing silicon
`oxide film 16 is diffused into the TEOS film 18 and the
`SiH4-based silicon oxide film 30 by heat treatment at about
`400° C. performed during the process for manufacturing the
`semiconductor device. Thus, the SiH4-based silicon oxide
`film 30 can capture diffused fluorine adequately. Therefore,
`according to the semiconductor device of the first
`embodiment, the formation of films containing a high con-
`centration of fluorine (corresponding to the F film 24 shown
`in FIG. 5) in the vicinity of the bottoms of metal wirings 20
`and the bottom of silicon nitride film 22 can be prevented
`effectively. Therefore, according to the semiconductor
`device and the above-described manufacturing method of
`the first embodiment, the blistering and separation of films,
`or the separation of patterns caused by fluorine can be
`prevented, and excellent reliability and high product yield
`can be realized.
`
`Second Embodiment
`
`Next, a second embodiment of the present invention will
`be described below referring to FIGS. 7 and 8.
`FIG. 7 is a diagram for illustrating problems involved in
`the above-described semiconductor device and manufactur-
`
`ing method of the first embodiment. In the first embodiment,
`the SiH4-based silicon oxide film 30 is affected by over-
`etching for patterning the metal wirings 20. Therefore, the
`thickness of the SiH4-based silicon oxide film 30,
`for
`example, of 100 nm may be thinned to 50 nm or less at the
`area not covered with metal wirings 20.
`When the SiH4-based silicon oxide film 30 has a sufficient
`thickness, even if the SiH4-based silicon oxide film 30
`captures fluorine diffused from the fluorine-containing sili-
`con oxide film 16, the fluorine content in the film can be
`restricted within the allowable range. However, if the film
`thickness becomes excessively thin due to the effect of
`over-etching, the fluorine content in the SiH4-based silicon
`oxide film 30 may exceed the allowable range when the film
`30 captures fluorine diffused from the fluorine-containing
`silicon oxide film 16. Therefore, in the second embodiment,
`the semiconductor device is manufactured in the procedures
`described below to avoid such a problem.
`FIG. 8 is a cross-sectional view showing a semiconductor
`device manufactured by the method of the second embodi-
`ment. In the second embodiment,
`the SiH4-based silicon
`oxide film 30 is deposited on the entire surface of the TEOS
`film 18 in the same procedures as in the first embodiment.
`Next, a film of a metal, such as aluminum, is formed on
`the SiH4-based silicon oxide film 30 using, for example,
`sputtering. In the procedure above, the semiconductor wafer
`is heated to about 400° C. Hereafter, this heat treatment is
`referred to as the “first heat
`treatment.” The first heat
`
`treatment may be performed separately from the formation
`of the metal film.
`
`The metal film is patterned by the combination of pho-
`toengraving and etching. As a result, metal wirings 20 are
`formed.
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`In the second embodiment, the SiH4-based silicon oxide
`film 30 is next removed except the areas underneath the
`metal wirings 20. As a result, the SiH4-based silicon oxide
`film 30 is patterned to the same patterns as the metal wirings
`20 as shown in FIG. 8.
`
`In the second embodiment, after the SiH4-based silicon
`oxide film 30 is patterned as described above, a second heat
`treatment is performed. The second heat treatment is per-
`formed at a temperature of about 400° C. During the second
`heat treatment, fluorine that has been present in the area to
`be the base of the SiH4-based silicon oxide film 30 is
`diffused again, and is captured by the SiH4-based silicon
`oxide film 30. On the other hand, fluorine that has been
`present in the exposed area of the TEOS film 18 is diffused
`into the atmosphere.
`When the above-described process steps have been
`completed, a silicon nitride film 22 is formed in the same
`procedures as in the first embodiment.
`In the second
`embodiment, the SiH4-based silicon oxide film 30 is formed
`only underneath the metal wirings 20 as described above.
`Under the metal wirings 20, the thickness of the SiH4-based
`silicon oxide film 30 is always maintained at a sufficient
`thickness. Therefore, in the second embodiment, the dete-
`rioration of the reliability of semiconductor devices and the
`lowering of product yield caused by the lack of thickness of
`the SiH4-based silicon oxide film 30 can be prevented. Also
`in the second embodiment, since fluorine in the TEOS film
`18 is diffused into the atmosphere, the formation of a layer
`having a high fluorine content in the vicinity of the boundary
`between the TEOS film 18 and the silicon oxide film 22 can
`
`be prevented. Therefore, according to the semiconductor
`device and the method for manufacturing the same of the
`second embodiment, a semiconductor device having excel-
`lent reliability and high product yield can be realized more
`stably than in First Embodiment.
`
`Third Embodiment
`
`Next, a third embodiment of the present invention will be
`described below referring to FIG. 9.
`FIG. 9 is a cross-sectional view showing a semiconductor
`device according to the third embodiment. As shown in FIG.
`9, the semiconductor device of the third embodiment com-
`prises a fluorine-barrier film 40 formed on the lower layer
`metal wirings 14. The fluorine-barrier 40 is a film having
`characteristics to prevent the diffusion of fluorine, and is
`formed from an SiH4-based silicon oxide film as used in the
`first embodiment or a silicon oxide-nitride film.
`In the semiconductor devices of the first or second
`
`embodiment, fluorine contained in the fluorine-containing
`silicon oxide film 16 may gather in the vicinity of the upper
`surface of the lower layer metal wirings 14 during the heat
`treatment, and may form an F layer.
`In the third
`embodiment, since the fluorine-barrier film 40 is present on
`the lower layer metal wirings 14,
`it is ensured that the
`formation of such an F layer can be prevented. Therefore,
`according to the third embodiment, the blistering and sepa-
`ration of films in the vicinity of lower layer metal wirings 14
`can be presented, and the semiconductor device having
`excellent reliability can be realized.
`
`Fourth Embodiment
`
`Next, Fourth Embodiment of the present invention will be
`described below referring to FIG. 10.
`FIG. 10 is a cross-sectional view showing a semiconduc-
`tor device according to a fourth embodiment. As shown in
`
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`IPR of U.S. Pat. No. 7,335,996
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`TSMC1011
`IPR of U.S. Pat. No. 7,335,996
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`US 6,586,838 B2
`
`7
`FIG. 10, the semiconductor device of the fourth embodiment
`comprises SiH4-based silicon oxide films 30 that are present
`only underneath metal wirings 20, and fluorine-barrier films
`40 that cover the upper surface of the lower metal wirings
`14. In other words, the semiconductor device of the fourth
`embodiment
`is the combination of the above-described
`structures of the second embodiment and the the third
`Embodiment.
`
`In the structure shown in FIG. 10, films for preventing the
`diffusion of fluorine are disposed between the fluorine-
`containing silicon oxide film 16 and the lower metal wirings
`14, and between the TEOS film 18 and the metal wirings 20.
`Therefore, according to the fourth embodiment, further
`higher reliability than in the second or third embodiment can
`be realized.
`
`Fifth Embodiment
`
`Next, a fifth embodiment of the present invention will be
`described below referring to FIG. 11.
`FIG. 11 is a cross-sectional view showing a semiconduc-
`tor device according to the fifth embodiment. As shown in
`FIG. 11, the semiconductor device of the fifth embodiment
`comprises SiH4-based silicon oxide films 30 that are present
`only underneath metal wirings 20, as in the semiconductor
`device of the third embodiment. The semiconductor device
`
`of the fifth embodiment also comprises a passivation film
`consisting of a silicon oxide film 50 and a silicon nitride film
`22 on the TEOS film 18.
`
`In the fifth embodiment, the TEOS film 18 is deposited on
`the fluorine-containing silicon oxide film 16, and then pla-
`narized by the CMP method as in the first to fourth Embodi-
`ments. Although the CMP method is performed under the
`conditions not
`to expose the fluorine-containing silicon
`oxide film 16, the portions of the fluorine-containing silicon
`oxide film 16 which have the triangular shapes are consid-
`ered to be exposed on the surface of the TEOS film 18 when
`various conditions vary.
`to fourth
`In this case,
`in the structures of the first
`embodiments, the fluorine-containing silicon oxide film 16
`exposed on the surface of the TEOS film 18 may come into
`contact with the silicon nitride film 22 directly. Thereby, the
`fluorine content
`increases particularly at
`the contacting
`areas, easily causing the blistering or separation of films.
`In the structure of the fifth embodiment, since the silicon
`oxide layer 50 is present underneath the passivation film
`even if the fluorine-containing silicon oxide film 16 is
`exposed on the surface of the TEOS film 18, the fluorine-
`containing silicon oxide film 16 does not come into contact
`with the silicon nitride film 22 directly. Therefore, with the
`semiconductor device of the fifth embodiment,
`further
`higher reliability and product yield than in the first to fourth
`embodiments can be realized.
`
`in the fifth embodiment, the silicon oxide
`In addition,
`layer 50 that constitutes the lower layer of the passivation
`film is formed of a low-refraction-index silicon oxide film
`with a refraction index of lower than 1.48. The lower the
`
`refraction index, the higher the coverage characteristics of
`the silicon oxide layer 50. In the fifth embodiment, excellent
`coverage characteristics must be imparted to the silicon
`oxide layer 50 in order to achieve the object to prevent the
`direct contact between the fluorine-containing silicon oxide
`film 16 and the silicon nitride film 22.
`
`Also, the better the coverage of the silicon oxide film 50
`to be the lower layer of the passivation film, the better the
`coverage of the silicon nitride film 22 that becomes the
`upper layer of the passivation film. The passivation film is a
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`film for protecting the semiconductor device. Therefore,
`good coverage characteristics are required for the passiva-
`tion film. From this point of view, excellent coverage
`characteristics must be imparted to the silicon oxide film 50.
`In the fifth embodiment, as described above, the silicon
`oxide film 50 is composed of a low-refraction-index film
`that has good coverage characteristics. Therefore, according
`to the fifth embodiment, the desired object to prevent the
`direct contact between the fluorine-containing silicon oxide
`film 16 and the silicon nitride film 22 can be achieved, and
`excellent coverage characteristics can be imparted to the
`passivation film.
`
`Sixth Embodiment
`
`Next, a method for manufacturing a semiconductor device
`according to a sixth embodiment of the present invention
`will be described referring to FIG. 12.
`FIG. 12 is a diagram illustrating the major part of the
`method for manufacturing a semiconductor device of the
`sixth embodiment. In the manufacturing method of the sixth
`embodiment, a TEOS film 18 is formed on a fluorine-
`containing silicon oxide film 16 in the same procedures as
`the first embodiment.
`
`On the TEOS film 18 planarized by the CMP method is
`formed a fluorine capturing film 60 of a predetermined
`thickness (e.g., 100 nm). The fluorine capturing film 60 is
`specifically composed of an SiH4-based silicon oxide film
`formed by the plasma CVD method using SiH4 and 02 as
`reaction gases, or a silicon nitride film formed by the plasma
`CVD method using NH3 gas as the reaction gas.
`Next,
`in the sixth embodiment, a predetermined heat
`treatment is performed at a temperature exceeding 400° C.
`(e.g., 430° C.). By the above-described heat
`treatment,
`fluorine in the fluorine-containing silicon oxide film 16 is
`diffused, and is captured by the fluorine capturing film 60. At
`this time, since the fluorine capturing film 60 has a sufficient
`thickness (e.g., 100 nm), the separation of films does not
`occur.
`
`Next, the fluorine capturing film 60 is removed by dry
`etching or wet etching. In this stage, fluorine captured in the
`fluorine capturing film 60 is also removed together with the
`fluorine capturing film 60.
`After the fluorine capturing film 60 has been removed,
`metal wirings 20 and a silicon nitride film 22 are formed on
`the TEOS film 18 by the same procedures as conventional
`manufacturing methods (see FIG. 1). It is preferable that the
`temperature given to the semiconductor wafer after remov-
`ing the fluorine capturing film 60 is 400° C. or below.
`According to the above-described manufacturing method
`of the sixth embodiment, fluorine contained in the fluorine-
`containing silicon oxide film 16 is forcedly diffused by a
`heat treatment at a high temperature exceeding 400° C., and
`fluorine diffused through the upper surface of the TEOS film
`18 is removed together with the fluorine capturing film 60.
`Therefore, even if a heat treatment at 400° C. or below is
`performed, the F layer containing an excessively high con-
`tent of fluorine is not formed in the vicinities of the bottoms
`
`of the metal wirings 20 or the silicon nitride film 22.
`Therefore, according to the sixth embodiment, a semicon-
`ductor device having high reliability can be manufactured in
`high product yield.
`Seventh Embodiment
`
`Next, a method for manufacturing a semiconductor device
`according to a seventh embodiment of the present invention
`will be described referring to FIG. 13.
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`TSMC1011
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`IPR of U.S. Pat. No. 7,335,996
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`IPR of U.S. Pat. No. 7,335,996
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`

`US 6,586,838 B2
`
`9
`FIG. 13 is a diagram illustrating the major part of the
`method for manufacturing a semiconductor device of the
`seventh embodiment. In the manufacturing method of the
`seventh embodiment, a TEOS film 18 is formed on a
`fluorine-containing silicon oxide film 16 in the same proce-
`dures as the first embodiment.
`
`On the TEOS film 18 planarized by the CMP method is
`formed a fluorine capturing film 70 of a predetermined
`