Japanese Kokai Patent Application No. Hei 9[1997]-148321
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`TSMC1009
`IPR of U.S. Pat. No. 7,335,996
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`(11) PATENT APPLICATION PUBLICATION
`NO. HEI 9[1997]-148321
`(43) Publication Date: June 6, 1997
`Technical Disclosure Section
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`No. of Claims: 10 (Total of 8 pages; OL)
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` 01 L 21/316
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`21/88
`21/90
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`(71) Applicant: 000006013
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`Mitsubishi Electric Corporation
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`2-2-3 Marunouchi, Chiyoda-ku, Tokyo
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`(72) Inventor: Koji Shibata
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`Mitsubishi Electric Corporation
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`2-2-3 Marunouchi, Chiyoda-ku, Tokyo
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`(72) Inventor: Yuko Kawai
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`Mitsubishi Electric Corporation
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`2-2-3 Marunouchi, Chiyoda-ku, Tokyo
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`(74) Agents:
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`Kaneo Miyata, patent attorney
`(and 3 others)
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`SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
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`[See end of translation for translation of legend.]
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`(19) JAPANESE
`PATENT OFFICE (JP)
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`(12) KOKAI TOKUYO PATENT
`JOURNAL (A)
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`FI
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`Identification
`Codes:
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`Sequence Nos.
`for Office Use:
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`Examination Request: Not filed
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`(51) Int. Cl.6:
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` 01 L 21/316
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`21/3205
`21/768
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`(21) Filing No.: Hei 7[1995]-305680
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`(22) Filing Date: November 24, 1995
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`(54) Title
`
`(57) Abstract
`
`Problem
`
`Peeling or cracking of SOG film 14 occurs inside
`interlayer insulating film 16 that includes fluorine-
`containing silicon oxide film 12 and SOG film 14 formed
`on said oxide film, which are formed between wiring
`layers 3 and 9.
`Solution
`
`Fluorine-free silicon oxide film 13 is formed directly
`on fluorine-containing silicon oxide film 12, and SOG
`film 14 is directly formed on top in order to improve
`close adhesion between SOG film 14 and its base.
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`TSMC1009
`IPR of U.S. Pat. No. 7,335,996
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`Claims
`
`1. A semiconductor device having a wiring layer and an upper-layer wiring layer, which
`is formed on said wiring layer via an interlayer insulating film, on a semiconductor substrate,
`characterized in that the aforementioned interlayer insulating film has a laminated structure
`comprising a fluorine-containing silicon oxide film, a fluorine-free silicon oxide film formed
`directly on said fluorine-containing silicon oxide film, and a spin-on glass film formed directly
`on said fluorine-free silicon oxide film.
`
`2. A semiconductor device manufacturing method characterized by comprising a first
`step in which after a wiring layer is formed on a semiconductor substrate, a fluorine-containing
`silicon oxide film is deposited over the entire surface; a second step in which a fluorine-free
`silicon oxide film is deposited over the entire surface of said fluorine-containing silicon oxide
`film; a third step in which a spin-on glass film is formed over the entire surface of said fluorine-
`free silicon oxide film by coating a silicon compound solution and applying a thermal treatment;
`and a fourth step in which an upper-layer wiring layer is formed subsequently.
`
`3. The semiconductor device manufacturing method described in Claim 2, characterized
`in that the fluorine-containing silicon oxide film and the fluorine-free silicon oxide film are
`formed continuously inside the same reaction chamber.
`
`4. A semiconductor device manufacturing method characterized by comprising a first
`step in which after a wiring layer is formed on a semiconductor substrate, a fluorine-containing
`silicon oxide film is deposited over the entire surface; a second step in which wet etching with
`fluorine is applied to the surface of the aforementioned fluorine-containing silicon oxide film; a
`third step in which a spin-on glass film is then formed over the entire surface by coating a silicon
`compound solution and applying a thermal treatment ; and a fourth step in which an upper-layer
`wiring layer is formed subsequently.
`
`5. A semiconductor device manufacturing method characterized by comprising a first
`step in which after a wiring layer is formed on a semiconductor substrate, a fluorine-containing
`silicon oxide film is deposited over the entire surface; a second step in which a plasma treatment
`is applied to the aforementioned fluorine-containing silicon oxide film using Ar, O2, or N2; a
`third step in which a spin-on glass film is then formed over the entire surface by coating a silicon
`compound solution and applying a thermal treatment; and a fourth step in which an upper-layer
`wiring layer is formed subsequently.
`
`6. A semiconductor device having a wiring layer and an upper-layer wiring layer, which
`is formed on said wiring layer via an interlayer insulating film, on a semiconductor substrate,
`characterized in that the aforementioned interlayer insulating film has a laminated structure in
`which a spin-on glass film is formed on a fluorine-containing silicon oxide film, a silicon oxide
`film is formed on a surface where the fluorine in the surface part of the aforementioned fluorine-
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`containing silicon oxide film is removed, and slopes are formed at corners of steps of the silicon
`oxide film.
`
`7. A method for manufacturing the semiconductor device described in Claim 6,
`characterized by comprising a first step in which after a wiring layer is formed on a
`semiconductor substrate, a fluorine-containing silicon oxide film is deposited over the entire
`surface; a second step in which sputter-etching with Ar is applied to the aforementioned fluorine-
`containing silicon oxide film; a third step in which a spin-on glass film is then formed over the
`entire surface by coating a silicon compound solution and applying a thermal treatment; and a
`fourth step in which an upper-layer wiring layer is formed subsequently.
`
`8. The semiconductor device described in Claim 1, characterized in that the
`aforementioned interlayer insulating film comprises a fluorine-containing silicon oxide film, a
`spin-on glass film formed on said fluorine-containing silicon oxide film via a fluorine-free
`silicon oxide film, and a silicon oxide film formed on said spin-on glass film.
`
`9. The semiconductor device described in Claim 8, characterized in that the silicon oxide
`film formed on the spin-on glass film comprises a fluorine-free silicon oxide film formed directly
`on the aforementioned spin-on glass film and a fluorine-containing silicon oxide film formed
`directly on said fluorine-free silicon oxide film.
`
`10. The semiconductor device manufacturing method described in one of Claims 2
`through 5 and 7, characterized in that a plasma treatment is applied to the surface of the
`aforementioned spin-on glass layer using N2 after the third step for forming the spin-on glass
`layer, and the fourth step for forming the upper-layer wiring layer is then carried out after a
`fluorine-containing silicon oxide film is deposited over the entire surface.
`
`Detailed explanation of the invention
`[0001]
`Technical field of the invention
`
`The present invention pertains to a semiconductor device, particularly, to a structure of an
`interlayer insulating film provided between wiring layers and a method for forming said
`[interlayer insulating film].
`
`[0002]
`Prior art
`
`Multi-layer wiring has been utilized in response to the recent progress in LSIs. As such,
`flattening of a step created by a base wiring layer for an interlayer insulating film formed
`between wiring layers and reduction of the capacitance between the wiring layers are required.
`Figure 6 is a cross-section showing the structure of a conventional semiconductor device. In the
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`figure, 1 represents a semiconductor substrate (referred to as substrate hereinafter) made of
`single crystal silicon, for example; 2 represents an insulating film formed on substrate 1; 3
`represents a first wiring layer that is made of aluminum, for example, and that is formed on
`insulating film 2; 4 represents a silicon oxide film containing fluoride (referred to as fluorine-
`containing silicon oxide film hereinafter) formed on first wiring layer 3; 5 represents a spin-on
`glass film (referred to as SOG hereinafter), that is, an inorganic coated insulating film formed on
`fluorine-containing silicon oxide film 4; 6 represents a silicon oxide film formed on SOG film 5;
`and 7 represents an interlayer insulating film comprising fluorine-containing silicon oxide film 4,
`SOG film 5, and silicon oxide film 6. Furthermore, 8 represents a connection hole created on
`interlayer insulating film 7; 9 represents a second wiring layer that is made of aluminum, for
`example, and that is formed on interlayer insulating film 7 so as to serve as an upper-layer wiring
`layer.
`
`[0003]
`A method for manufacturing a conventional semiconductor device having the
`
`aforementioned configuration will be shown below. First, after a layer of metal such as
`aluminum is formed to a film thickness of approximately 0.6 µm on insulating film 2 formed on
`substrate 1, patterning is applied in order to form first wiring layer 3. Next, fluorine-containing
`oxide film 4 is formed to a film thickness of approximately 0.35 µm over the entire surface by
`means of a plasma CVD method, for example, while adding fluorine-containing C2F6 gas to
`TEOS (tetraethoxysilane) used as the main raw material gas. Then, after coating solution 5a (not
`illustrated), which is prepared by dissolving silanol (Si(OH)4) in an organic solvent, for example,
`is coated to a thickness of approximately 0.15 µm over the entire surface of fluorine-containing
`oxide film 4, SOG film 5 is formed by means of baking, and the surface is flattened.
`
`[0004]
`Furthermore, silicon oxide film 6 is formed to a film thickness of approximately 0.5 µm
`
`over the entire surface of SOG film 5 by means of a plasma CVD method, for example, using
`TEOS as the main raw material gas in order to form three-layer interlayer insulating film 7
`comprising fluorine-containing oxide film 4, SOG film 5, and silicon oxide film 6. Next, after
`connection holes 8 are created at predetermined positions on interlayer insulating film 7 using a
`known photolithographic technique and an etching technique, a layer of metal such as aluminum
`is formed over the entire surface so as to bury said connection holes 8, and patterning is then
`applied in order to form second wiring layer 9.
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`[0005]
`Problems to be solved by the invention
`
`A conventional semiconductor device is configured in the aforementioned manner,
`wherein an insulating film having a low specific permittivity is formed using fluorine-containing
`oxide film 4 for interlayer insulating film 7 in order to reduce the interlayer capacitance, and
`SOG film 5 is utilized to achieve flatness. However, because silicon-fluorine bonding (referred
`to as Si-F hereinafter) is present inside fluorine-containing oxide film 4, the surface of fluorine-
`containing silicon oxide film 4 becomes moisture-repellent due to the Si-F present on the film
`surface. Thus, the adhesion with SOG film 5 formed on top becomes poor; and fluorine-
`containing oxide film 4 and SOG film 5 exhibit a large difference in terms of thermal shrinkage.
`Thus, as shown in Figure 7, there are problems that peeling 10 of SOG film 5 peeled from
`fluorine-containing oxide film 4 takes place, and SOG film 5 sustains cracking 11.
`
`[0006]
`The reaction that takes place at the interface between fluorine-containing oxide film 4
`
`and coating solution 5a when coating solution 5a for SOG film 5 is coated on fluorine-containing
`oxide film 4 is shown by Chemical equation 1 given below.
`
`[0007]
`Chemical equation 1
`
`Si-F + H2O → Si-OH + HF … Chemical equation 1
`
`
`[0008]
`As shown above, the Si-F on the surface of fluorine-containing silicon film 4 reacts with
`
`the H2O in coating solution 5a in the manner shown by aforementioned Chemical equation 1,
`causing peeling 10 and cracking 11 of the SOG film.
`
`[0009]
`The present invention was devised in order to solve the aforementioned problem, and its
`
`objective is to obtain a peeling-free/cracking-free highly reliable interlayer insulating film, said
`interlayer insulating film comprising a fluorine-containing silicon film and an SOG film and
`having a well-planarized laminate structure with a low permittivity.
`
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`IPR of U.S. Pat. No. 7,335,996
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`[0010]
`Means to solve the problems
`
`The semiconductor device pertaining to Claim 1 of the present invention has a laminate
`structure in which an interlayer insulating film has a fluorine-containing silicon oxide film, a
`fluorine-free silicon oxide film formed directly on said fluorine-containing silicon oxide film,
`and a spin-on glass film formed directly on said fluorine-free silicon oxide film.
`
`[0011]
`The semiconductor device manufacturing method pertaining to Claim 2 of the present
`
`invention has a first step in which after a wiring layer is formed on a semiconductor substrate, a
`fluorine-containing silicon oxide film is deposited over the entire surface; a second step in which
`a fluorine-free silicon oxide film is deposited over the entire surface of said fluorine-containing
`silicon oxide film; a third step in which a spin-on glass film is formed over the entire surface of
`said fluorine-free silicon oxide film by coating a silicon compound solution and applying a
`thermal treatment; and a fourth step in which an upper-layer wiring layer is formed subsequently.
`
`[0012]
`In the semiconductor device manufacturing method pertaining to Claim 3 of the present
`
`invention, the fluorine-containing silicon oxide film and the fluorine-free silicon oxide film are
`formed continuously inside the same reaction chamber.
`
`[0013]
`The semiconductor device manufacturing method pertaining to Claim 4 of the present
`
`invention has a first step in which after a wiring layer is formed on a semiconductor substrate, a
`fluorine-containing silicon oxide film is deposited over the entire surface; a second step in which
`wet etching with fluorine is applied to the surface of the aforementioned fluorine-containing
`silicon oxide film fluoride; a third step in which a spin-on glass film is then formed over the
`entire surface by coating a silicon compound solution and applying a thermal treatment ; and a
`fourth step in which an upper-layer wiring layer is formed subsequently.
`
`[0014]
`The semiconductor device manufacturing method pertaining to Claim 5 of the present
`
`invention has a first step in which after a wiring layer is formed on a semiconductor substrate, a
`fluorine-containing silicon oxide film is deposited over the entire surface; a second step in which
`a plasma treatment is applied to the aforementioned fluorine-containing silicon oxide film using
`Ar, O2, or N2; a third step in which a spin-on glass film is then formed over the entire surface by
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`coating a silicon compound solution and applying a thermal treatment; and a fourth step in which
`an upper-layer wiring layer is formed subsequently.
`
`[0015]
`In the semiconductor device pertaining to Claim 6 of the present invention, an interlayer
`
`insulating film has a laminated structure in which a spin-on glass film is formed on a fluorine-
`containing silicon oxide film, a silicon oxide film is formed on a surface where the fluorine in the
`surface part of the aforementioned fluorine-containing silicon oxide film is removed, and slopes
`are formed at corners of steps of the silicon oxide film.
`
`[0016]
`The semiconductor device manufacturing method pertaining to Claim 7 of the present
`
`invention has a first step in which after a wiring layer is formed on a semiconductor substrate, a
`fluorine-containing silicon oxide film is deposited over the entire surface; a second step in which
`sputter-etching with Ar is applied to the aforementioned fluorine-containing silicon oxide film; a
`third step in which a spin-on glass film is then formed over the entire surface by coating a silicon
`compound solution and applying a thermal treatment; and a fourth step in which an upper-layer
`wiring layer is formed subsequently.
`
`[0017]
`In the semiconductor device pertaining to Claim 8 of the present invention, the interlayer
`
`insulating film comprises a fluorine-containing silicon oxide film, a spin-on glass film formed on
`said fluorine-containing silicon oxide film via a fluorine-free silicon oxide film, and a silicon
`oxide film formed on said spin-on glass film.
`
`[0018]
`In the semiconductor device pertaining to Claim 9 of the present invention, the silicon
`
`oxide film formed on the spin-on glass film comprises a fluorine-free silicon oxide film formed
`directly on the aforementioned spin-on glass film and a fluorine-containing silicon oxide film
`formed directly on said fluorine-free silicon oxide film.
`
`[0019]
`In the semiconductor device pertaining to Claim 10 of the present invention, a plasma
`
`treatment is applied to the surface of the aforementioned spin-on glass layer using N2 after the
`third step for forming the spin-on glass layer, and the fourth step for forming the upper-layer
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`wiring layer is then carried out after a fluorine-containing silicon oxide film is deposited over the
`entire surface.
`
`[0020]
`Embodiment of the invention
`Embodiment 1
`
`Embodiment 1 of the present invention will be explained below with reference to figures.
`Here, an explanation of portions overlapping those of the prior art will be omitted arbitrarily.
`Figure 1 is a cross-section showing the structure of a semiconductor device in accordance with
`Embodiment 1 of the present invention. In the figure, 1 through 3, 8, and 9 represent the same
`components as those of a conventional semiconductor device; 12 represents a first fluorine-
`containing oxide film formed on first wiring layer 3; 13 represents a fluorine-free silicon oxide
`film formed on the surface of first fluorine-containing oxide film 12; 14 represents an SOG film
`formed on silicon oxide film 13; 15 represents a second fluorine-containing oxide film formed on
`SOG film 14; 16 represents an interlayer insulating film comprising first fluorine-containing
`oxide film 12, silicon oxide film 13, SOG film 14, and second fluorine-containing oxide film 15.
`
`[0021]
`A method for manufacturing the semiconductor device configured in the aforementioned
`
`manner will be shown based on Figure 2. First, after a layer of a metal such as aluminum is
`formed to a film thickness of approximately 0.6 µm on insulating film 2 formed on substrate 1,
`patterning is applied in order to form first wiring layer 3. Next, first fluorine-containing oxide
`film 12 is formed to a film thickness of approximately 0.3 µm over the entire surface by means
`of a plasma CVD method under conditions consisting of a temperature of 400˚C, a pressure of
`5.0 torr, a C2F6 flow rate of 400 SCCM, a TEOS flow rate of 900 SCCM, an O2 flow rate of 900
`SCCM, an output of 0.76 W/cm2 at a high-side frequency of 13.56 MHz, and an output of 0.76
`W/cm2 at a low-side frequency of 420 KHz (Figure 2(a)).
`
`[0022]
`Next, silicon oxide film 13 is formed to a film thickness of approximately 0.5 µm over
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`the entire surface of first fluorine-containing oxide film 12 by means of a plasma CVD method
`under conditions consisting of a temperature of 400˚C, a pressure of 5.0 torr, a TEOS flow rate
`of 900 SCCM, an O2 flow rate of 900 SCCM, an output of 0.76 W/cm2 at a high-side frequency
`of 13.56 MHz, and an output of 0.76 W/cm2 at a low-side frequency of 420 KHz (Figure 2(b)).
`Next, coating solution 14a (not illustrated), that is, a silicon compound solution prepared by
`dissolving silanol in an organic solvent, is applied to a thickness of approximately 0.15 µm over
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`the entire surface of silicon oxide film 13 by means of a spin-coating method and baked at a
`temperature of 400°C for 30 min in an N2 atmosphere in order to obtain planar SOG film 14
`(Figure 2(c)).
`
`[0023]
`Next, second fluorine-containing oxide film 15 is formed to a film thickness of
`
`approximately 0.5 µm over the entire surface of SOG film 14 by means of a plasma CVD
`method under the same conditions as those for the formation of first fluorine-containing oxide
`film 12 in order to form interlayer insulating film 16 comprising first fluorine-containing oxide
`film 12, silicon oxide film 13, SOG film 14, and second fluorine-containing oxide film 15.
`Subsequently, second wiring layer 9 is formed after connection holes 8 are created in a
`conventional manner (Refer to Figure 1).
`
`[0024]
`In this embodiment, because fluorine-free silicon oxide film 13 is formed between first
`
`fluorine-containing oxide film 12 and SOG film 14, coating solution 14a on SOG film 14 never
`comes into direct contact with the surface of first fluorine-containing oxide film 12 where Si-Fi
`is present. In addition, because fluorine-free silicon oxide film 13 and SOG film 14 suitably
`adhere together and have a relatively small difference in terms of thermal shrinkage, unlike a
`conventional semiconductor device, peeling and cracking of SOG film 14 never occur, so the
`reliability of interlayer insulating film 16 is improved. Also, this highly reliable interlayer
`insulating film 16 can be obtained easily.
`
`[0025]
`Furthermore, in the manufacturing method in aforementioned Embodiment 1, first
`
`fluorine-containing oxide film 12 and silicon oxide film 13 formed on top can be formed
`continuously inside the same reaction chamber of the CVD device. First fluorine-containing
`oxide film 12 is deposited for approximately 50 sec by means of a plasma CVD method, for
`example, under conditions consisting of a temperature of 400˚C, a pressure of 5.0 torr, a C2F6
`flow rate of 400 SCCM, a TEOS flow rate of 900 SCCM, an O2 flow rate of 900 SCCM, an
`output of 0.76 W/cm2 at a high-side frequency of 13.56 MHz, and an output of 0.76 W/cm2 at a
`low-side frequency of 420 KHz. Then, silicon oxide film 13 is deposited continuously for 5 sec
`under exactly the same conditions except that the C2F6 flow rate is changed to 0 SCCM. When
`first fluorine-containing oxide film 12 and silicon oxide film 13 are formed continuously in the
`same reaction chamber in this manner, the work process is simplified, so highly reliable
`interlayer insulating film 16 that exerts the aforementioned effect can be obtained more easily.
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`[0026]
`In addition, aforementioned fluorine-containing oxide films 12 and 15 and silicon oxide
`
`film 13 may be formed using multiple CVD methods or an atmospheric-pressure CVD method,
`for example, without being restricted to the use of a plasma CVD method, whereby a similar
`effect can be achieved.
`
`[0027]
`Embodiment 2
`
`Next, Embodiment 2 of the present invention will be explained. Figure 3 consists of
`cross-sections showing a semiconductor device manufacturing method in accordance with
`Embodiment 2. First, similarly to aforementioned Embodiment 1, after first wiring layer 3 is
`formed on insulating film 2 that is already formed on substrate 1, first fluorine-containing oxide
`film 12a is formed to a film thickness of approximately 0.35 µm (Figure 3(a)). Next, wet etching
`is applied to substrate 1 using 1:10 buffered hydrofluoric acid (referred to as BHF hereinafter) in
`order to etch the surface of first fluorine-containing oxide film 12a by several nm. Consequently,
`the fluorine contained in the surface part of first fluorine-containing oxide film 12a is removed,
`and a thin layer of silicon oxide film 13a is formed as a fluorine-free silicon oxide film (Figure
`3(b)). Next, similar to aforementioned Embodiment 1, SOG film 14 is formed on silicon oxide
`film 13a (Figure 3(c)). After second fluorine-containing oxide film 15 is further formed on top,
`connection holes 8 and second wiring layer 9 are formed in sequence (Figure 3(d)).
`
`[0028]
`In this embodiment, the wet etching with the BHF is applied after first fluorine-
`
`containing oxide film 12a is formed. The reaction that takes place at this time inside the BHF at
`the surface of first fluorine-containing oxide film 12a is shown by Chemical equation 2 given
`below.
`
`[0029]
`Chemical equation 2
`
`Si-F + H2O → Si-OH + HF … Chemical equation 2
`
`
`[0030]
`As shown above, the Si-F on the surface of first fluorine-containing oxide film 12a reacts
`
`with H2O in the manner shown by Chemical equation 2 inside the BHF. Consequently, the Si-F
`is replaced with stable Si-OH, and the HF formed on the surface is removed from the BHF.
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`Incidentally, the reaction shown by Chemical equation 2 is identical to the reaction shown by
`Chemical equation 1 that takes place when coating solution 5a for SOG film 5 is applied to
`fluorine-containing oxide film 4 of a conventional semiconductor device. That is, in this
`embodiment, because the reaction shown by Chemical equations 1 and 2 has already taken place
`due to the application of the etching treatment with the BHF, the reaction (Chemical equations 1
`and 2) that causes peeling and cracking of SOG film 14 can be prevented when coating solution
`14a for SOG film 14 is applied in a subsequent step. The adhesion between SOG film 14 and
`base silicon oxide film layer 13a, from which the fluorine has been removed, becomes so good
`that no peeling and cracking of SOG film 14 occur, so highly reliable interlayer insulating film
`16 can be obtained easily.
`
`[0031]
`Furthermore, although the wet etching treatment with the BHF was applied in order to
`
`remove the fluorine contained in the surface part of first fluorine-containing oxide film 12a in
`aforementioned Embodiment 2, a plasma treatment may be applied to the surface of first
`fluorine-containing oxide film 12a using Ar, O2, or N2 gas. The reaction that takes place in such
`case are shown by Chemical equations given below.
`
`[0032]
`Chemical equation 3
`
`Si-F  Ar plasma → Si + F↑ … Chemical equation 3
`
`
`Chemical equation 4
`
`
`Chemical equation 5
`
`Si-F + N → Si-N + F↑ … Chemical equation 4
`
`Si-F + O → Si-O + F↑ … Chemical equation 5
`
`
`[0033]
`As shown above, the Si-F in the surface part of first fluorine-containing oxide film 12a is
`
`decomposed to terminate the Si bond, and the fluorine is removed when it gets separated due to
`gasification. In this case, too, a similar effect, that is, the effect achieved when the wet etching
`treatment with the BHF is applied, can be achieved.
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`[0034]
`Embodiment 3
`
`Next, Embodiment 3 of the present invention will be explained. Figure 4 consists of
`cross-sections showing the semiconductor device manufacturing method in accordance with
`Embodiment 3. First, similar to aforementioned Embodiment 1, after first wiring layer 3 is
`formed on insulating film 2 that is already formed on substrate 1, first fluorine-containing oxide
`film 12b is formed to a film thickness of approximately 0.37 µm (Figure 4(a)). Next, substrate 1
`is etched by means of sputter-etching with Ar ions under conditions consisting of a pressure of
`30 mtorr, an Ar flow rate of 100 SCCM, and an output of 500W in order to remove the surface of
`first fluorine-containing oxide film 12b by a thickness of 20 nm; the fluorine contained in the
`exposed surface part of first fluorine-containing oxide film 12b is removed in order to form thin
`silicon oxide film 13b as a fluorine-free silicon oxide film; and slopes 17 are formed at corner
`sections of steps (Figure 4(b)). Next, similar to aforementioned Embodiment 1, SOG film 14 is
`formed on silicon oxide film 13b (Figure 4(c)). After second fluorine-containing oxide film 15 is
`further formed on top, connection holes 8 and second wiring layer 9 are formed in sequence
`(Figure 4(d)).
`
`[0035]
`In this embodiment, sputter-etching with Ar ions is applied to the surface of first fluorine-
`
`containing oxide film 12b. Consequently, the fluorine contained in the exposed surface part of
`first fluorine-containing oxide film 12b is removed through the reaction shown by Chemical
`equation 3 introduced in aforementioned Embodiment 2. Thus, the adhesion between [the first
`fluorine-containing oxide film] and SOG film 14 formed in a subsequent step becomes so good
`that peeling and cracking of SOG film 14 never occur. Furthermore, because slopes 17 are
`formed at the step corner sections by means of sputter-etching with Ar ions, coating solution 14a
`for SOG film 14 sets in easily between the steps even when the aspect ratio of first wiring layer 3
`is high, so the surface planarity is improved. In addition, because the removal of the contained
`fluorine from the surface part of first fluorine-containing oxide film 12b and the formation of
`slopes 17 can be achieved simultaneously by sputter-etching with Ar ions, interlayer insulating
`film 16 that exerts the aforementioned effect can be formed easily.
`
`[0036]
`Embodiment 4
`
`Next, Embodiment 4 of the present invention will be explained. Figure 5 is a cross-
`section showing the structure of a semiconductor device in accordance with Embodiment 4. In
`the figure, 1 through 3, 8, 9, and 12 through 16 represent the same components as those of
`
`TSMC1009
`IPR of U.S. Pat. No. 7,335,996
`
`

`

`aforementioned Embodiment 1; and 18 represents a fluorine-free silicon oxide film that is
`formed by means of a plasma CVD method, for example, between SOG film 14 and second
`fluorine-containing oxide film 15 formed on top. In this embodiment, fluorine-free silicon oxide
`film 18 is formed above SOG film 14 in addition to [the fluorine-free silicon oxide film formed]
`below [the SOG film] in order to improve the adhesion with second fluorine-containing silicon
`oxide film 15 and to also reduce the thermal shrinkage difference. Thus, the reliability of
`interlayer insulating film 16 is further improved.
`
`[0037]
`Furthermore, in this case, silicon oxide film 18 formed on SOG film 14 and second
`
`fluorine-containing oxide film 15 can also be formed continuously inside the same reaction
`chamber as is the case with first fluorine-containing silicon oxide film 12 and fluorine-containing
`oxide film 13 that are formed below SOG film 14 in aforementioned Embodiment 1.
`
`[0038]
`Embodiment 5
`
`Next, Embodiment 5 of the present invention will be explained. First, similar to
`aforementioned Embodiment 1, after the process for forming SOG film 14 is completed, a
`plasma treatment with N2 gas is applied to the surface of SOG film 14, and second fluorine-
`containing oxide film 15 is formed subsequently. When the plasma treatment with the N2 gas is
`applied to the surface of SOG film 14 as described above, the surface part of SOG film 14
`becomes impregnated with nitrogen, whereby permeation of moisture from the layer below is
`prevented due to the function of Si-N. As such, the Si-F in second fluorine-containing oxide film
`15, which is formed on SOG film 14, prevents the creation of harmful effects at the interface
`with SOG film 14 serving as the base by reaction with moisture that permeates from the layer
`below. Thus, the adhesion between SOG film 14 and second fluorine-containing oxide film 15
`formed on top is improved, whereby the reliability of interlayer insulating film 16 is further
`improved, and said highly reliable interlayer insulating film 16 can be formed easily as is the
`case with aforementioned Embodiment 4.
`
`[0039]
`Furthermore, although aforementioned Embodiment 1 was applied to the structure of the
`
`layers below SOG film 14 in aforementioned Embodiments 4 and 5, a similar effect can be
`achieved when aforementioned Embodiment 2 or 3 is applied.
`
`
`TSMC1009
`IPR of U.S. Pat. No. 7,335,996
`
`

`

`[0040]
`Effect of the invention
`
`As described above, according to the present invention, the interlayer insulating film
`provided between the wiring layers has a laminated structure comprising a fluorine-containing
`silicon oxide film and an SOG film that is formed on top via a fluorine-free silicon oxide film.
`Thus, an interlayer insulating film that exhibits low permittivity and excellent planarity, said
`interlayer insulating film being also highly reliable in that no peeling/cracking of the SOG film
`occurs due to excellent adhesion between the SOG film and its base, can be obtained.
`
`[0041]
`In addition, according to the present invention, after a fluorine-containing silicon oxide
`
`film is formed, a fluorine-free silicon oxide film is deposited on top, and an SOG film is formed
`on top by coating a silicon compound solution and applying a thermal treatment in order to form
`an in