USOO8068204B2
`
`US 8,068,204 B2
`(10) Patent No.:
`(12) Unlted States Patent
`
`Hirakata et al.
`(45) Date of Patent:
`*Nov. 29, 2011
`
`(54) ELECTRONIC APPARATUS WITH A
`FLEXIBLE PRINTED CIRCUIT AND A
`TRANSPARENT CONDUCTIVE LAYER
`
`(51)
`
`Int. Cl.
`G02F 1/1345
`G02F ”839
`G02F 1/1343
`
`(2006.01)
`(2006.01)
`(2006.01)
`
`(75)
`
`Inventors: Yoshiharu Hirakata, Kanagawa (JP);
`Shunpei Yamazaki, Tokyo (jp)
`
`(73) Assignee: Semiconductor Energy Laboratory
`C0" Ltd' (JP)
`
`......... 349/149; 349/152; 349/153; 349/143
`(52) US. Cl.
`(58) Field of Classification Search .................. 349/ 149,
`349/152, 153, 143
`See application file for complete search history.
`References Cited
`
`(56)
`
`(
`
`) Notlce.
`
`Subject. to any dlsclalmer, the term of this
`patent is extended or adjusted under 35
`U30 1540’) by 0 days‘
`This patent is subject to a terminal dis-
`claimer.
`
`U.S. PATENT DOCUMENTS
`awa su as re a .
`,
`,
`5 148 301 A
`9/1992 S
`t b h'
`t
`1
`5,179,460 A
`1/1993 Hinata et-al.
`5,187,604 A
`2/1993 Tamgucmet 31'
`(Continued)
`
`(21) APP1~N0~3 13/009,980
`
`(22)
`
`Filed:
`
`Jan. 20, 2011
`
`JP
`
`FOREIGN PATENT DOCUMENTS
`6-138487
`5/1994
`
`(Continued)
`
`(65)
`
`Prior Publication Data
`US 2011/0109865 A1
`May 12 2011
`
`Primary Examiner 7 Mike Qi
`(74) Attorney, Agent, or Firm 7 Husch Blackwell LLP
`
`Related US. Application Data
`.
`.
`.
`.
`(63) Contmuation 0f applicatlon NO- 12/252,793, filed on
`OCt- 16, 2008, HOW Pat. NO- 7,876,413, Wthh 15 a
`continuation of application No. 11/837,588, filed on
`Aug. 13, 2007, now Pat. No. 7,440,068, which is a
`continuation of application No. 10/384,943, filed on
`Mar. 10, 2003, now Pat. No. 7,268,851, which is a
`continuation of application No. 09/865,081, filed on
`May 24, 2001, now Pat. No. 6,567,146, which is a
`continuation of application No. 09/481,278, filed on
`Jan. 11, 2000, now Pat. No. 6,239,854, which is a
`continuation of application No. 09/165,628, filed on
`Oct. 1, 1998, now Pat. No. 6,072, 556.
`
`(30)
`
`Foreign Application Priority Data
`
`ABSTRACT
`(57)
`A height difference under a sealant is reduced in a case where
`lines are present under the sealant. There is provided a sub-
`strate having an active matrix display circuit and peripheral
`driving circuits, a counter substrate having a counter elec-
`trode provided on the substrate in a face-to-face relationship
`therewith, a sealant provided between the substrate and the
`counter substrate such that it surrounds the active matrix
`display circuit and peripheral driving circuits, a liquid crystal
`material provided inside the sealant, a plurality of external
`connection lines provided on the substrate under the sealant
`witharesin inter-layer film interposed therebetween for elec-
`trically connecting the active matrix display circuit and
`peripheral driving circuits to circuits present outside the seal-
`ant and an adjustment layer provided in the same layer as the
`plurality of external connection lines.
`
`Oct. 6, 1997
`
`(JP) ....................................... 9-289160
`
`83 Claims, 9 Drawing Sheets
`
`105 SEALENT
`113 RESIN INTER-LAYER FILM
`107 FPC
`
`
`
`. O O O C O .4
`
`Landaugupga 1 14 ITO
`5’9’9’0’9’0‘0’o’o’0‘9’2fi
`
`
`112 FIRST INTER-
`LAYER FILM
`
`111 UNDERLYING
`
`FILM
`
`“*3
`101 SUBSTRATE
`X
`
`X'
`
`401 AUXILIARY LINES
`403
`EXTERNAL CONNECTION LINES
`
`404 SECOND ADJUST-
`MENT LAYER
`
`
`’\
`
`
` w
`
`402 FIRST
`ADJUSTMENT LAYER
`
`401
`
`CMI Exhibit 1001
`1
`
`CMI Exhibit 1001
`1
`
`

`

`US 8,068,204 B2
`
`Page 2
`
`US. PATENT DOCUMENTS
`5,323,042 A
`6/1994 Matsumoto
`.
`5,396,356 A
`3/1995 Fukuchl
`5,432,626 A
`7/1995 Sasuga et al.
`.
`5,483,082 A
`1/1996 Tahzawa et 31.
`5/1996 Hu et al.
`5,517,344 A
`5,572,046 A
`11/1996 Takemura
`5,596,023 A
`1/1997 Tsubota et al.
`5,598,283 A
`1/1997 Fuju et al.
`5,619,358 A
`4/1997 Tanaka et al.
`.
`.
`.
`5,621,553 A
`4/1997 N1sh1guch1etal.
`5,636,329 A
`6/1997 Sukegawa et 31.
`5,684,547 A
`11/1997 Park et al.
`.
`5,684,555 A
`11/1997 Shlba et al.
`1
`5 706 069 A
`1/1998 H
`5,745,208 A
`4998 6353:2151 a~
`5:770:349 A
`6/1998 Suginoya et al.
`5,798,812 A
`8/1998 Nishiki et al.
`5,835,177 A
`11/1998 Dohjo et 31.
`5,929,959 A
`7/1999 Iida et al.
`5,936,693 A
`8/1999 Yoshida et al.
`5,995,189 A
`11/1999 Zhang
`6,011,607 A
`1/2000 Yamazaki et al.
`6,037,005 A
`3/2000 Moshrefzadeh et a1.
`
`6,055,034 A
`6,072,556 A
`6,088,070 A
`6,115,097 A
`6,122,030 A
`6,124,604 A
`6,124,917 A
`6,163,356 A
`6,198,517 B1
`6,239,854 B1
`6,335,716 B1
`6,567,146 B2
`6,630,687 B1
`7,268,851 B2
`
`4/2000 Zhang et 31.
`6/2000 leakqta et al.
`7/2000 Ohtanl et 31.
`-
`9/2000 Yamazak1
`9/2000 Nagata et 31.
`9/2000 Koyama et al.
`--
`9/2000 Fujloka et al.
`12/2000 Song et 31.
`-
`3/2001 Ohorl et 31.
`-
`5/2001 leakata et al.
`-
`1/2002 Yamazak1 et 31.
`-
`5/2003 leakata et al.
`10/2003 Koyama et 31.
`-
`9/2007 leakata et al.
`-
`10/2008 leakata et 31.
`7,440,068 B2
`1/2011 Hirakata et al.
`7,876,413 B2 *
`5/2004 Koyama et 31.
`2004/0084675 A1
`FOREIGN PATENT DOCUMENTS
`
`.............. 349/149
`
`6438488
`JP
`6-250221
`JP
`9460076
`JP
`10498292
`JP
`* cited by examiner
`
`5/ 1994
`9/ 1994
`“997
`7/1998
`
`CMI Exhibit 1001
`2
`
`CMI Exhibit 1001
`2
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 1 019
`
`US 8,068,204 B2
`
`
`
`
`108
`
`EXTERNAL CONNECTION
`
`101 SUBSTRATE
`
`102 COUNTER
`SUBSTRATE
`
`106 ADJUSTMENT
`LAYER
`
`105 SEALANT
`
`103 ACTIVE
`MATRIX DISPLAY
`CIRCUIT
`
`104 PERIPHERAL
`DRIVING CIRCUIT
`
`
`.—_._,—-.__.—..-I-,-.-.--'-iVi“\_\\\\1‘\“‘n
` u-v
`
`IIIIIIIIIIIEIIIIIIIIIIII‘
`
`
`110
`..
`,
`‘
`
`INJECTION ‘
`"
`HOLE
`
`
`
`
`
`
`
`
`
`
`
`IIII IIIIIIII
`
`-,
`:41
`
`lllllllllIIIllllIIIIlIllllllllllllllllllllllll ‘
`WWW
`
`ADJUSTMENT LAYER
`
`_
`.
`_
`_
`105
`FINE 2A
`\\\\\\\xx\xx\\\\x .\\\ k :7
`
`108 EXTERNAL
`
`CONNECTION
`LINES
`105
`
`/////V///// // SEALANT
`T I TIN
`AL I
`“IE-25 ////;////// HIE-2’3
`\K\X\\X\\\\\\\\\
`::-_.:_:::~;~.:‘;.i_v.::;_;\I .7T’:~-7i.r'-?.i*?5;:'If 11V
`
`WIDTH
`W1
`
`INTERVAL
`W2
`
`1F[NE 28
`
`A
`
`A'f 113 RESIN
`
`
`
`‘
`
`
`
`
`
`
`
`
`105
`ADJUSTMENT
`LAYER
`
`108
`EXTERNAL CONNECTION
`LINES
`_
`
`105 SEALANT
`
`INTER—LAYER
`FILM
`
`112 FIRSTINTER—
`LAYER FILM
`
`111 UNDERLYING
`
`flFILM
`
`101
`
`SUBSTRATE
`
`CMI Exhibit 1001
`3
`
`CMI Exhibit 1001
`3
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 2 of9
`
`US 8,068,204 B2
`
`12711123. 3A
`
`301
`ADJUSTMENT
`LAYER
`
`\ A\\\\\\\‘
`
`108 EXTERNAL
`
`CONNECTION
`
`_.f/\LINES
`2L///___f,I;.
`
`i
`
`\
`
`I. \\\\\\V‘
`
`IWNTERVAL
`
`W'DTH
`
`I
`
`\\\\\
`
`I
`INTERVAL
`
`NI “I
`
`W'DTH
`
`‘~
`
`3B
`
`NTERVAL
`
`ENE. 38
`
`A
`
`105 SEALANT
`
`A!
`
`/
`
`.
`
`113 RESIN
`If INTER—LAYER
`
`FILM
`
`
`'
`
`E.
`-
`
`30‘
`QE‘i/‘USTMENT
`
`108 EXTERNAL
`CONNECTION LINES
`
`112
`FIRST INTER—
`LAYER FILM
`111
`UNDERLYING
`FILM
`101
`SUBSTRATE
`
`CMI Exhibit 1001
`4
`
`CMI Exhibit 1001
`4
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 3 of9
`
`US 8,068,204 B2
`
`105 SEALENT
`
`113 RESIN INTER—LAYER FILM
`
`107 FPC
`
`FINE. 4A
`
`
`
`
`114 ITO
`
`112 FIRST INTER—
`LAYER FILM
`
`
`s\\\w\\\\\\\v\\\\\\\v\\\1
`\
`k
`L
`
`——,—
`
`
`
`XI
`401 AUXILIARY LINES
`X 101 SUBSTRATE
`403
`EXTERNAL CONNECTION LINES
`
`111 UNDERLYING
`FILM
`
`404 SECOND ADJUST—
`
`MENT LAYER
`
`
`403
`&“\“Vk\‘ &\\\\\3'IL\“\\R
`
`
`
`
`WH’WZWJWZL
`
`—_‘—=
`
`
`R101
`
`401
`
`T ’
`402 FIRST
`ADJUSTMENT LAYER
`
`JF[7113. 5
`107 1:120
`
`108 EXTERNAL
`505
`
`CONNECTION LINES
`509
`;
`
`
`- 1.3- 1 LL,
`1.
`.11:
`PERIPHERAL
`101 SUBSTRATE
`,
`A
`DRIVING
`102 COUNTER
`
`SUBSTRATE
`‘
`CIRCUIT
`501 FIRST
`
`ADJUSTMENT LAYER
`
`
`
`502 SECOND
`
`ADJUSTMENT LAYER
` BIIIIIIIIIIIII
`
`_______
`
`‘
`f,
`
`‘
`i
`s
`
`(I
`
`‘
`'
`,£!1!|.|,I1|.!.|l.|.!|_|||l1|.,.llluulfllllulllulllu,
`‘
`
`
`.Iw artillilzzgggaggg .
`
`
`
`
`
`506
`REGION C
`
`508
`INJECTION
`HOLE
`
`
`
`105 SEALANT
`
`103 ACTIVE
`MATRIX CIRCUIT
`
`503 SCANNING LINE
`SHORT RING
`
`507 REGIONAL D
`
`
`504 SIGNAL LINE
`SHORT RING
`
`CMI Exhibit 1001
`5
`
`CMI Exhibit 1001
`5
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 4 of9
`
`US 8,068,204 B2
`
`FINE. 6A
`
`502 SECOND
`501 FIRST
`
`
`ADJUSTMENT
`
`1ggNiIXg§1figfiLL|NE
`
`ADJUSTMENT
`
`LAYER
`
`
`
`‘.:;:-;}i.‘j?'
`‘ {ti
`I WIDTH I
`
`.rjli'f? f\
`'
`flINTERVAL
`
`105
`SEALANT
`
`BE}
`
`IFWEJGB
`
`W1
`
`W2
`
`502 SECOND
`ADJUSTMENT
`105 SEALANT
`
`LAYER
`
`B'
`
`B
`
`113 RESIN INTER~
`LAYER FILM
`
`
`
`U J2
`
`
`112 FIRST INTER—
`LAYER FILM
`
`T
`
`
`
`111 UNDERLYING
`50
`08
`i 01
`1 FIRST
`‘
`1
`WM
`ADJUSTMENT
`EXTERNAL
`1
`LAYER
`CONNECTION LINE
`
`SUBSTRATE
`
`CMI Exhibit 1001
`6
`
`CMI Exhibit 1001
`6
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 5 019
`
`US 8,068,204 B2
`
`502 SECOND
`
`501 FIRST
`ADJUSTMENT LAY
`ER
`‘
`ADJUSTMENT LAYER
`‘
`_
`I
`'5‘ g\
`51. 5:
`g
`I
`I
`I
`I
`a”
`'5:
`\\\\\\~e\\\\\\\\f1“ :1 431:“ .9..- :11
`
`504
`S‘GNALUNE
`SHORTRING
`
`105
`
`
`
`///1’:'~AIR—:51,
`\\\\\x\\\\\\\\\ \\ V‘\\\\a R3
`if“I+I«.I
`+1 R:—
`—a>IW4I;-
`5
`I
`ELI \’I.
`‘i.
`‘
`
`
`
`W6 W5 W4 W3
`
`W/M [1 CI 105 SEALANT
`
`
`
`
`
`
`501
`
`503
`
`113 RESIN INTER—
`LAYER FILM
`
`112 FIRST INTER-
`LAYER FILM
`
`111 UNDERLYING
`FILM
`101 SUBSTRATE
`
`502
`501
`V
`v
`I
`I
`v
`3
`g
`g
`5
`g
`p
`5
`I
`5
`a
`503 SCANNING
`\\\\\\\\\\\x\\\\\v\\\\\I\\\\\‘\\ L'Nifijgom
`
`
`
`///
`‘E- \\\\\\\\\\,\\,}\\\\\\\\\
`1
`1
`a
`1
`a
`a
`«,1
`I111
`’
`‘
`91W4fi>1 1+W3
`
`
`1 5
`
`_ IL. DE;
`
`105
`
`8,
`
`
`
`
`
`CMI Exhibit 1001
`7
`
`CMI Exhibit 1001
`7
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 6 of9
`
`US 8,068,204 B2
`
`503 SCANNING LINE
`SHORT RING
`
`
`
`
`D
`
`D'
`W 105
`1 13
`1 12
`
`i.\\\\\\\\\\\\\\\\m\\\\\\\\\\\\\\\\\\
`
`F1]1L:' QB
`
`502
`
`501 FIRST
`ADJUSTMENT
`LAYER
`
`503
`SCANNING LINE
`SHORT RING
`
`SECOND
`ADJUSTMENT
`LAYER 502
`
`1 O1
`
`mm; 10A 3‘ .;
`
`F D 9:3:
`
`mm; 103 x
`
`'
`
`
`
`
`
`IF17E. 708
`
`
`
`
`
`CMI Exhibit 1001
`8
`
`CMI Exhibit 1001
`8
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 7 of9
`
`US 8,068,204 B2
`
`FINEflA
`
`503 SCANNlNG
`LINE SHORT RING
`
`JEWISHB
`
`105
`
`113
`
`101
`
`
`
`\\\\\\\\\\\\\\\\\V\ \\\x mam! xxx
`rill/111111111IlllllllllnIaI'IIIII.IaIWinII’ll/l
`____- 111
`
`[(Illlfl{fl/(IIIIIIIIIIIIl/Illt
`
`'
`
`.
`
`_
`
`,
`
`
`
`’,
`/
`
`.
`\V
`;
`, .\
`
`
`,
`g \
`
`_
`
`\\
`‘ .\
`
`
`I[III/”Illllllllllllllllll . Ill
`
`
`
`CMI Exhibit 1001
`9
`
`CMI Exhibit 1001
`9
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 8 of9
`
`US 8,068,204 B2
`
`1504
`
`1508 EXTERNAL
`CONNECTION LINE
`
`1501
`
`PERIPHERAL
`DRIVING
`
`
`
`CIRCUIT
`1303:2929262030202fofofofofofofode-
`
`
`
`_‘I‘IFIL‘ILIILI\I‘I‘IFILlLlLlII‘I‘I"
`VW/I/I/I/////////////////////////////// f!
`
`
`‘
`—\I.‘I.‘IL‘ILIII\I.\I‘I3IL Iilil‘l‘l‘l‘
`I
`1502
`' _IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIi__‘_
`
`COUNTER
`g;
`5;:
`
`
`SUBSTRATE
`g;
`:5;
`1505 SEALANT
`g:
`2?:
`1510
`g;
`Egg
`INJECTION " fig
`5‘5 1503
`HOLE
`ER 021%?
`5E
`
`
`”lull“IllllIIIIIIIIIllllllgw‘lolgwlgyyl-I’l
`DISPLAY
`
`
`
`JF[7123. 13
`1509
`WI
`SHORT RING
`
`IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII'IIIIIIIIIII
`
`CIRCUIT
`
`
`
`___________________
`d---
`
`FINE. 14A
`PRIOR ART
`
`1508
`
`1513 RESIN
`
`INTERLAYER
`FILM
`
`1512 FIRST
`
`INTERLAYER
`FILM
`
`1511
`
`15‘“
`
`
`
`
`
`
`
`1508
`
`1513
`
`1512
`
`1511
`
`UNDERLYING
`LAYER
`
`1501
`SUBSTRATE
`
`I509
`
`FINE. 14B
`PRIOR ART
`
`CMI Exhibit 1001
`10
`
`CMI Exhibit 1001
`10
`
`

`

`US. Patent
`
`Nov. 29, 2011
`
`Sheet 9 of9
`
`US 8,068,204 B2
`
`2001
`MAIN BODY
`
`2005
`DISPLAY DEVICE
`
`
`
`2002
`CAMERA
`PORTION
`
`
`
`
`
`FINE. 15A
`
`2003
`IMAGE
`RECEIVING
`PORTION
`2004
`OPERATION
`SWITCH
`
`2101
`MAIN BODY
`ZBXDSD
`
`PORTION
`
`
`
`2152
`DISPLAY
`DEVICE
`
`2202
`
`SPEECH
`OUTPUT
`PORTION
`2205
`OPERATION
`SWITCH
`2203
`SPIEIESH
`PORTION
`
`.
`
`2200
`ANTENNA
`
`2201
`“ANN
`BODY
`
`,_
`
`
`
`
`" O
`“ CDC)C
`
`O O O
`
`
`
`2204
`DISPLAY
`DEVICE
`
`IFME. 150
`
`2401
`
`BODY
`.
`
`F[7123. 15B
`
`2300 IMAGE
`RECEIVING PORTION
`
`2304
`OPERATION
`
`SWITCH
`
`
`2303
`SPEECH
`INPUT
`PORTION
`
`
`
`k
`
`2302
`
`DISPLAY
`DEVICE
`2305
`
`BATTERY
`
`' 2304OPERA~
`TION
`SWITCH
`
`IF[7123. 15D
`
`,
`
`24% ‘\
`MIRROR
`
`
`
`SCREEN
`
`SCREEN
`
`
`
`
`2504
`OPTICAL
`
`SYSTEM
`
`
`12404
`MIRROR
`/
`\
`2402' LIGHT
`2403 DISPLAY
`
`SOURCE
`DEVICE
`IFIIIE 15E
`
`
`
`.,
`
`"
`DISPLAY DEVICE
`
`2501
`MAIN
`BODY
`I502
`EISGQCE
`
`F95 75’:
`
`CMI Exhibit 1001
`11
`
`CMI Exhibit 1001
`11
`
`

`

`US 8,068,204 B2
`
`1
`ELECTRONIC APPARATUS WITH A
`FLEXIBLE PRINTED CIRCUIT AND A
`TRANSPARENT CONDUCTIVE LAYER
`
`This application is a continuation of US. application Ser.
`No. 12/252,793, filed on Oct. 16, 2008 now US. Pat. No.
`7,876,413 which is a continuation ofU.S. application Ser. No.
`11/837,588, filed onAug. 13, 2007 (now US. Pat. No. 7,440,
`068 issued on Oct. 21, 2008) which is a continuation of US.
`application Ser. No. 10/384,943, filed on Mar. 10, 2003 (now
`US. Pat. No. 7,268,851 issued on Sep. 11, 2007) which is a
`continuation of US. application Ser. No. 09/865,081 filed on
`May 24, 2001 (now US. Pat. No. 6,567,146 issued on May
`20, 2003) which is a continuation ofUS. application Ser. No.
`09/481,278, filed on Jan. 11, 2000 (now US. Pat. No. 6,239,
`854 issued on May 29, 2001) which is a continuation ofU.S.
`application Ser. No. 09/165,628, filed on Oct. 1, 1998 (now
`US. Pat. No. 6,072,556 issued on Jun. 6, 2000).
`The present invention relates to a structure of a liquid
`crystal display device integral with peripheral circuits in
`which an active matrix display circuit and peripheral driving
`circuits are provided on the same substrate.
`More particularly, the present invention relates to a con-
`figuration in which peripheral driving circuits are provide
`inside a region enclosed by a sealant for sealing a liquid
`crystal material.
`There are configurations of liquid crystal display devices
`integral with peripheral circuits having an active matrix cir-
`cuit and peripheral driving circuits provided on the same
`substrate in which peripheral driving circuits are provided
`inside a region enclosed by a sealant for sealing the liquid
`crystal material. A CPU, a memory, a control circuit and the
`like may be provided in addition to peripheral driving circuits.
`In such a device, lines are provided under the region where
`the sealant is provided (hereinafter referred to as “sealant
`region”). For example, such lines include external connection
`lines for transmitting signals between the outside and inside
`of the sealant and short rings formed by extending scanning
`lines and signal lines and shorting them outside the sealant
`region in order to prevent electrostatic breakdown of TFTs
`(thin film transistors) forming an active matrix display circuit
`at manufacturing steps.
`The lines provided under the sealant region results in dif-
`ferent heights in the sealant. Such a height difference is pri-
`marily caused by two reasons.
`One reason is that the lines under the sealant region are
`localized and are not present in some locations.
`The other reason is that the line width and line intervals of
`
`the lines under the sealant region vary.
`FIG. 13 shows an example of a liquid crystal display device
`integral with peripheral driving circuits. Referring to FIG. 13,
`a substrate 1501 and a counter substrate 1502 are disposed in
`a face-to-face relationship with a sealant 1505 having an
`injection hole 1510 interposed therebetween to form a panel.
`On the substrate 1501, there is provided an active matrix
`display circuit 1503, peripheral driving circuits such as shift
`registers and decoders for driving the circuit 1503 and exter-
`nal connection lines 1508 for electrically connecting those
`circuits and circuits outside the sealant to transmit signals
`therebetween.
`The external connection lines 1508 are connected to the
`
`external circuits through an FPC (flexible printed circuit).
`There is further provided short rings 1509 which are
`formed by extending scanning lines and signal lines. The
`short rings 1509 are formed to short those lines with each
`other outside the sealant region to prevent electrostatic break-
`down ofTFTs (thin film transistors) forming the active matrix
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`
`display circuit at manufacturing steps. The configuration of
`the short rings 1509 shown in FIG. 13 is a configuration for
`multi-shot manufacture in which a plurality of panels are
`obtained from a single substrate. Although not shown in FIG.
`13, the short rings are electrically connected to the short rings
`of an adjacent panel to short the scanning lines and signal
`lines, and the short, rings are separated when the substrate is
`separated into independent panels as shown in FIG. 13.
`FIG. 14A shows sections ofa region under the sealant 1505
`where the external connection lines 1508 are provided and a
`region where no line is provided. Referring to FIG. 14A,
`provided on the substrate 1501 are an underlying film 1511
`such as a silicon oxide film, a first inter-layer film 1512
`formed by a silicon oxide film, a silicon nitride film or a
`multi-layer film consisting of them, external connection lines
`1508 and a resin inter-layer film 1513 made of resin such as
`polyimide or acrylic.
`The external connection lines 1508 are formed by a metal
`film, e. g., an aluminum film, in the range from about 200 nm
`to 700 nm. Although dependent on the application, the exter-
`nal connection lines 1508 are formed by a plurality of lines
`each having a width in the range from 50 um to 300 um
`provided as a group at intervals in the range from 30 um to 100
`pm.
`In such a configuration, the resin inter-layer film 1513 has
`a thickness of about 1 um and is provided in order to achieve
`flatness. However, regions of the resin inter-layer film 1513
`having the external connection lines 1508 is higher than
`regions having no line by a height difference d. Such a step
`can be in the range from a few hundred nm to 500 nm,
`although it is smaller than the height (thickness) of the exter-
`nal connection lines 1508.
`
`FIG. 14B shows a sectional view of a region under the
`sealant 1505 where the short rings 1509 are provided in the
`same layer and using the same material as those of the exter-
`nal connection lines 1508. Therefore, the thickness (height)
`of the short rings 1509 is the same as that of the external
`connection lines 1508. The short rings are extensions of sig-
`nal lines and scanning lines. They are a plurality of lines each
`having a width in the range from 2 pm to 10 um provided as
`a group at intervals in the range from 20 pm to 100 pm.
`There is a height difference d2 between the region where
`the short rings 1509 are provided and the region where the
`external connection lines 1508 are provided. This height dif-
`ference can be also in an approximate range from a few
`hundred nm to 500 nm. Especially, the height difference is
`increased when a plurality of the resin inter-layer films are
`formed. A step on the order of 1000 nm may be formed when
`the films are stacked to a thickness on the order of 2 pm.
`A step can be formed on the resin inter-layer film also
`between the region having the short rings 1509 and the region
`having no line.
`The substrate having the active matrix display circuit pro-
`vided thereon and the counter circuit are provided in a face-
`to-face relationship with a sealant including spacers (spheri-
`cal or cylindrical microscopic particles for maintaining an
`interval between the substrates) interposed therebetween.
`Therefore, any uneven height difference in the sealant region
`where the sealant is provided causes distortion of the counter
`substrate such as flexing and twisting to make the substrate
`interval uneven. As a result, a uniform state of display can not
`be achieved in a single screen and there will be unevenness in
`color and brightness.
`The problem of the distortion of the substrate does not
`occur even in the presence of a height difference under the
`sealant region ifthe height difference is uniformly distributed
`under the sealant region. However, since the lines extending
`CMI Exhibit 1001
`12
`
`CMI Exhibit 1001
`12
`
`

`

`US 8,068,204 B2
`
`3
`across the sealant region are provided as a group of lines
`which are locally concentrated, in general, such a height
`difference is not uniformly distributed under the sealant
`region. This results in distortion of the substrate as described
`above.
`
`The allowance (the range in which no uneven display
`occurs) for the height difference under the sealant region is on
`the order of only 1000 nm for a TN (twisted nematic) type
`liquid crystal display. Especially, for an ECB (electrically
`controlled multi-reflectivity) mode utilizing nematic liquid
`crystal, a height difference of only 200 nm causes distortion
`of the substrate which leads to uneven display and color
`variation. For example, a height difference of 200 nm
`between the external connection lines and the short rings
`makes the substrate interval in the vicinity of the short rings
`smaller than that in the vicinity of the external connection
`lines, thereby causing distortion of the substrate and uneven
`display. Therefore, it is quite important for a liquid crystal
`display device to have a small height difference under the
`sealant region in order to provide uniform display in one
`screen.
`
`It is an object of the present invention to reduce a height
`difference under a sealant region where wiring is provided
`under the sealant region (sealant).
`Especially, it is an object ofthe present invention to reduce
`a height difference under a sealant region in a configuration
`wherein wiring is provided under the sealant region and one
`or more inter-layer films made ofa resin material are provided
`on the wiring.
`It is another object of the present invention to reduce a
`height difference under the sealant region in a configuration
`wherein lines having different widths are provided under the
`sealant region and wherein one or more inter-layer films made
`of a resin material are provided above those lines.
`According to the present invention, a liquid crystal display
`device comprises:
`a first substrate having a active matrix circuit and periph-
`eral driving circuits provided thereon;
`a counter substrate having a counter electrode provided in
`a face-to-face relationship with the substrate;
`a sealant provided between the first substrate and the
`counter substrate such that it surrounds the active matrix
`
`circuit and peripheral driving circuits;
`a liquid crystal material provided inside the sealant;
`a plurality of external connection lines provided on the first
`substrate under the sealant with a resin inter-layer film inter-
`posed therebetween for electrically connecting the active
`matrix display circuit and peripheral driving circuits to cir-
`cuits present outside the sealant; and
`an adjustment layer provided in the same layer as the
`plurality of external connection lines.
`In the above-described configuration, the adjustment layer
`may be provided with the same thickness as that of the plu-
`rality of external connection lines.
`In either of the above-described configurations, the adjust-
`ment layer may be provided with the same intervals and width
`as those of the plurality of external connection lines.
`In any ofthe above-described configurations, at least one of
`the plurality of external connection lines may be electrically
`connected in parallel to one of a plurality of auxiliary lines
`provided in a layer different from that of the external connec-
`tion lines to reduce electrical resistance, and an adjustment
`layer may be provided in the same layer as the auxiliary lines.
`A plurality of lines extending across the sealant thereunder
`and having a smaller width than that of each ofthe plurality of
`external connection lines and intervals greater than the width
`may be provided in a layer different from that of the plurality
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`
`of external connection lines, and the plurality of lines may
`include extensions from scanning lines and signal lines that
`form the active matrix display circuit.
`Further, a plurality of lines extending across the sealant
`thereunder and having a smaller width than that of each ofthe
`plurality of external connection lines and intervals greater
`than the width may be provided in the same layer as that ofthe
`plurality of external connection lines, and the plurality of
`lines may include extensions from scanning lines and signal
`lines that form the active matrix display circuit. The plurality
`of lines may include a portion under the sealant where the
`width is increased.
`
`In the configuration in which at least one of the plurality of
`external connection lines is electrically connected in parallel
`to one of a plurality of auxiliary lines provided in a layer
`different from that ofthe plurality ofexternal connection lines
`to reduce electrical resistance and in which an adjustment
`layer is provided in the same layer as the auxiliary lines:
`a plurality of first lines having a width smaller than that of
`each of the plurality of auxiliary lines may be provided at
`intervals greater than the width in the same layer as the
`auxiliary lines such that they extend across the sealant there-
`under;
`the plurality of first lines may include extensions of either
`the scanning lines or signal lines forming the active matrix
`display circuit;
`the plurality of first lines have a portion under the sealant
`where the width thereof is increased;
`a plurality of second lines having a width smaller than that
`of each of the plurality of auxiliary lines may be provided at
`intervals greater than the width in the same layer as the
`auxiliary lines such that they extend across the sealant there-
`under;
`the plurality of second lines may include extensions of the
`other of group of lines, i.e., the scanning lines or signal lines
`forming the active matrix display circuit; and
`the plurality of second lines have a portion under the seal-
`ant where the width thereof is increased.
`
`In the above-described configuration, the extensions of
`either the scanning lines or signal lines forming the active
`matrix circuit may be provided in a face-to-face relationship
`with the adjustment layer provided in a layer different from
`that of either the scanning lines or signal lines.
`Further, the adjustment layer may have a region under the
`sealant in a face-to-face relationship with the extension of
`either the scanning lines or signal lines, which is electrically
`separated from adjacent regions.
`layer may be electrically
`Furthermore,
`the adjustment
`divided into a plurality of segments in the region in a face-to-
`face relationship with the extensions, of either the scanning
`lines or signal lines.
`The extensions of the other group of lines, i.e., either the
`scanning lines or signal lines forming the active matrix dis-
`play circuit may be provided in a face-to-face relationship,
`with an adjustment layer provided in a layer different from
`that of the other group of lines, i.e., the scanning lines or
`signal lines.
`In addition, the adjustment layer may have a region facing
`the extension of either the scanning lines or signal lines,
`which is electrically separated from adjacent regions.
`Moreover, the adjustment layer may be electrically divided
`into a plurality of segments in the region facing the extensions
`of either the scanning lines or signal lines.
`According to the principle ofthe present invention, regions
`under a sealant are adjusted to a height similar to that of the
`highest region under the sealant.
`
`CMI Exhibit 1001
`13
`
`CMI Exhibit 1001
`13
`
`

`

`US 8,068,204 B2
`
`5
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shows a configuration of an embodiment of the
`present invention.
`FIGS. 2A and 2B show the configuration of the embodi-
`ment of the present invention.
`FIGS. 3A and 3B show a configuration of another embodi-
`ment of the present invention.
`FIGS. 4A and 4B show a configuration of still another
`embodiment of the present invention.
`FIG. 5 shows a configuration of still another embodiment
`of the present invention.
`FIGS. 6A and 6B show the configuration of the embodi-
`ment of the present invention.
`FIGS. 7A and 7B show the configuration of the embodi-
`ment, of the present invention.
`FIGS. 8A and 8B show the configuration of the embodi-
`ment of the present invention.
`FIGS. 9A and 9B show a configuration of still another
`embodiment of the present invention.
`FIGS. 10A and 10B show a configuration of still another
`embodiment of the present invention.
`FIGS. 11A and 11B show a configuration of still another
`embodiment of the present invention.
`FIG. 12 shows a configuration of still another embodiment
`of the present invention.
`FIG. 13 shows a configuration of an example of a liquid
`crystal panel.
`FIGS. 14A and 14B show the cross section of the liquid
`crystal panel of FIG. 13.
`FIGS. 15A through 15F show examples of the application
`of the present invention.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`Preferred embodiments of the present invention will now
`be described with reference to the accompanying drawings.
`
`Example 1
`
`The present embodiment refers to an example of flattening
`of a sealant region to eliminate a height difference in a con-
`figuration wherein external connection lines are provided
`under the sealant region.
`FIG. 1 shows a configuration of an active matrix display
`circuit according to the present embodiment.
`Referring to FIG. 1, a substrate 101 and a counter substrate
`102 are disposed in a face-to-face relationship with a sealant
`105 having an injection hole 110 interposed therebetween to
`form a panel. Provided on the substrate 101 are an active
`matrix display circuit 103, peripheral driving circuits 104
`such as shift registers and decoders for driving the circuit 103
`and external connection lines 108 for electrically connecting
`those circuits to circuits (not shown) outside the sealant to
`transmit signals therebetween. The external connection lines
`108 are connected to the external circuits through an FPC
`(flexible printed circuit). Both of the active matrix circuit and
`the driving circuit may be formed on the substrate using thin
`film transistors as disclosed by a pending application Ser. No.
`08/879,583 (filed on Jun. 20, 1997) for example. The entire
`disclosure of the application Ser. No. 08/879,583 is incorpo-
`rated herein by reference.
`Referring again to FIG. 1, the peripheral driving circuits
`104 have a redundant configuration wherein two driving cir-
`cuits are provided for each of signal lines and scanning lines.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`In FIG. 1, there is provided an adjustment layer 106 which
`extends along the sealant 105 in continuation to the region
`under the sealant 105 with an inter-layer film (not shown)
`interposed in the same layer as that ofthe external connection
`lines but in a region where the external connection lines 108
`are not present.
`FIG. 2A shows an enlarged view of the region A 109 in
`FIG. 1, and FIG. 2B shows a sectional view taken along the
`line A-A' in FIG. 2A.
`
`Referring to FIG. 2A, a plurality of external connection
`lines 108 having a predetermined width w1 are provided in a
`concentrated group at predetermined intervals w2.According
`to the present embodiment, the width w1 is in the range from
`50 pm to 300 um and is 200 um for example. The intervals w2
`are in the range from 30 pm to 100 um and is 50 um here.
`Referring to FIG. 2B, a first inter-layer film 112 and a resin
`inter-layer film 113 are provided on the substrate 101 made of
`glass, quartz, silicon wafer or the like with an underlying film
`111 constituted by a silicon oxide film or the like interposed
`therebetween, and a sealant 105 is provided thereon. An ori-
`entation film (nor shown) may be provided between the seal-
`ant 105 and the resin inter-layer film 113.
`As apparent from FIG. 2B, the external connection lines
`108 and an adjustment layer 106 are formed between the first
`inter-layer film 112 and resin inter-layer film 113 in the same
`layer and using the same material such as aluminum. There-
`fore, the adjustment layer 106 has the same thickness (height)
`as the external connection lines 108 such that regions under
`the inter-layer film 113 where the external connection lines
`108 are not present have the same height as the external
`connection lines 108.
`
`Such a configuration reduces the difference in height
`between a region having the external connection lines 108
`and a region having no external connection line on the upper
`surface of the resin inter-layer film 113 under the region
`where the sealant 105 is provided. This also reduces distor-
`tion of the counter substrate when it is put together. Further,
`uniform display without variation can be achieved in one
`screen.
`
`While the adjustment layer 106 has a configuration like a
`continuous lines, the external connection lines have intervals
`w2. As a result, a height difference can occur because the
`region including the external connection lines 108 in the
`region under the sealant 105 is slightly lower than the region
`where the adjustment layer 106 is provided. However, since
`the width w1 of the external connection lines 108 is sulfi-
`
`ciently greater than the intervals w1 between the lines, such a
`height difference is quite small and does not cause uneven
`display.
`The external connection lines 108 and the adjustment layer
`106 may be provided in a layer different from that of the
`signal lines (source lines) of the TFTs forming the active
`matrix display circuit and peripheral driving circuits,
`although they are in the same layer in the configuration ofthe
`present embodiment.
`The external connection lines 108 and adjustment layer
`106 may be provided in different layers with the same thick-
`ness, which is still similarly effective as providing them in the
`same layer. For example, the adjustment layer 106 may be
`provided under the first inter-layer film 112, and the external
`connection lines 108 may be provided above the first inter-
`layer film 112. Alternatively, their positions may be reversed.
`When the external connection lines 108 and adjustment layer
`106 are provided in the same layer, it is easier to predict and
`control the height differ