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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INNOLUX CORPORATION
`Petitioner
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`v.
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`PATENT OF SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
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`CASE IPR2013-00065
`PATENT 7,923,311
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`RESPONSE OF THE PATENT OWNER
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`TABLE OF CONTENTS
`I. Background ........................................................................................................ 1
`II. Summary of Arguments ................................................................................... 2
`A. Claims 23, 24, 26-40, 42-44, 46, 49, 50, 53, and 54 of the ’311 patent
`are patentable over Taniguchi, Mori, and Van Zant ........................................ 2
`III. The ’311 Patent .................................................................................................. 8
`A. Claims of the ’311 patent .............................................................................. 8
`B. The invention of the ’311 patent ................................................................. 11
`IV. Taniguchi ......................................................................................................... 15
`A. Taniguchi does not disclose a method for forming a step-like structure
` as recited in the claims of the ’311 patent ....................................................... 15
`B. Taniguchi teaches using the first conductive layer (d1) as a hard mask
`to etch the N-type semiconductor layer (d0) .................................................... 17
`C. Inherent overetch of the first conducting layer (d1) will not create
`the claimed step-like structure in Taniguchi ................................................... 21
`D. A person of ordinary skill in the art would not create a step
`between the source/drain electrode and the N-type semiconductor layer of
`Taniguchi ............................................................................................................. 24
`E. Taniguchi solves the increased capacitance problem ............................... 26
`V. Mori .................................................................................................................. 28
`A. It is not clear that the teaching of Mori would have any impact on
`displays at the low frequency (60 Hz) at which they operate ......................... 29
`B. The Mori structure increases resistance and reduces ON current ......... 31
`VI. Claims 23, 24, 26-40, 42-44, 46, 49, 50, 53, and 54 are patentable over
`Taniguchi, Mori, and Van Zant ............................................................................ 33
`A. Creating a step-like structure in Taniguchi is not obvious ...................... 36
`B. There is no suggestion to those skilled in the art to combine Taniguchi
`with Mori ............................................................................................................. 37
`1. Taniguchi solves the parasitic capacitance problem ............................. 38
`2. Reducing the size of the electrode layer above the N-type
`semiconductor layer has little effect on parasitic capacitance .................... 40
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`3. A person of ordinary skill in the art would likely not combine
`Taniguchi with Mori because the combined structure would have higher
`resistance and lower ON current ................................................................... 41
`4. There is no reasonable expectation of success if Taniguchi were
`modified as detailed by Dr. Kanicki .............................................................. 44
`a. The modified Taniguchi process does not connect the third
`conductive layer d3 to the first conductive layer d1 ................................. 46
`b. The modified Taniguchi process has an undercut problem ............. 49
`c. Because of its complexity, the modified Taniguchi process would not
`have been obvious ........................................................................................ 52
`d. The modified Taniguchi process would change the principles of
`operation ....................................................................................................... 53
`5. Dr. Kanicki’s preference for tapering the TFT layers of Taniguchi is
`further evidence that the claimed step-like structure was not obvious ..... 56
`C. Taniguchi, Mori, and Van Zant fail to teach claim element (c)
`in each of independent claims 27, 35, and 43 ................................................... 58
`VII. CONCLUSION ............................................................................................ 60 
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`EXHIBIT LIST
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`
`Previously filed
`Exhibit 2001 – Complaint, Semiconductor Energy Laboratory Co., Ltd. v.
`Chimei Innolux Corp., et al., Case No. SACV 12-0021-JST (C.D. Cal).
`Exhibit 2002 – Defendants’ Motion to Stay Litigation Pending Outcome of Inter
`Partes Review, Semiconductor Energy Laboratory Co., Ltd. v. Chimei
`Innolux Corp., et al.
`Exhibit 2003 – Supplemental Declaration of Gregory S. Cordrey in Support of
`Defendants' Motion for Stay, Semiconductor Energy Laboratory Co., Ltd. v.
`Chimei Innolux Corp., et al.
`to Stay,
`their Motion
`in Support of
`Exhibit 2004 – Defendants’ Reply
`Semiconductor Energy Laboratory Co., Ltd. v. Chimei Innolux Corp., et al.
`Exhibit 2005 – Defendant Westinghouse Digital's Notice
`of
`Joinder,
`Semiconductor Energy Laboratory Co., Ltd. v. Chimei Innolux Corp., et al.
`Exhibit 2006 – ’311 Patent Prosecution History Excerpt - Prior Art considered
`by the Office
`Currently filed
`Exhibit 2007 – Blank
`Exhibit 2008 – Chun-sung Chiang, Chun-ying Chen, and Jerzy Kanicki,
`“Investigation of Intrinsic Channel Characteristics of Hydrogenated
`Amorphous Silicon Thin-Film Transistors by Gated-Four-Probe Structure,”
`Applied Physics Letters, Vol. 72, No. 22, pp. 2874-2876 (1998)
`Exhibit 2009 –U.S. Patent No. 5,270,567 to Mori annotated by Dr. Kanicki
`Exhibit 2010 – Chun-ying Chen and Jerzy Kancicki, “High Field-Effect-Mobility
`a-Si:H TFT Based on High Deposition-Rate PECVD Materials,” IEEE
`Electron Device Letters, Vol. 17, No. 9, pp. 437-439 (1996)
`Exhibit 2011 – Declaration of Alex Z. Kattamis, Ph.D.
`Exhibit 2012 - Willem den Boer, “Active Matrix Liquid Crystal Displays,”
`Elsevier, Chapter 2, pp. 23-48 (2005).
`
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`iii
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`Exhibit 2013 - Wang et al., “Cu/CuMg Gate Electrode for the Application of
`Hydrogenated Amorphous Silicon Thin-Film Transistors,” Electrochem.
`Solid-State Lett. Vol. 10 No. 8, pp. J83-J85 (2007).
`Exhibit 2014 - Zou, “Anisotropic Si Deep Beam Etching with Profile Control using
`SF6/O2 Plasma,” Microsystem Technologies, Vol. 10, pp. 603–607 (2004)
`Exhibit 2015 - Choi et al., “Simple Process for Making New Self-Aligned TFT
`with Improved On-Current,” Electrochemical Society Proceedings, Vol. 96-
`23, pp. 129-137, 1997
`Exhibit 2016 - Uchikoga et al., “The Effect of Contact Overlap Distance on a-Si
`TFT Performance,” Mat. Res. Soc. Symp. Proc., Vol. 258, pp. 1025-1030,
`1992
`Exhibit 2017 - Kuo et al., “Advanced Multilayer Amorphous Silicon Thin-Film
`Transistor Structure: Film Thickness Effect on Its Electrical Performance
`and Contact Resistance,” Jpn. J. Appl. Phys. Vol. 47, No. 5, pp. 3362–3367
`(2008)
`Exhibit 2018 – C. van Berkel, “Amorphous-Silicon Thin-Film Transistors: Physics
`and Properties, in Amorphous and Microcrystalline Semiconductor
`Devices,” Vol. 2 edited by J. Kanicki, Artech House, pp. 397-447(1992).
`Exhibit 2019 – Chiang et al., “Electrical Instability of Hydrogenated Amorphous
`Silicon Thin-Film Transistors for Active-Matrix Liquid-Crystal Displays,”
`Jpn. J. Appl. Phys. Vol. 37 pp. 4704-4710 (1998)
`Exhibit 2020 – Transcript of Videotaped Deposition of Jerzy Kanicki
`Exhibit 2021 – U.S. Patent No. 6,104,042 to Wen-Jyh Sah
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`iv
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`Semiconductor Energy Laboratory Co., Ltd. (the “Patent Owner”) hereby
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`responds to the Decision to Initiate Trial for Inter Partes Review of claims 23, 24,
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`26-40, 42-44, 46, 49, 50, 53, and 54 of United States Patent No. 7,923,311 (“the
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`
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`’311 patent”).
`
`I.
`
`Background
`
`Petitioner Innolux Corporation requested inter partes review of claims 23,
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`24, 26-40, 42-44, 46, 49, 50, 53, and 54 of the ’311 patent. Paper No. 3 (“Petition”
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`or “Pet.”). The Patent Owner submitted a preliminary response under 37 C.F.R. §
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`42.107(b) on February 26, 2013. Paper No. 8 (“Preliminary Response” or
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`“Preliminary Resp.”). On April 30, 2013, the Patent Trial and Appeal Board (the
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`“Board”) issued a Decision to Initiate Trial for Inter Partes Review as to claims 23,
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`24, 26-40, 42-44, 46, 49, 50, 53, and 54 of the ’311 patent for obviousness over JP
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`Patent Publication 02-234125 (“Taniguchi”), U.S. Patent No. 5,270,567 (“Mori”),
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`and Peter Van Zant, Microchip Fabrication: A Pratical Guide to Semiconductor
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`Processing, pp. 221-228 and 298 (2nd ed. 1990) (“Van Zant”). Paper No. 11
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`(“Decision” or “Dec.”). The Board denied the Petition as to all other grounds of
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`unpatentability set forth in the Petition.
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`II.
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`Summary of Arguments
`A. Claims 23, 24, 26-40, 42-44, 46, 49, 50, 53, and 54 of the ‘311
`patent are patentable over Taniguchi, Mori, and Van Zant
`
`Independent claims 23, 27, 31, 35, 39, and 43 of the ’311 patent are
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`patentable over Taniguchi, Mori, and Van Zant. These independent claims recite a
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`method of manufacturing a display device including a thin-film transistor (“TFT”)
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`having a step-like structure between the source/drain electrodes and the
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`source/drain regions. Patent Owner respectfully submits that forming a step-like
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`structure in the Taniguchi TFT is not obvious in view of Mori. Taniguchi teaches
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`away from forming a step-like structure between the first conductive layer d1 and
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`the N-type semiconductor
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`layer d0.
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` Petitioner’s expert, Dr. Kanicki,
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`acknowledged that it is not clear that the teaching in Mori would have any impact
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`on liquid crystal displays, given the low frequency at which they operate.
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`As shown in FIG. 22 of Taniguchi, the edges of the first conductive layer d1
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`(blue layer) and the N-type semiconductor layer d0 (yellow layer) are aligned(i.e.,
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`there is no step from layer d1
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`to
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`layer d0).
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` Taniguchi
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`teaches away from forming a
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`step-like structure because the
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`edges of the first conductive
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`2
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`layer d1 of the electrodes set the gate length of the TFT. Setting the gate length
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`consistently among TFTs in an active matrix display is of critical importance. See
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`Ex. 2011, Declaration of Alex Z. Kattamis (“Kattamis Decl.”), at ¶¶ 64, 87 and 88.
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`The importance of consistently setting the gate length is recognized by Taniguchi,
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`which teaches that the first conductive layer d1 (i.e., the layer directly on top of the
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`source/drain region) is to be used as a hard mask to etch the N-type semiconductor
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`layer d0 in order to consistently set the gate length of the TFTs. See Ex. 1006,
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`Taniguchi, at p. 8. Etching the first conductive layer d1 of the electrode in
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`Taniguchi laterally in order to create a step-like structure would negatively affect
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`the uniformity of the gate length of the TFTs because the first conductive layer d1
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`could no longer act as a hard mask when etching the N-type semiconductor layer
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`d0.
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`In addition, Taniguchi teaches away from forming a step-like structure
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`because further etching the first conductive layer d1 to create a step-like structure
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`would reduce the overall size of the d1 layer, which may prevent the first
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`conductive layer d1 from making secure connection with the third conductive layer
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`d3 as taught by Taniguchi. When etching the first conductive layer d1 on the
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`channel side of the source electrode, the first conductive layer d1 will also be
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`etched on the opposite side of the source electrode shown in the red circle of
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`annotated FIG. 22 above. Any additional etching of the first conductive layer d1
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`would reduce the size of the first conductive layer on the left side of the source
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`electrode (red circle above), which may prevent a secure connection between the
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`third conductive layer d3 and the first conductive layer d1. Ex. 2011, Kattamis at
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`¶¶ 126, 127, and 129. Accordingly, Taniguchi teaches away from the claimed
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`invention because the claimed invention requires a step-like structure between the
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`source/drain electrode and the source/drain region of the TFT.
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`Not only does Taniguchi teach
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`away from forming a step-like structure as
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`recited in the claims of the ’311 patent,
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`but there is no motivation to combine
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`Taniguchi with Mori. Mori teaches a TFT
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`where the edges of the source/drain electrodes are formed at positions far removed
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`from the edges of the source/drain regions, such that the source/drain electrodes do
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`not overlap the gate electrode as shown in FIG. 2 of Mori. Ex. 1003, Mori at
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`Abstract; FIG. 2 (reproduced above.) This is very different from what Taniguchi
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`teaches, which is that the lower portion of the source/drain electrodes (d1 layer)
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`completely covers the upper portion of the source/drain regions. In addition,
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`unlike Taniguchi, which teaches enlarging the gate electrode to cover the i-type
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`semiconductor layer, Mori teaches that the gate electrode 12 is relatively small and
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`does not cover the i-type semiconductor layer 14 or the source and drain electrodes
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`16 and 17. Ex. 2011, Kattamis Decl. at ¶¶ 67 and 152-153. Since Taniguchi’s
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`teaching is nearly opposite of Mori’s teaching, these two references teach
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`dramatically away from each other. Where the references teach away from their
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`combination, it is improper to combine them.
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`Furthermore, Mori also teaches that using an arrangement such as shown in
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`FIG. 2 can almost eliminate parasitic capacitance between the gate and the drain
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`electrodes. Ex. 1003, Mori, at col. 2, ll. 11-22. However, a person of ordinary
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`skill in the art would not look to Mori to modify the TFT disclosed in Taniguchi.
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`This is because a person of ordinary skill in the art would not understand that the
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`benefit taught by Mori (reducing parasitic capacitance) would have any impact on
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`the display at the low frequency (60 Hz) at which liquid crystal displays operate.
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`Petitioner’s expert Dr. Kanicki explains that liquid crystal displays operate at 60
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`Hz and that FIG. 7 of Mori (reproduced below) displays the frequency in terms of
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`kHz. Ex. 2020,
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`Videotaped Deposition of
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`Jerzy Kanicki
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`(“Kanicki
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`Dep.”), at p. 182, ll. 7-17.
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`Further, Dr. Kanicki, an
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`expert in this field, states
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`that it is not clear that the teaching of Mori would have any impact at the low
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`frequency (60 Hz) at which LCDs operate. See Ex. 2020, Kanicki Dep., at p. 182,
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`ll. 7-17. Thus, it also would not be clear to a person of ordinary skill in the art that
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`the teaching of Mori would have any impact on LCDs given the low frequency
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`(typically 60 Hz or 120 Hz) at which they operate. Mori’s specification even states
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`that “testing element in FIG. 6 has a capacitance almost equal to that of the testing
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`element in FIG. 5 in the low-frequency region, since the n-type semiconductor
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`layer 15a formed on the i-type semiconductor layer 14a … serves as an electrode
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`in the low-frequency region.” Ex. 1003, Mori, col. 4, ll. 25-31. Accordingly, there
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`would be no motivation for a person of ordinary skill in the art to modify
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`Taniguchi in hopes of reducing parasitic capacitance in TFTs used in LCDs
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`because Mori teaches (e.g. at FIG. 7) that there is no reduction in parasitic
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`capacitance at low frequencies (1000 Hz).
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`For all of these reasons, and the additional reasons discussed below, creating
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`a step-like structure between the first conductive layer d1 and the N-type
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`semiconductor layer d0 in Taniguchi would not have been obvious. The only
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`possible explanation for modifying Taniguchi to include a step-like structure as
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`recited in the claims of the ’311 patent is the impermissible use of hindsight. Even
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`Dr. Kanicki states that he would have tapered the TFT structure in Taniguchi
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`instead of forming a step-like structure. See Ex. 2020, Kanicki Dep., at p. 408, ll.
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`11-21; p. 409, ll. 8-13; p. 460, ll. 2-16.
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`Van Zant is cited by the Petitioner for disclosing, generally, profiles of
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`etches and does not remedy the deficiencies of Taniguchi and Mori set forth above.
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`See, e.g., the Petition, at page 21.
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`Thus, independent claim 23, 27, 31, 35, 39, and 43, and their dependent
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`claims, are patentable over the combination of Taniguchi, Mori, and Van Zant.1
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`Furthermore, independent claims 27, 35, and 43 each similarly recite (in
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`element (c) of claim 27, for example) “using said resist” to etch a portion of the N-
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`type semiconductor film and form source and drain regions. The “resist” referred
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`to in these similar claim elements is the same resist used to etch a portion of a
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`conductive layer to form source and drain electrodes as recited in element (b) of
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`claim 27, for example. That is, claims 27, 35, and 43 provide that the same resist
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`is used to form the source and drain electrodes and to form the source and drain
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`regions. Taniguchi and Mori, either separately or combined, do not teach or
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`1 Patent Owner respectfully submits that the Board lacks statutory authority to
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`consider the Petition because Petitioner failed to identify all real parties-in-interest
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`according to 35 U.S.C. § 312(a)(2). Notably, Chi Mei Optoelectronics USA, Inc.,
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`Acer America Corporation, ViewSonic Corporation, VIZIO
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`Inc., and
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`Westinghouse Digital, LLC are real parties-in-interest, which Petitioner failed to
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`identify in its Petition. See Paper No. 8, Preliminary Response, at 2-9. The
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`Petition should have been denied on this ground.
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`suggest this claim limitation. Instead, as discussed above, Taniguchi uses the first
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`conductive layer d1 as a hard mask to etch the N-type semiconductor layer d0 and
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`form the source and drain regions. See Ex. 1006, Taniguchi, at p. 8. Taniguchi
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`does not teach using a photoresist layer to etch the N-type semiconductor layer d0
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`because the Cr layer (d1) is used as a hard mask for etching the N-type
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`semiconductor layer (d0). No processing steps are disclosed in Mori. Van Zant
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`does not cure the foregoing deficiencies of Taniguchi and Mori.
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`For these additional reasons, independent claims 27, 35 and 43, and their
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`dependent claims, are patentable over Taniguchi, Mori, and Van Zant.
`
`III. The ’311 Patent
`A. Claims of the ’311 patent
`This proceeding involves independent claims 23, 27, 31, 35, 39, and 43,
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`along with dependent claims 24, 26, 28-30, 32-34, 36-38, 40, 42, 44, 46, 49, 50,
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`53, and 54. Independent claims 23, 27, 31, 35, 39, and 43 recite the following2:
`
`Claim elements of claim 23
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`Claim elements of claim 27
`
`Preamble: A method of manufacturing
`a display device including a thin film
`transistor over a glass substrate, the
`method comprising steps of:
`
`Preamble: Same as claim 23.
`
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`2 Note that the reference numerals (a, b, c, …) used in claim charts herein
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`correspond to those used in Section VII of the Petition. See Petition, at pp. 18-60.
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`Claim elements of claim 23
`
`Claim elements of claim 27
`
`
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`(a) forming a resist on a conductive
`layer wherein said conductive layer is
`formed on an N-type semiconductor
`film, said N-type semiconductor film is
`formed on a first semiconductor film
`comprising amorphous silicon, and said
`first semiconductor film is formed over
`a gate electrode with a gate insulating
`film comprising silicon nitride
`interposed therebetween;
`(b) Same as claim 23.
`
`(c) etching a portion of said N-type
`semiconductor film to form source and
`drain regions using said resist wherein a
`channel forming region is formed in
`said first semiconductor film between
`said source and drain regions; and
`
`(d) Same as claim 23.
`
`(e) Same as claim 23.
`
`(f) Same as claim 23.
`
`(a) forming a resist on a conductive
`layer wherein said conductive layer is
`formed on an N-type semiconductor
`film, said N-type semiconductor film is
`formed on a first semiconductor film,
`and said first semiconductor film is
`formed over a gate electrode with a gate
`insulating film comprising silicon
`nitride interposed therebetween;
`
`(b) etching a portion of said conductive
`layer to form source and drain
`electrodes using said resist;
`(c) etching a portion of said N-type
`semiconductor film to form source and
`drain regions without removing said
`resist wherein a channel forming region
`is formed in said first semiconductor
`film between said source and drain
`regions; and
`(d) forming a passivation film over at
`least said source and drain electrodes
`and said channel forming region after
`removing said resist,
`(e) wherein each of the source and drain
`regions has a bottom surface in contact
`with the first semiconductor film, each
`of the source and drain electrodes has a
`bottom surface in contact with
`corresponding one of the source and
`drain regions, and
`(f) the conductive layer is overetched
`using said resist so that a distance
`between opposed ends of the bottom
`surfaces of the source and drain
`electrodes is larger than a distance
`between opposed ends of the bottom
`surfaces of the source and drain regions.
`
`
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`9
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`Claim elements of claim 31
`
`Claim elements of claim 35
`
`
`
`Preamble: Same as claim 23.
`(a) Same as claim 27.
`(b) Same as claim 23.
`(c) etching a portion of said N-type
`Semiconductor film by dry etching to
`form source and drain regions using said
`resist wherein a channel forming region
`is formed in said first semiconductor
`film between said source and drain
`regions; and
`(d) Same as claim 23.
`(e) Same as claim 31.
`
`Preamble: Same as claim 23.
`(a) Same as claim 27.
`(b) Same as claim 23.
`(c) etching a portion of said N-type
`Semiconductor film by dry etching to
`form source and drain regions without
`removing said resist wherein a channel
`forming region is formed in said first
`semiconductor film between said source
`and drain regions; and
`(d) Same as claim 23.
`(e) wherein an upper portion of each of
`said source and drain regions extend
`beyond a lower portion of each of said
`source and drain electrodes so that a
`distance between the source and drain
`regions is shorter than a distance
`between the source and drain electrodes.
`
`
`Claim elements of claim 39
`
`Claim elements of claim 43
`
`Preamble: Same as claim 23.
`(a) Same as claim 23.
`(b) Same as claim 23.
`(c) Same as claim 27.
`(d) Same as claim 39.
`
`Preamble: Same as claim 23.
`(a) Same as claim 23.
`(b) Same as claim 23.
`(c) Same as claim 23.
`(d) forming a passivation film over said
`glass substrate to cover at least said
`source and drain electrodes, said
`channel forming region, a part of a
`surface of said source region not
`covered by said source electrode and a
`part of a surface of said drain region not
`covered by said drain electrode,
`
`
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`10
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`

`

`
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`Claim elements of claim 39
`
`Claim elements of claim 43
`
`(e) Same as claim 39.
`
`(f) Same as claim 39.
`
`(e) wherein a first portion of each of the
`source and drain regions extend beyond
`a lower portion of each of the source
`and drain electrodes so that a distance
`between the source and drain regions is
`shorter than a distance between the
`source and drain electrodes,
`(f) and a thickness of the source and
`drain regions in at least a part of the first
`portion is substantially the same as a
`thickness of at least a part of a second
`portion of each of the source and drain
`regions covered by the source and drain
`electrodes.
`
`
`The invention of the ’311 patent
`
`B.
`The claims of the ’311 patent are directed to a method of manufacturing a
`
`thin film transistor (“TFT”) as shown in FIGS. 3(A)-3(H). See Ex. 1001, the ’311
`
`patent, col. 5, l. 55 – col. 7, l. 9. More specifically, the claims of the ’311 patent
`
`recite a method for manufacturing a display device including a thin film transistor
`
`having a “step-like structure.” This step-like structure is recited as follows: “each
`
`of the source and drain regions has a bottom surface in contact with the first
`
`semiconductor film, each of the source and drain electrodes has a bottom surface in
`
`contact with corresponding one of the source and drain regions, and the conductive
`
`layer is overetched using said resist so that a distance between opposed ends of the
`
`bottom surfaces of the source and drain electrodes is larger than a distance between
`
`
`
`11
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`

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`opposed ends of the bottom surfaces of the source and drain regions” (claims 23
`
`and 27); “an upper portion of each of said source and drain regions extend beyond
`
`a lower portion of each of said source and drain electrodes so that a distance
`
`between the source and drain regions is shorter than a distance between the source
`
`and drain electrodes” (claims 31 and 35); and “a first portion of each of the source
`
`and drain regions extend beyond a lower portion of each of the source and drain
`
`electrodes so that a distance between the source and drain regions is shorter than a
`
`distance between the source and drain electrodes” (claims 39 and 43). Id; Ex.
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`2011, Kattamis Decl., ¶¶ 40-43. An annotated version of FIG. 3(H) from the ’311
`
`patent reproduced below shows the claimed step-like structure.
`
`
`
`As shown in the above figure, the ends of the source and drain regions 11
`
`and 12 extend beyond the ends of the source and drain electrodes 9 and 10, so the
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`distance between the source and drain regions (distance between the red lines) is
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`shorter than the distance between the source and drain electrodes (distance between
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`blue lines). The claimed manufacturing method of the ’311 patent used to form the
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`
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`12
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`

`

`
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`step-like structure includes forming a gate electrode 3 over a glass substrate 1 and
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`forming a gate insulating film 4, which may include silicon nitride, over the gate
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`electrode 3. Next, a first semiconductor film (or intrinsic amorphous silicon film
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`5) is formed over the gate insulating film 4 and the gate electrode 3, followed by
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`forming an N-type semiconductor film (or doped amorphous silicon layer 6, which
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`is the layer from which source region 11 and drain region 12 are formed) over the
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`first semiconductor film. See Ex. 1001, the ’311 patent, col. 5, l. 55- col. 6, l. 50
`
`and FIGS. 3(A)-3(C).
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`Subsequently,
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`the
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`first
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`semiconductor film and the N-type
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`semiconductor film are patterned using a resist formed by a photomask P2 to form
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`a TFT island as shown in FIG. 3(D), and a conductive layer, such as a chromium
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`layer 7, is then formed over the patterned N-type semiconductor film as shown in
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`FIG. 3(E). Id., at col. 6, ll. 50-55. A
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`portion of the conductive layer 7 is then
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`etched to form source and drain electrodes 9 and 10 using a resist 8 formed by a
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`photomask P3. Without removing the resist 8, a portion of the patterned N-type
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`semiconductor film is etched to form
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`a source region 11, drain region 12,
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`and a channel formation region
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`
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`13
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`

`

`
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`between the source and drain regions. Id., at col. 6, ll. 55-62; FIG. 3(F).
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`In one embodiment, a wet etching process may be carried out without
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`peeling the resist 8 off to perform an overetching process to make the distance
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`between the source and drain electrodes 9 and 10 larger than the distance between
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`the source and drain regions 11 and 12 as shown in FIG. 3(G) of the ’311 patent
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`reproduced herein. Id., at col. 6, ll. 63-66.
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`As noted above, the ’311 patent teaches using the same resist for etching
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`both the source and drain electrodes 9 and 10 and the source and drain regions 11
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`and 12. Using the same resist for these etching processes reduces the number of
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`photomask processes necessary to form the TFT and helps to control accurately the
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`length of the channel formation region. Ex. 2011, Kattamis Decl., ¶¶ 29 and 50-
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`54. Also, using the same resist for these etching processes prevents a mask
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`misalignment when forming the source and drain electrodes 9 and 10 and source
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`and drain regions 11 and 12, which would cause an undesirable variation of TFT
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`performance characteristics. Id.
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`The
`
`claimed method
`
`also
`
`includes removing
`
`the resist 8 as
`
`shown in FIG. 3(G) and then forming a passivation film 13 to cover the source and
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`drain electrodes 9 and 10, channel
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`formation region 5, and a part of the
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`
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`14
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`

`

`
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`source and drain regions 11 and 12 as shown in FIG. 3(H). Ex. 1001, the ’311
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`patent, at col. 7, ll. 1-9.
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`IV. Taniguchi
`A. Taniguchi does not disclose a method for forming a step-like
`structure as recited in the claims of the ’311 patent
`
`Taniguchi does not disclose a step-like structure between the source and
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`drain electrodes and the source and drain regions as claimed in the ’311 patent.
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`Instead, Taniguchi discloses a TFT having a different structure where the edges of
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`the source and drain electrodes are aligned with the edges of the source and drain
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`regions, respectively. In addition, Taniguchi discloses a TFT having multilayered
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`source and drain electrodes SD3 and SD4 that include a first conductive layer d1, a
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`second conductive layer d2, and a third conductive layer d3. Ex. 1006, Taniguchi,
`
`at p. 22. As shown in FIG. 22 of Taniguchi, it is these three layers of the source
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`and drain electrodes that appear to form a step-like structure with one another but
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`not with the source and drain regions as required by the claims of the ’311 patent.
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`As shown below in the
`
`annotated portion of Taniguchi’s
`
`FIG. 22, the first conductive
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`layer d1 (shown in blue) of the
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`source and drain electrodes SD3
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`
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`15
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`

`

`
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`and SD4 entirely covers the N-type semiconductor layer d0 (shown in yellow),
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`which corresponds to the source and drain regions as claimed in the ’311 patent. In
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`other words, the ends of the first conductive layer d1 are aligned with the ends of
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`the N-type semiconductor layer d0.
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`Accordingly, claim elements 23(e)(f), 27(e)(f), 31(e), 35(e), 39(e) and 43(e),
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`which recite the step-like structure between the source and drain electrodes and the
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`source and drain regions are not disclosed or suggested in Taniguchi.
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`Petitioner’s expert, Dr. Kanicki, ignored the d1 layer of Taniguchi in stating
`
`that Taniguchi discloses creating a step-like structure as recited in these claim
`
`elements between layer d2 and layer d0. See Exhibit 1014, Declaration of Jerzy
`
`Kanicki, Ph.D (“Kanicki Decl.”) at ¶¶ 64, 66, 70 and 73. However, Dr. Kanicki’s
`
`argument completely ignores the existence of the first conductive layer (d1), which
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`Taniguchi discloses to be the lower portion of the source and drain electrodes SD3
`
`and SD4. See Ex. 1006, Taniguchi, at p. 22 and FIG. 22. When asked why he did
`
`not discuss layer d1 in paragraph 70 of his declaration regarding claim elements
`
`31(e) and 35(e), Dr. Kanicki did not have an explanation and only could answer: “I
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`don't know. Maybe I was not -- I was not -- I didn't think about it, you know.” See
`
`Ex. 2020, Kanicki Dep., at p. 452, ln. 17 – p. 453, ln. 22. Thus, Dr. Kanicki’s
`
`assertion in paragraphs 64, 66, 70 and 73 of his declaration that Taniguchi
`
`
`
`16
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`

`

`
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`discloses claim elements23(e)(f), 27(e)(f), 31(e), 35(e), 39(e) and 43(e) is incorrect
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`and the Board should give no weight to Dr. Kanicki’s foregoing assertion.
`
`B.
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`Taniguchi teaches using the first conductive layer (d1) as a hard
`mask to etch the N-type semiconductor layer (d0)
`
`As is well known in the art, gate lengths are perhaps the most critical
`
`dimension in a transistor. Ex. 2011, Kattamis Decl. at ¶¶ 64 and 87. Dr. Kanicki
`
`agrees that control of the gate length is very important because if the gate length
`
`varies from one TFT to another, then the drain current would vary, which as Dr.
`
`Kanicki states is an important, undesirable effect for the performance of the
`
`transistor. See Ex. 2020, Kanicki Dep., at p. 347, ll. 6-18. The control of gate
`
`lengths in the manufacturing process is a critical concern because slight variations
`
`in the gate lengths can lead to non-uniform TFT characteristics across the display
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`area. Id.
`
`In an effort to address this issue, Taniguchi teaches that the first conductive
`
`layer d1 (i.e., the layer on top of the source/drain region) is to be used to define the
`
`gate length of the TFT device to en