IN THE UNITED STATES PATENT & TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`Sep. 17, 2007
`) FILED ELECTRONICALLY
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`Semiconductor Energy ) PER 37 C.F.R. § 42.6(b)
`Laboratory Co., Ltd.
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`
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`Electro-Optical Device )
`and Thin Film
`)
`Transistor and Method )
`for Forming the Same
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`
`
`In re Inter Partes Review of:
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`U.S. Patent No.: 7,923,311
`
` Apr. 12, 2011
`Issued:
`
`
` Hongyong Zhang
`Inventors:
` Naoto Kusumoto
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`
`
`Application No.: 11/898,833
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`
`Filed:
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`Assignee:
`
`
`Title:
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`
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`Mail Stop Patent Board (37 C.F.R. § 42.6(b)(2))
`Patent Trial and Appeal Board
`U.S.P.T.O.
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DECLARATION OF JERZY KANICKI, Ph.D.
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`Background and Qualifications
`(1) My name is Jerzy Kanicki. I am currently a Professor at the
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`
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`I.
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`University of Michigan in the Department of Electrical Engineering and Computer
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`1
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`Science. I have studied, taught, and practiced in the relevant flat panel display
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`technology for over 25 years.
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`(2)
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`I received my Doctorate of Science (D. Sc.) from the Free University
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`of Brussels, Belgium in 1982. My educational background also includes a B.S.
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`(1976) and M.S. (1978) in Chemistry from the Free University of Brussels,
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`Belgium.
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`(3)
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`Since 1995, I have been a member of the faculty at the University of
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`Michigan, College of Engineering at Ann Arbor, Michigan. During that period, I
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`have held the position of Professor in the Department of Electrical Engineering and
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`Computer Science (EECS). Between 1995 and 1999, I was group team leader
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`within the University of Michigan Center of Display Technology and
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`Manufacturing (DTM). During my tenure at the University of Michigan, I have
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`conducted leading work on various light transmissive, reflective, and emissive flat
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`panel display technologies including hydrogenated amorphous silicon (a-Si:H),
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`thin-film transistors (TFTs), active-matrix a-Si:H TFTs liquid crystal displays
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`(AM-LCDs), and active-matrix a-Si:H TFTs light emitting displays (AM-OLEDs).
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`(4)
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`I have taught a number of different courses in solid-state devices and
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`circuits at the undergraduate and graduate levels within the EECS department at
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`the College of Engineering. I have introduced two new courses in the Electrical
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`Engineering and Computer Science Department, “Amorphous and Microcrystalline
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`
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`2
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`Exhibit 1014, page2
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`Semiconductor Thin-Film Devices” in 1996 and "Flat Panel Display” in 1997, both
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`of which are still being offered annually. I also direct the research of several
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`graduate and undergraduate students in the area of amorphous inorganic and
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`organic semiconductor devices and circuits for flat panel displays. More
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`information on this subject can be found on my research group web pages:
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`www.eecs.umich.edu/omelab/
`
`(5)
`
`From 1983 to 1995, I was a Research Staff Member at the IBM T.J.
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`Watson Research Center in Yorktown Heights, New York, involved in the research
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`and development of flat panel display materials and devices. During that period, I
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`was a member of a team that developed a-Si:H TFT technology for AM-LCDs, and
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`the initial fundamental understanding and manufacturing methods of the a-Si:H
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`TFT AM-LCDs for IBM's Think Pad laptop computers.
`
`(6)
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`I am a member of several professional organizations including the
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`Society for Information Display (SID) and Institute of Electrical and Electronics
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`Engineers (IEEE). My areas of expertise include material sciences, devices, and
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`circuits for flat panel displays. In these fields of research, I edited or co-edited
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`several books, authored over 250 technical papers and gave over 350 presentations
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`(among which over 70 were invited presentations) relating to thin film
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`semiconductor devices and/or flat panel displays. I have also been the chair or co-
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`chair at numerous national and international conferences / symposiums. I am
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`
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`3
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`Exhibit 1014, page3
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`editor for IEEE Transaction on Electron Device, and I am a reviewer for several
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`prestigious international archival journals. I am also a reviewer of proposals for
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`several federal agencies, such as the National Science Foundation, DoD and
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`DARPA. Among other distinctions, I was awarded the IBM External Honors,
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`which recognizes the technical leadership of staff members in IBM's Research
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`Division, three times. My research work at the University of Michigan has been
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`supported by different grants from the state of Michigan, federal agencies, and flat
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`panel displays related multinational industry.
`
`(7) My latest curriculum vitae, which includes a list of my publications
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`and presentations, is attached at Exhibit A. I believe this list includes the papers in
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`which I have participated as an author or coauthor within the preceding ten years.
`
`II. My Status as an Independent Expert Witness
`(8)
`I have been retained in this matter by Chimei Innolux Corp.
`
`(“Petitioner”) to provide an analysis of the scope and content of the ‘311 patent
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`relative to the state of the art at the time of the earliest application underlying the
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`‘311 patent.
`
`(9)
`
`I am being compensated at the rate of $425 per hour for my work. My
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`fee is not contingent on the outcome of any matter or on any of the technical
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`positions I explain in this declaration. I have no financial interest in Petitioner.
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`(10) I have been informed that Semiconductor Energy Laboratory Co., Ltd.
`
`
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`4
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`Exhibit 1014, page4
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`(hereinafter referred to as “Patentee”) owns the ‘311 patent. I have no financial
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`interest in the Patentee or the ‘311 patent nor have I ever had any contact with the
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`Patentee, or the inventors of the ‘311 patent, Hongyong Zhang and Naoto
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`Kusumoto.
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`III. Description of the Relevant Field and the Relevant Timeframe
`(11) I have carefully reviewed the ‘311 patent, its file history as well as the
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`file history of the related U.S. Patent No. 6,756,258 (the “‘258 patent”).
`
`(12) For convenience, I have listed all of the information that I considered
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`in arriving at my opinions in Appendix B.
`
`(13) Based on my review of these materials, I believe that the relevant field
`
`for purposes of the ‘311 patent is semiconductor processes and devices related to
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`flat panel displays. I have been informed that the relevant timeframe is Jun. 19,
`
`1991.
`
`(14) As described in Section I above, I have extensive experience in the
`
`relevant field. Based on my experience, I have a good understanding of the
`
`relevant field in the relevant timeframe.
`
`IV. The Person of Ordinary Skill in the Relevant Field in the Relevant
`Timeframe
`(15) I have been informed that “a person of ordinary skill in the relevant
`
`field” is a mythical person to whom an expert in the relevant field could assign a
`
`routine task with reasonable confidence that the task would be successfully carried
`
`
`
`5
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`Exhibit 1014, page5
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`out. I have been informed that the level of skill in the art is evidenced by the prior
`
`art references. The prior art discussed herein demonstrates that a person of
`
`ordinary skill in the art, at the time the ‘311 patent was filed, was aware of
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`amorphous silicon thin film transistors design, including techniques and methods
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`of construction to be used for AM-LCDs.
`
`(16) Based on my experience, I have a good understanding of the
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`capabilities of a person of ordinary skill in the relevant filed. I have supervised
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`and directed many such persons over the course of my career.
`
`V. Background of LCD Technology
`(17) In each AMLCD display, an image is divided into small elements
`
`called pixels. In a color AMLCD display, each pixel is further divided into three
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`sub-pixels, one for each of the three primary colors red, green, and blue. Each
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`pixel (in a monochrome display) or sub-pixel (in a color display) contains a TFT, a
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`storage capacitor, and a pixel electrode.
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`(18) The TFT serves as a switch that, when turned ON, allows an electrical
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`current to flow into and charge the capacitor to a specific voltage. When the TFT
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`switch is turned OFF, current cannot flow through it; thus, the voltage established
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`at the capacitor is maintained until the next frame period, at which time the switch
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`will be turned ON again in order to update the voltage stored in the capacitor.
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`(19) The voltage stored in the capacitor also appears at the pixel electrode.
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`
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`6
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`Exhibit 1014, page6
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`This voltage sets an electric field across the liquid crystal material that is on-top of
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`the electrode; the higher the stored voltage, the higher the electric field. The
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`magnitude of the electric field across the pixel electrode will determine the optical
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`properties of the Liquid Crystal Display’s (LCD) material and this, in turn, will
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`determine the amount of light that will pass through the pixel or sub-pixel.
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`(20) The number of pixels in an AMLCD display depends upon the display
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`format. For example, the VGA format contains 640x480 pixels in a monochrome
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`display and 640x480x3 in a color display. There are many display formats ranging
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`from the aforementioned VGA (640x480) format up to an HDTV format, which
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`includes up to 1920x1080x3 pixels with over six million TFTs.
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`(21) The display format (i.e., the total number of pixels) and the display
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`frame rate (i.e., how many times per second the image content will be updated)
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`determine the required speed of the TFT switch. A typical display frame rate is 60
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`Hz, which implies that the image content will be updated every 1/60 of a second,
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`or 0.017 sec. A typical computer monitor has the SXGA format (1280x1024
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`pixels). When such a display operates at a 60 Hz frame rate, the time that is
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`allocated for updating or changing the voltage stored at the pixel’s capacitor is
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`0.017/1024 sec, or about 17 microseconds. In order to ensure correct light output
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`for the particular pixel, a pixel TFT must provide enough current to charge its pixel
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`capacitor to the correct voltage level within the allocated time. TFTs made in
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`
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`7
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`Exhibit 1014, page7
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`

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`hydrogenated-amorphous silicon can produce such results, but only if they are
`
`properly fabricated.
`
`(22) A wide range of AMLCD displays use hydrogenated-amorphous
`
`silicon TFTs. In fact, most types of AMLCD displays use hydrogenated-
`
`amorphous silicon TFTs due to their inherently lower manufacturing cost.
`
`VI. Background of TFT Fabrication
`(23) Hydrogenated amorphous silicon (a-Si:H) is increasingly being used
`
`in the applications that require large-area and low-temperature thin-film
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`processing. It can be deposited on inexpensive substrates such as glass at low
`
`temperature and low cost. A-Si:H has a low dark conductivity, a high
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`photoconductivity, and a high absorption coefficient in the range of visible photon
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`energies. Hence, its optical and electrical properties make it perfect for
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`applications such as solar cells, image sensors, X-ray detectors, ultraviolet light
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`detectors, position sensors, edge detectors, and TFTs based circuits.
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`(24) Electrical properties such as a very low OFF-current, a very high ON-
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`OFF current ratio (> 106), a low density of gap states, and a low threshold voltage
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`make a-Si:H TFTs very attractive for AMLCDs, where they are used as switching
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`devices in combination with the liquid-crystals (LCs). The TFT-LCD, an
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`abbreviation of thin-film transistor addressed liquid-crystal display, is a flat panel
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`display in which the display medium is liquid-crystal molecules and a TFT switch
`
`
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`8
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`Exhibit 1014, page8
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`controls each picture element (pixel).
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`(25) So far, the most popular structure for a-Si:H TFTs AMLCDs with
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`state-of-the-art performance is the inverted-staggered device structure. Depending
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`on the fabrication process, this structure is divided into two types: back-channel
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`etched (BCE) and tri-layered (TL) a-Si:H TFT structures, as shown in Figure 7.
`
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`Figure 7. Structures of back-channel-etched (BCE) and tri-layered (TL) a-Si:H
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`TFTs.
`
`(26) In manufacturing a-Si:H TFTs for LCDs, the processes or steps used
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`to etch the metal, amorphous semiconductor, or gate insulator films are critical to
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`the device quality control and product manufacturing yield. Precise etching
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`control allows engineers to fabricate devices with high reproducibility,
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`repeatability, and uniform properties.
`
`(27) Traditionally in the a-Si integrated circuits (ICs) industry, chemical
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`etching processes have been described as being either wet or dry. Wet chemical
`
`etching entails the use of a liquid-phase solution as the primary etchant, and dry
`
`chemical etching typically involves the use of gaseous plasma as the etchant.
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`Etching processes, both wet and dry, consist of three main steps: (1) application of
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`
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`9
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`Exhibit 1014, page9
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`etchant to the surface of the film to be etched, (2) physical interaction and/or
`
`chemical reaction between the etchant and the film, and (3) removal of the etch
`
`process by products, which are generally in gas or liquid phase, from the etched
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`surface. In the first step, i.e., the step in which the etchants are applied to the
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`surface of a film, “masks” are commonly used to define the areas on the film
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`where the etching reactions can and cannot occur. Masks can be made of photo-
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`resist, metal, or other etchant resistant materials.
`
`(28) Wet chemical etching was the standard pattern transfer technique
`
`when early generations of a-Si integrated circuits (ICs) and flat panel displays
`
`(FPDs) were fabricated. As previously explained, wet etching involves the use of a
`
`liquid etchant to pattern films into a desirable shape or size. Some benefits to wet
`
`chemical etching are that it can be very selective and that it does not attack the
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`photoresist, which is the most common etch-mask material. Because wet etching
`
`is a chemical process, it is possible to choose specific etching solutions that will
`
`only etch the desired film (metal or other), as opposed to other films that the
`
`etching solution may come into contact with, such as the films beneath the target
`
`film.
`
`(29) Wet chemical etching, however, lacks anisotropy, which means that
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`there is generally very little control over the direction in which an etchant will etch
`
`a film. In other words, wet chemical processes typically etch in all directions at the
`
`
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`10
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`Exhibit 1014, page10
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`same rate (i.e., they etch isotropically). It is nearly impossible to control the
`
`anisotropy of wet etching for amorphous silicon semiconductors such as Si:H or
`
`other amorphous materials, including metals. Thus, wet etching processes for
`
`amorphous silicon TFTs are referred to as isotropic; a term that indicates that the
`
`etching process etches films, involved in TFT manufacturing, in all directions at an
`
`equal etching rate, i.e., the rate of lateral etching equals the rate of vertical etching.
`
`(30) The physical component of the dry etching process comes from
`
`accelerating the ions toward the substrate layer to be etched, a process referred to
`
`as ion bombardment. Ion bombardment is essentially a sandblasting process that
`
`does two things to inhibit lateral etching: (1) it deposits non-volatile etching
`
`products on the sidewalls or the area intended to be etched; and (2) it “knocks lose”
`
`the atoms on the film’s surface, making the chemical reaction occur more easily
`
`for the free radicals. It is generally accepted and experimentally demonstrated that
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`a-Si:H TFTs dry etching is anisotropic, i.e., highly directional, in nature.
`
`(31) In contrast to wet chemical etching, dry etching provides significantly
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`better anisotropic (or non-isotropic) etching due to sidewall inhibitor deposition
`
`and ion bombardment. Dry etching can result in decreased selectivity because the
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`free radicals created by the plasma process arc highly reactive and will chemically
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`react with many films commonly used in a-Si:H TFT fabrication. Dry etching also
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`offers the important TFT manufacturing advantage of eliminating the handling,
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`
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`11
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`Exhibit 1014, page11
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`consumption, and disposal of the relatively large quantities of dangerous acids and
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`solvents used in wet etching.
`
`(32) Overetching can have several different meanings to people of ordinary
`
`skill in the art in the 1990 timeframe, depending upon the context. For example, a
`
`person of ordinary skill in the art might have understood the term to describe
`
`etching a given feature beyond the target etching depth. A person of ordinary skill
`
`might have also understood the term to apply to etching for a length of time that
`
`exceeds that which was believed necessary to achieve target dimensions.
`
`(33) The overetch time is the etching time added to the etching process to
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`intentionally overetch the film. In AMLCD manufacturing, the amount of
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`overetching needed is generally stated in terms of time or a percentage of etch
`
`time, and is determined by estimating the uncertainties in etch rates and in the non-
`
`uniformities of the film thicknesses and then calculating the worst case etch time
`
`needed. This extra time (varying between 5% and 10%) is part of the Standard
`
`Operating Procedures associated with the etching tools and processes. Some
`
`additional etching time is built into every a-Si:H TFT manufacturing process to
`
`ensure that the etch goes to completion everywhere.
`
`VII. The ‘311 Patent
`(34) I have been informed that the claims at issue are claims 9–11, 15, 17–
`
`19, 48, 51, and 52 (the “Asserted Claims”) of the ‘311 patent.
`
`
`
`12
`
`Exhibit 1014, page12
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`(35) The ‘311 patent describes a method of fabricating a TFT where
`
`crystallization of the channel formation region and activation of the ohmic contact
`
`region of the source and drain by laser irradiation occurs after the device structure
`
`is completed. ‘311 patent col. 1, ll. 52–56. This is accomplished by constructing
`
`the TFT such that a part of “the channel formation region [5] and parts of the
`
`source and drain on the side of channel formation region [11, 12] are exposed to
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`incident laser radiation.” ‘311 patent at col. 1, ll. 56–58; ‘311 patent at Fig. 1(a).
`
`
`(36) In order to obtain the claimed benefit of this particular TFT structure,
`
`the invention calls for a step-like structure wherein an upper portion of the source
`
`and drain region extends beyond a lower portion of the source and drain electrodes.
`
`See, e.g., ‘311 patent at col. 12, ll. 42–46. The ‘311 patent’s method of
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`constructing the TFT, as described in Example 1, is illustrated in Figures 3(A)–(H).
`
`‘311 patent at Fig. 3(A)–(H). The method is accomplished by systematically
`
`layering conductive layers, semiconductor layers, and insulating layers. ‘311
`
`
`
`13
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`Exhibit 1014, page13
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`patent at col. 5, ln. 55–col. 7, ln. 9. The fabrication method includes steps for
`
`applying a photoresist [8] to the top of the TFT structure and using said photoresist
`
`to create the desired geometry shown in Figure 1(a). ‘311 patent at col. 6, ln. 56–
`
`col. 7, ln.3.
`
`
`
`(37) As stated in the specification, the benefit of the claimed structure is
`
`that electrical characteristics can be monitored and improved during the irradiation
`
`process because construction of the amorphous silicon TFT is completed prior to
`
`commencing the irradiation process. ‘311 patent at col. 5, ll. 2–7.
`
`(38) The two asserted independent claims, claims 9 and 17, are directed to
`
`methods of manufacturing the above-described TFT structure. I have prepared a
`
`chart dividing the two independent claims into elements. Further, I have
`
`underlined the differences between the two claims in order to eliminate extraneous
`
`explanations of identical claim language.
`
`
`
`14
`
`Exhibit 1014, page14
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`

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`
`
`Claim 9.
`Preamble. A method of manufacturing
`a display device including a thin film
`transistor, the method comprising the
`steps of:
`a. forming a gate electrode over a glass
`substrate;
`b. forming a gate insulating film
`comprising silicon nitride on said gate
`electrode;
`c. forming a first semiconductor film
`over said gate electrode with said gate
`insulating film interposed therebetween;
`
`d. forming an N-type semiconductor
`film on said first semiconductor film;
`e. patterning said first and N-type
`semiconductor films using a first
`photomask;
`f. forming a conductive layer on at least
`the patterned N-type semiconductor
`film;
`g. etching a portion of said conductive
`layer to form source and drain
`electrodes using a resist formed by a
`second photomask;
`h. etching a portion of the patterned N-
`type semiconductor film to form source
`and drain regions by dry etching without
`removing said resist wherein a channel
`forming region is formed in said first
`semiconductor film between said source
`and drain regions; and
`
`Claim 17.
`Preamble. A method of manufacturing
`a display device including a thin film
`transistor, the method comprising the
`steps of:
`a. forming a gate electrode over a glass
`substrate;
`b. forming a gate insulating film
`comprising silicon nitride on said gate
`electrode;
`c. forming a first semiconductor film
`comprising amorphous silicon over said
`gate electrode with said gate insulating
`film interposed therebetween;
`d. forming an N-type semiconductor
`film on said first semiconductor film;
`e. patterning said first and N-type
`semiconductor films using a first
`photomask;
`f. forming a conductive layer on at least
`the patterned N-type semiconductor
`film;
`g. etching a portion of said conductive
`layer to form source and drain
`electrodes using a resist formed by a
`second photomask;
`h. etching a portion of the patterned N-
`type semiconductor film to form source
`and drain regions using said resist
`wherein a channel forming region is
`formed in said first semiconductor film
`between said source and drain regions;
`
`
`
`15
`
`Exhibit 1014, page15
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`

`
`i. forming a passivation film over said
`glass substrate to cover at least said
`source and drain electrodes, said
`channel forming region, a part of a
`surface of said source region not
`covered by said source electrode and a
`part of a surface of said drain region not
`covered by said drain electrode after
`removing said resist,
`
`
`j. wherein an upper portion of each of
`said source and drain regions extend
`beyond a lower portion of each of said
`source and drain electrodes so that a
`distance between the source and drain
`regions is shorter than a distance
`between the source and drain
`electrodes.
`
`
`i. forming a passivation film over at
`least said source and drain electrodes
`and said channel forming region after
`removing said resist; and
`
`j. forming a pixel electrode over said
`passivation film wherein said pixel
`electrode is electrically connected to
`said source electrode or said drain
`electrode,
`k. wherein an upper portion of each of
`said source and drain regions extend
`beyond a lower portion of each of said
`source and drain electrodes so that a
`distance between the source and drain
`regions is shorter than a distance
`between the source and drain
`electrodes.
`
`VIII. Claim Interpretation
`(39) In proceedings before the USPTO, I understand that the USPTO
`
`applies a policy of liberal claim construction when interpreting claims of an
`
`expired patent. I have been informed that the ‘311 patent has expired. In
`
`comparing the claims of the ‘311 patent to the known prior art, I have carefully
`
`considered the ‘311 patent and its file history based upon my experience and
`
`knowledge in the relevant field. I have not encountered any “coined” terms or
`
`terms that require consideration of a special or explicitly defined meaning.
`
`
`
`16
`
`Exhibit 1014, page16
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`

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`Instead, the claim terms of the ‘311 patent are used in their ordinary and customary
`
`sense as one skilled in the relevant field would understand them.
`
`(40) I am informed that the ‘311 patent is a division of U.S. Patent
`
`Application No. 10/925,984, filed on Aug. 26, 2004, which is a division of U.S.
`
`Patent Application No. 10/140,176, filed on May 8, 2002, which is a division of
`
`U.S. Patent Application No. 10/011,708, filed on Dec. 11, 2001, which is a
`
`division of U.S. Patent Application No. 09/291,279, filed on Apr. 14, 1999, which
`
`is a division of U.S. Patent Application No. 09/045,696, filed on Mar. 23, 1998,
`
`which is a division of U.S. Patent Application No. 08/455,067, filed on May 31,
`
`1995, which is a division of U.S. Patent Application No. 08/260,751, filed on Jun.
`
`15, 1994, which is a continuation of U.S. Patent Application No. 07/895,029, filed
`
`on Jun. 8, 1992. Additionally, the ‘311 patent claims priority to a foreign patent,
`
`Japanese Patent Publication No. JP 03-174541, filed on Jun. 19, 1991. I am further
`
`informed that this means that the ‘311 patent is considered to have been filed on
`
`Jun. 19, 1991 for purposes of determining whether a reference constitutes prior art.
`
`Thus, a reference will qualify as prior art if it disclosed or suggested the invention
`
`on Jun. 19, 1991 or earlier.
`
`(41) I have been informed that a patent claim can be found unpatentable as
`
`obvious where the differences between the subject matter sought to be patented
`
`and the prior art are such that the subject matter as a whole would have been
`
`
`
`17
`
`Exhibit 1014, page17
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`

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`obvious at the time the invention was made to a person having ordinary skill in the
`
`relevant field. I understand that an obviousness analysis involves a consideration
`
`of: (1) the scope and content of the prior art; (2) the differences between the
`
`claimed inventions and the prior art; (3) the level of ordinary skill in the pertinent
`
`art; and (4) secondary considerations of non-obviousness.
`
`IX. Scope and Content of Japanese Patent Publication No. JP H2-234125 to
`Taniguchi, et al. (“Taniguchi”) taken in view of U.S. Patent No.
`5,270,567 to Mori, et al. (“Mori”), U.S. Patent No. 5,054,887 to Kato, et
`al. (“Kato”), and Microchip Fabrication: A practical Guide to
`Semiconductor Processing (“Van Zant”)
`(42) I have been asked to consider the scope and content of Taniguchi in
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`view of Mori, Kato, and Van Zant, and to compare these combined teachings to the
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`Asserted Claims of the ‘311 patent.
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`(43) Claim elements 9.Preamble and 17.Preamble state “[a] method of
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`manufacturing a display device including a thin film transistor.” Taniguchi, in the
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`same field of endeavor as the ‘311 patent, is directed to “a liquid crystal display
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`device such as active matrix color liquid display devices comprising, for example,
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`thin-film transistors and picture element electrodes.” Taniguchi at p. 2.
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`(44) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim elements 9.Preamble and 17.Preamble.
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`(45)
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` Claim elements 9.a and 17.a state “forming a gate electrode over a
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`glass substrate.” Taniguchi discloses a first conductive layer etched to form a gate
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`18
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`Exhibit 1014, page18
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`

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`electrode [GT]. Taniguchi at p. 22. Further, Taniguchi discloses forming the gate
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`electrode [GT] on a glass substrate [SUB1]. Taniguchi at Fig. 22 (see below).
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`(46) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim elements 9.a and 17.a.
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`(47) Claim elements 9.b and 17.b state “forming a gate insulating film
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`comprising silicon nitride on said gate electrode.” Taniguchi discloses the use of
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`silicon nitride to form a gate insulating film [GI] on the gate electrode [GT].
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`Taniguchi at p. 5; Taniguchi at Fig. 22 (see below).
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`(48) I see no discernable difference between the stated subject matter of
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`19
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`Exhibit 1014, page19
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`

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`Taniguchi and claim elements 9.b and 17.b.
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`(49) Claim element 9.c states “forming a first semiconductor film over said
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`gate electrode with said gate insulating film interposed therebetween.” Taniguchi
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`discloses forming an i-type amorphous silicon layer [AS]. Taniguchi at p. 22.
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`Further, as seen in Figure 22, the i-type amorphous silicon layer [AS] (i.e. a first
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`semiconductor layer) is formed over the gate electrode [GT] with the gate
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`insulating film [GI] formed in between. Taniguchi at Fig. 22 (see below).
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`(50) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim element 9.c.
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`(51) Claim element 17.c states “forming a first semiconductor film
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`comprising amorphous silicon over said gate electrode with said gate insulating
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`film interposed therebetween.” As denoted by the underlining above, claim
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`element 17.c further limits, as compared to claim element 9.c, the first
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`semiconductor film to a film “comprising amorphous silicon.” Taniguchi discloses
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`forming an i-type amorphous silicon layer [AS]. Taniguchi at p. 6.
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`
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`20
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`Exhibit 1014, page20
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`(52) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim element 17.c.
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`(53) Claim elements 9.d and 17.d state “forming an N-type semiconductor
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`film on said first semiconductor film.” Taniguchi discloses forming an N+-type
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`silicon film [d0] on the first semiconductor film [AS]. Taniguchi at p. 22;
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`Taniguchi at Fig. 22 (see below).
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`(54) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim elements 9.d and 17.d.
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`(55) Claim elements 9.e and 17.e state “patterning said first and N-type
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`semiconductor films using a first photomask.” Taniguchi discloses, “selectively
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`etching the N+-type silicon layer and the i-type amorphous silicon layer using a
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`photo processing technique.” Taniguchi at p. 22. A person of ordinary skill in the
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`art would have known that the disclosed photo processing technique would require
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`the use of a first photomask.
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`(56) I see no discernable difference between the stated subject matter of
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`
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`21
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`Exhibit 1014, page21
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`Taniguchi and claim elements 9.e and 17.e.
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`(57) Claim elements 9.f and 17.f state “forming a conductive layer on at
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`least the patterned N-type semiconductor film.” Taniguchi discloses a first [d1]
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`and second [d2] conductive layer formed on the N+-type silicon layer. Taniguchi
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`at p.22; Taniguchi at Fig. 22 (see below).
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`(58) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim elements 9.f and 17.f.
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`(59) Claim elements 9.g and 17.g state “etching a portion of said
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`conductive layer to form source and drain electrodes using a resist formed by a
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`second photomask.” Taniguchi discloses “selectively etching the 2nd conductive
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`layer d2 using the photo process technique employing the mixture of hydrochloric
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`acid, phosphoric acid and acetic acid as the etching solution, the 2nd layer on the
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`source electrode SD3 and the 2nd layer on the drain electrode SD4 are formed.
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`Next, by selectively etching the 1st conductive layer d1 using a photo processing
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`technique after washing and drying with a rinser, the 1st layer on the source
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`22
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`Exhibit 1014, page22
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`electrode SD3 and the 1st layer on the drain electrode SD4 are formed.” Taniguchi
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`at p. 22; Taniguchi at Fig. 22 (see below).
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`(60) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim elements 9.g and 17.g.
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`(61) Claim element 9.h states “etching a portion of the patterned N-type
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`semiconductor film to form source and drain regions by dry etching without
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`removing said resist wherein a channel forming region is formed in said first
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`semiconductor film between said source and drain regions.” Taniguchi discloses
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`“filling CCl4 and SF6 into a dry etching device to selectively etch the N+-type
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`silicon layer, the N+-type semiconductor layer d0 is formed before removing the
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`resist.” Taniguchi at pp. 22, 23. Further, Taniguchi discloses that the i-type
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`semiconductor layer [AS] is used as the respective channel formation area for the
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`TFT. Taniguchi at pp. 22, 23; Taniguchi at Fig. 22 (see below).
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`23
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`Exhibit 1014, page23
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`(62) I see no discernable difference between the stated subject matter of
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`Taniguchi and claim element 9.h.
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`(63) Claim element 17.h states “etching a portion of the patterned N-type
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`semiconductor film to form source and drain regions using said resist wherein a
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`channel forming region is formed in said first semiconductor film between said
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`source and drain regions.” As denoted by the underlining above, claim element
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`17.h differs from claim element 9.h in two respects: 1) claim element 17.h does not
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`limit the patterning process to dry etching, and 2) claim element 17.h requires the
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`patterning p