UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.o. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICAnON NO.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMAnON NO.
`
`95/000,246
`
`03/22/2007
`
`6756258
`
`9526
`
`05/1412008
`
`7590
`31780
`ERIC ROBINSON
`PMB 955
`21010 SOUTHBANK ST.
`POTOMAC FALLS, VA 20165
`
`EXAMINER
`
`DIAMOND, ALAN D
`
`ART UNIT
`
`PAPER NUMBER
`
`3991
`
`MAIL DATE
`
`05/1412008
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`Exhibit 1011, page 1
`
`

`

`ACTION CLOSING PROSECUTION
`(37 CFR 1.949)
`
`Control No.
`
`95/000,246
`Examiner
`
`ALAN DIAMOND
`
`Patent Under Reexamination
`
`6756258
`Art Unit
`
`3991
`
`•• The MAILING DA TE of this communication appears on the cover sheet with the correspondence address. ••
`
`Responsive to the communication(s) filed by:
`Patent Owner on 17 October 2007
`Third Party(ies) on __
`
`Patent owner may once file a submission under 37 CFR 1.951 (a) within 1 month(s) from the mailing date of this
`Office action. Where a submission is filed, third party requester may file responsive comments under 37 CFR
`1.951 (b) within 30-days (not extendable- 35 U.S.C. § 314(b)(2)) from the date of service of the initial
`submission on the requester. Appeal cannot be taken from this action. Appeal can only be taken from a
`Right of Appeal Notice under 37 CFR 1.953.
`
`All correspondence relating to this inter partes reexamination proceeding should be directed to the Central
`Reexamination Unit at the mail, FAX, or hand-carry addresses given at the end of this Office action.
`
`PART I. THE FOLLOWING ATTACHMENT(S) ARE PART OF THIS ACTION:
`1. 0 Notice of References Cited by Examiner, PTO-892
`2. [gIlnformation Disclosure Citation, PTO/S8/08
`3.0 __
`
`PART II. SUMMARY OF ACTION:
`1a. [gI Claims 3-8,10-15 and 18-31 are subject to reexamination.
`1b. [gI Claims 1,2,9,16.17 and 32 are not subject to reexamination.
`2. 0 Claims
`have been canceled.
`3.
`[gI Claims 24-31 are confirmed. [Unamended patent claims]
`4. 0 Claims
`are patentable.
`[Amended or new claims]
`5.
`[gI Claims 3-8,10-15 and 18-23 are rejected.
`6. 0 Claims
`are objected to.
`0 are not acceptable.
`0 are acceptable
`7. 0 The drawings filed on
`8 0 The drawing correction request filed on
`is:
`0 approved. 0 disapproved.
`9 [gI Acknowledgment is made of the claim for priority under 35 U.S.C. 119 (a)-(d). The certified copy has:
`0 not been received.
`[gI been filed in Application/Control No 07/895,029
`
`o been received.
`
`10.00ther
`
`_
`
`U.S. Patent and Trademark Office
`PTOL-2065 (08/06)
`
`Paper No. 20080430
`
`Exhibit 1011, page 2
`
`

`

`Transmittal of Communication to
`Third Party Requester
`Inter Partes Reexamination
`
`Control No.
`
`95/000,246
`Examiner
`
`ALAN DIAMOND
`
`Patent Under Reexamination
`
`6756258
`Art Unit
`
`3991
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address. --
`
`Enclosed is acopy of the latest communication from the United States Patent and Trademark Office
`in the above-identified reexamination proceeding. 37 CFR 1.903.
`
`Prior to the filing of a Notice of Appeal, each time the patent owner responds to this communication,
`the third party requester of the inter partes reexamination may once file written comments within a
`period of 30 days from the date of service of the patent owner's response. This 3D-day time period is
`statutory (35 U.S.C. 314(b)(2)), and, as such, it cannot be extended. See also 37 CFR 1.947.
`
`If an ex parte reexamination has been merged with the inter partes reexamination, no responsive
`submission by any ex parte third party requester is permitted.
`
`All correspondence relating to this inter partes reexamination proceeding should be directed to the
`Central Reexamination Unit at the mail, FAX, or hand-carry addresses given at the end of the
`communication enclosed with this transmittal.
`
`U.S. Patent and Trademark Office
`PTOL-2070 (5/04)
`
`PaperNo. 20080430
`
`Exhibit 1011, page 3
`
`

`

`INTER PARTES REEXAMINATION
`COMMUNICATION
`
`Control No.
`
`95/000,246
`Examiner
`
`ALAN DIAMOND
`
`Patent Under Reexamination
`
`6756258
`Art Unit
`
`3991
`
`-- The MAILING DA TE of this communication appears on the cover she~t with the correspondence address.--
`
`BELOW/ATIACHED YOU WILL FIND A COMMUNICATION FROM THE UNITED STATES PATENT
`AND TRADEMARK OFFICE OFFICIAL(S) IN CHARGE OF THE PRESENT REEXAMINATION
`PROCEEDING.
`
`All correspondence relating to this inter partes reexaminCition proceeding should be directed to the
`Central Reexamination Unit at the mail, FAX, or hand-carry addresses given at the end of this
`communication.
`
`U.S. Palenl and Trademark Office
`PTOL-2072 (5/04)
`
`PaperNo. 20080430
`
`Exhibit 1011, page 4
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 2
`
`Status of Proceedings
`
`1.
`
`A Request pursuant to 37 CFR 1.913 for inter partes reexamination of claims 1-
`
`32 of U.S. Patent 6,756,258 (hereinafter "the '258 patent") was filed March 22, 2007 by
`
`Third Party Requester. An Order granting inter partes reexamination of claims 1-32 of
`
`the '258 patent was mailed June 5,2007. A Statutory Disclaimer filed April 9,2007 was
`
`approved for the '258 patent, and n'otification of such approval was published on July
`
`17,2007 in the Official Gazette. Said Statutory Disclaimer disclaims claims 1,2,9, 16,
`
`17 and 32 of the '258 patent. Since claims 1, 2, 9, 16, 17 and 32 were statutorily
`
`disclaimed, they are not subject to reexamination. A non-final Office action rejecting
`
`claims 3-8, 10-15 and 18-31 was mailed August 13, 2007. A Patent Owner's response
`
`to the non-final Office action was filed October 17, 2007. Third Party Comments have
`
`n9t been received.
`
`Information Disclosure Statement (IDS)
`
`2.
`
`. All of the references cited on the PTO-1449 form filed August 10, 2007 have
`
`been considered by the Examiner but have been crossed out because they are not
`
`appropriate for printing on the face of the reexamination certificate. Likewise, the
`
`references that have been crossed out on the PTO-1449 form filed November 21,2007
`
`have been considered but are not appropriate for printing on the face of the
`
`reexamination certificate.
`
`In the IDS filed January 25,2008, U.S. Patent 5,270,567 has
`
`been crossed out to avoid duplication since this patent is already of record. See the
`
`IDS filed March 22,2007.
`
`Exhibit 1011, page 5
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 3
`
`Scope of Claims
`
`3.
`
`In reexamination"patent claims are construed broadly.
`
`In re Yamamoto, 740
`
`F.2d 1569,1571,222 USPQ 934, 936 (Fed. Cir. 1984) (claims given "their broadest
`
`reasonable interpretation consistent with the specification"). Claims 3-8, 10-15 and 18-
`
`31 of the '258 patent are directed to a method of manufacturing a semiconductor
`
`device. Claims 3-8 are representative:
`
`3. A method of manufacturing a semiconductor device comprising the steps of:
`forming a gate electrode on an insulating surface;
`forming a gate insulating film comprising silicon nitride on said gate
`electrode;
`,
`forming a first semiconductor film comprising amorphous silicon over said
`gate electrode with said gate insulating film interposed therebetween;
`forming a second semiconductor film on said first semiconductor film, said
`second semiconductor film doped with an N-type dopant;
`patterning said first and second semiconductor films;
`forming a conductive layer on the patterned second semiconductor film;
`patterning the conductive layer to form source and drain electrodes by
`using a mask wherein a portion of the patterned second semiconductor film is
`exposed between said source and drain electrodes;
`etching the exposed portion of the second semiconductor film to form
`source and drain regions wherein a channel forming region is formed in said first
`semiconductor film between said source and drain regions,
`wherein said conductive layer is overetched to form a stepped portion
`from an upper surface at the source and drain electrodes to a surface at the first
`semiconductor film.
`
`4. A method of manufacturing a semiconductor device comprising the steps of:
`forming a gate electrode on an insulating surface;
`forming a gate insulating film comprising silicon nitride on said gate
`electrode;
`forming a first semiconductor film comprising amorphous silicon over said
`gate electrode with said gate insulating film interposed therebetween;
`forming a second semiconductor film on said first semiconductor film, said
`second semiconductor film doped with an N-type dopant;
`patterning said first and second semiconductor films;
`forming a conductive layer on the patterned second semiconductor film;
`
`Exhibit 1011, page 6
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 4
`
`patterning the conductive layer to form source and drain electrodes by
`using a mask wherein a portion of the patterned second semiconductor film is
`exposed between said source and drain electrodes;
`etching the exposed portion of the second semiconductor film to form
`source and drain regions wherein a channel forming region is formed in said first
`semiconductor film between said source and drain regions; and
`over etching the conductive layer by wet etching so that an upper surface
`of the source and drain regions is partially exposed from said source and drain
`electrodes.
`
`5. A method of manufacturing a semiconductor device comprising the steps of:
`forming a gate electrode on an insulating surface;
`forming a gate insulating film comprising silicon nitride on said gate
`electrode;
`forming a first semiconductor film comprising amorphous silicon over said
`gate electrode with said gate insulating film interposed therebetween;
`forming a second semiconductor film on said first semiconductor film, said
`second semiconductor film doped with an N-type dopant;
`patterning said first and second semiconductor films;
`forming a conductive layer on the patterned second semiconductor film;
`patterning the conductive layer to form source and drain electrodes by
`using a mask wherein a portion of the patterned second semiconductor film is
`exposed between said source and drain electrodes;
`etching the exposed portion of the second semiconductor film to form
`source and drain regions wherein a channel forming region is formed in said first
`semiconductor film between said source and drain regions; and
`.
`overetching the conductive layer by wet etching so that a distance
`. between the source and drain regions at an upper surface thereof is shorter than
`a distance between the source and drain electrodes at a lower surface thereof.
`
`6. A method of manufacturing a semiconductor device comprising the steps of:
`forming a gate electrode on an insulating surface;
`forming a gate insulating film comprising silicon nitride on said gate
`electrode;
`forming a first semiconductor film comprising amorphous silicon over said
`gate electrode with said gate insulating film interposed therebetween;
`forming a second semiconductor film on said first semiconductor film, said
`second semiconductor film doped with an N-type dopant;
`patterning said first and second semiconductor films;
`forming a conductive layer on the patterned second semiconductor film;
`patterning the conductive layer to form source and drain electrodes by
`using a mask wherein a portion of the patterned second semiconductor film is
`exposed between said source and drain electrodes;
`
`Exhibit 1011, page 7
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 5
`
`etching the exposed portion of the second semiconductor film to form
`source and drain regions wherein a channel forming region is formed in said first
`semiconductor film between said source and drain regions,
`wherein said conductive layer is over etched by wet etching to form a
`stepped portion from an upper surface at the source and drain electrodes to a
`surface at the first semiconductor film.
`
`7. A method of manufacturing a semiconductor device comprising the steps of:
`forming a gate electrode on an insulating surface;
`forming a gate insulating film comprising silicon nitride on said gate
`electrode;
`forming a first semiconductor film comprising amorphous silicon over said
`gate electrode with said gate insulating film interposed therebetween;
`forming a second semiconductor film on said first semiconductor film, said
`second semiconductor film doped with an N-type dopant;
`patterning said first and second semiconductor films;
`forming a conductive layer on the patterned second semiconductor film;
`patterning the conductive layer to form source and drain electrodes by
`using a mask wherein a portion of the patterned second semiconductor film is
`exposed between said source and drain electrodes;
`dry etching the exposed portion of the second semiconductor film to form
`source and drain regions wherein a channel forming region is formed in said first
`semiconductor film between said source and drain regions; and
`overetching the conductive layer by wet etching after the dry etching.
`
`8. A method of manufacturing a semiconductor device comprising the steps of:
`forming a gate electrode on an insulating surface;
`forming a gate insulating film comprising silicon nitride on said gate
`electrode;
`forming a first semiconductor film comprising amorphous silicon over said
`gate electrode with said gate insulating film interposed therebetween;
`forming a second semiconductor film on said first semiconductor film, said
`second semiconductor film doped with an N-type dopant;
`patterning said first and second semiconductor films;
`forming a conductiye layer on the patterned second semiconductor film;
`patterning the conductive layer to form source and drain electrodes by using a
`mask wherein a portion of the patterned second semiconductor film is exposed
`between said source and drain electrodes;
`dry etching the exposed portion of the second semiconductor film to form
`source and drain regions wherein a channel forming region is formed in said first
`semiconductor film between said source and drain regions; and
`wet etching the conductive layer after the dry etching so that a distance
`between the source and drain regions is shorter than a distance between the
`source and drain electrodes.
`
`Exhibit 1011, page 8
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 6
`
`The terms "overetched", "over etching", "overetching" and "over etched" which
`
`appear in the instant claims have not been given any special meaning in the
`
`specification of the '258 patent. The Examiner notes SEL's, i.e. Patent Owner's,
`
`opening claim construction brief, at 10:9-21 (Exhibit R of the request for reexamination)
`
`where patent owner argues that the terms "overetching" or overetched" include (1) the
`
`continuation of an etching step or process or (2) an additional etching step or process,
`
`with the result in both cases being "to etch for an additional time to remove some
`
`additional materiaL" Furthermore, the Examiner agrees with the third party requester
`
`at pages 22-23 of the request that "overetching" includes an anisotropic etch and an
`
`isotropic etch, provided that, whichever etch i_~ chosen, it be performed for an
`
`additional time; and that "overetching" not only encompasses the case where the
`
`purpose of the overetch is to more completely remove the exposed region, but also
`
`encompasses the case where the purpose of the overetch is to achieve undercutting,
`
`and thereby intentionally remove one or more portions of the unexposed region.
`
`Further, the term "stepped portion" in claims 3 and 6 has not been given any
`
`special meaning in the specification of the '258 patent.
`
`Indeed, this term is never
`
`mentioned in the specification of the '258 patent. Claims 3 and 6 require that the
`
`conductive layer is overetched to form a stepped portion "from an upper surface at the
`
`source and drain electrodes to a surface at the first semiconductor film." Presumably,
`
`an example of the "stepped portion" is in Figures 3(G) and 3(H), where there are steps
`
`from an upper surface of the source and drain electrodes 9, 10, to the n-doped layer
`
`Exhibit 1011, page 9
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 7
`
`11, 12, and then to the first semiconductor film 5 (see Figures 3(C) and 3(F) for
`
`numbering). While these are plural steps, the term "stepped portion" does not require
`
`plural steps.
`
`In other words, it is the Examiner's position that a "stepped portion"
`
`merely requires what claims 3 and 6 state, a step from the upper surface at the source
`
`and drain electrodes to a surface at the first semiconductor surface. The rise of the
`
`step is not required to be vertical, but can be tapered or sloped as shown by third party
`
`requester at page 21 of the Request.
`
`At page 43 of the Rebuttal Expert Witness Report of Michael Thomas (Exhibit 0
`
`of the Request), Patent Owner's expert stated the "stepped portion" means "that a
`
`portion of the n+ layer is exposed between the electrode and the channel region." The
`
`Examiner disagrees. Nowhere does the specification of the '258 patent require that a
`
`stepped portion must have an exposed n+ layer (second semiconductor layer) between
`
`the electrode and channel region. Once again, all that is required is a step "from an
`
`upper surface at the source and drain electrodes to a surface at the first semiconductor
`
`surface".
`
`At page 2 of the Remarks filed 10/17/07, Patent Owner argues:
`
`The Official Action states that "[t]he Examiner agrees ... thafthe term
`'stepped' is met not only by vertical sidewalls for the source drain regions as
`seen in Figure 3(G) of the '258 patent, but also by tapered sidewalls of the
`source drain regions" (page 7, Paper No. 20070524). In this regard, it should be
`noted that the term "stepped" is not to be interpreted based on the sidewalls of
`the source and drain regions, since such sidewalls do not control whether the
`structure results in a "stepped" configuration. Rather, it is believed that a stepped
`portion, as claimed, corresponds to a layer having at least two exposed surfaces,
`such as a side surface and an upper surface. Thus, in accordance with a
`reasonable interpretation of the term "stepped," it may include a device having
`tapered sidewalls of the source and drain region or a device having vertical
`sidewalls. The mere presence of tapered sidewalls alone is insufficient to
`
`Exhibit 1011, page 10
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 8
`
`disclose a "stepped" portion as claimed. To the extent that the Examiner or the
`third party requester takes any contrary position, such position is traversed.
`
`These arguments are not persuasive. The rise of the step need not be vertical.
`
`It can be tapered or sloped. Once again, in order to have a "stepped portion" as
`
`claimed, all that is required is a step from the upper surface at the source and drain
`
`electrodes to a surface at the first semiconductor surface.
`
`CLAIM REJECTIONS
`
`4.
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
`
`form the basis for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless -
`
`(a) the invention was known or used by others in this country, or patented or described in a printed
`publication in this or a foreign country, before the invention thereof by the applicant for a patent.
`
`(b) the invention was patented or described in a printed publication in this or a foreign country or in public
`use or on sale in this country, more than one year prior to the date of application for patent in the United
`States.
`
`(e) the invention was described in (1) C!n application for patent, published under section 122(b), by
`another filed in the United States before the invention by the applicant for patent or (2) a patent
`granted on an application for patent by another filed in the United States before the invention by the
`applicant for patent, except that an international application filed under the treaty defined in section
`351 (a) shall have the effects for purposes of this subsection of an application filed in the United States
`only if the international application designated the United States and was published under Article 21 (2)
`of such treaty in the English language.
`
`5.
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obv.ious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`Requester's Proposed Rejections
`
`Exhibit 1011, page 11
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 9
`
`6.
`
`Claims 3, 10 and 18 are rejected under 35 U.S.C. 102(e) as being anticipated
`
`by Mori et al (U.S. Patent 5,270,567, hereinafter "the '567 patent"), as evidenced
`
`by Rebuttal Expert Witness Report of Michael Thomas, PhD, patent owner's
`
`expert witness, Appendix B thereto, Semiconductor Energy Laboratory Co., Ltd.
`
`v. Chi Mei Optoelectronics Corp. et aI., Case C 044675 MHP (N.D. Cal.), Nov. 14,
`
`2006 (found in Exhibit 0 of the instant reexamination, hereinafter referred to as
`
`"Thomas Testimony") and Peter Van Zant, Microchip Fabrication, A Practical
`
`Guide to Semiconductor Processing, pages 221-257, 2nd edition, (1990), McGraw
`
`Hill (hereinafter "Van Zant").
`
`It is clear that the rejection proposed by the third party requester at page 46, line
`
`1, through page 49, line 11, of the request relies upon the Thomas Testimony.
`
`Accordingly, the Thomas Testimony has been included in the rejection statement in the
`
`immediately preceding paragraph.
`
`This rejection of claims 3, 10 and 18 was proposed by the third party requester
`
`as set forth in the request at page 46, line 1, through page 49, line 11, which is hereby
`
`incorporated by reference. This rejection was adopted in the first Office action, and the
`
`Examiner's position remains unchanged.
`
`In addition to what is discussed at said page 46, line 1 through page 49, line 11,
`
`claim 3 recites the following etching step: "etching the exposed portion of the second
`
`semiconductor film to form source and drain regions wherein a channel forming region
`
`is formed in said first semiconductor film between said source and drain regions". At
`
`Exhibit 1011, page 12
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 10
`
`page 7 of the Thomas Testimony, patent oWl'ler's expert makes the following statement
`
`with respect to the '567 patent and said etching step:
`
`I agree with Dr. Kanicki that: As indicated by the text and figures cited
`below, this reference [i.e., the '567 patent] discloses source I drain structures that
`can be achieved by etching the exposed portion of the second semiconductor
`film to form source and drain regions wherein a channel forming region is formed
`in said first semiconductor film between said source and drain regions.
`
`Further, third party requester makes the following statement on page 41 of the request
`
`with respect to said etching step:
`
`Additionally, ... this reference [i.e., the '567 patent] discloses forming a
`channel portion in the first semiconductor film 14 ... which necessarily requires
`etching the exposed portion of the second semiconductor ... to form source and
`drain regions wherein the .channel forming region is formed in the first
`semiconductor film between the source and drain regions.
`
`The instant etching step is never specifically mentioned in the '567 patent, but based on
`
`the statement of patent owner's expert and said statement made by third party
`
`requester, this etching step is inherent in the '567 patent.
`
`Claim 3 further requires "wherein said conductive layer is overetched to form a
`
`stepped portion from an upper surface at the source and drain electrodes to a surface at
`
`the first semiconductor film." At page 47, and wi~h respect to this requirement, the third
`
`party requester notes that in the '567 patent, "there is no other technique [other than
`
`etching] that could be applied to remove these portions [i.e., the portions of the
`
`conductive layer]".
`
`In particular, as seen in Prior Art Figure 1 of the '567 patent, source
`
`and drain electrodes 6, 7 overlap the gate electrode 2. The '567 patent teaches
`
`eliminating this overlap in order to minimize stray capacitance to obtain the structure
`
`seen in the '567 patent's Figure 2.
`
`In order to obtain the source and drain electrodes
`
`Exhibit 1011, page 13
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 11
`
`16, 17 in said Figure 2, as compared to the electrodes 6, 7 in Figure 1, said etching
`
`would be used. Thus, etching of the conductive layer is inherent in the '567 patent.
`
`Van Zant is relied upon for teaching that "[i]n any etch process there is always some
`
`degree of overetch planned into the process" (see page 48 of the request; and page
`
`222 of Van Zant). Thus, the '567 patent, as evidenced by the teaching of Van Zant,
`
`inherently teaches the instant overetching. Furthermore, as noted on page 46 of the
`
`request, Figure 2 of the '567 patent shows the claimed stepped portion.
`
`Arguments:
`
`Patent Owner argues that Mori '567 (i.e., the '567 patent) does not disclose
`
`"'overetching the conductive layer to form a step portion' as recited in claim 3", and that
`
`Mori (i.e., the '567 patent) is silent as to the process used to form its TFT device"
`
`(Remarks of 10/17/07, pp. 4-5).
`
`This argument is not persuasive. As noted on page 46 of the request, the
`
`Thomas Testimony admits that the '567 patent discloses the preamble and "each of
`
`elements a-h of claim 3". These elements a-h correspond to each of the steps in claim
`
`3, up to and including the step of "etching the exposed portion of the second
`
`semiconductor film ... ". The last element of claim 3 is the recitation "wherein said
`
`conductive layer is overetched to form a stepped portion from an upper surface at the
`
`source and drain electrodes to a surface at the first semiconductor film." As noted on
`
`page 47 of the request, this overetching requirement is inherently disclosed by the '567
`
`patent.
`
`In particular, as seen in Prior Art Figure 1 of the '567 patent, source and drain
`
`electrodes 6, 7 overlap the gate electrode 2. The '567 patent teaches eliminating this
`
`Exhibit 1011, page 14
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 12
`
`vertical overlap in order to minimize stray capacitance to obtain the structure seen in the
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`'567 patent's Figure 2.
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`In order to obtain the source and drain electrodes 16, 17 in said
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`Figure 2, as compared to the electrodes 6, 7 in Figure 1, etching would be used
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`because, as noted on page 47 of the request, there is no other technique that could be
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`used. With respect to overetching, Van Zant t~aches that "[i]n any etch process there is
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`always some degree of overetch planned into the process" (see page 222).
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`In other
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`words, the etching that is used to form said electrodes 16, 17 would inherently have
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`some degree of overetching.
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`Having followed said steps a-h which the Thomas Testimony admits are
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`disclosed in the '567 patent, i.e. having followed the steps of:
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`(a) forming a gate electrode on an insulating surface;
`(b) forming a gate insulating film comprising silicon nitride on said gate
`electrode;
`(c) forming a first semiconductor film comprising amorphous silicon over
`said gate electrode with said gate insulating film interposed therebetween;
`(d) forming a second semiconductor film on said first semiconductor film,
`said second semiconductor film doped with an N-type dopant;
`(e) patterning said first and second semiconductor films;
`(f) forming a conductive layer on the patterned second semiconductor film;
`(g) patterning the conductive layer to form source and drain electrodes by
`using a mask wherein a portion of the patterned second semiconductor film is
`exposed between said source and drain electrodes; and
`(h) etching the exposed portion of the second semiconductor film to form
`source and drain regions wherein a channel forming region is formed in said first
`semiconductor film between said source and drain regions
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`a skilled artisan arrives at Figure 3(F) in the '258 patent under reexam. Figure 3(F) is
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`very similar to Prior Art Figure 1 in the '567 patent, with Figure 3(F) still having resist 8
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`on top. Said Prior Art Figure 1 no longer has the resist. The question then becomes,
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`having obtained the prior art structure in Figure 1 of the '567 patent, how can Figure 2 of
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`Exhibit 1011, page 15
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`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 13
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`the '567 patent be obtained. Third party states that the only way to do this is by etching, .
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`and that.etching inherently entails overetching. The Examiner agrees with Third Party.
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`Patent Owner cites JP 63-224258 (supplied in the IDS filed 11/21/07) and argues
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`that there are several possible methods to form a step portion of a TFT device such as
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`that disclosed in the '567 patent, and overetching the conductive layer to form the step
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`portion is only one of the possible processes that could be employed (Remarks of
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`10/17/07, p. 5).
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`In particular, Patent Owner argues that "there is a method in which a
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`conductive layer and an n+ semiconductor layer are formed using different masks to
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`form a step portion as disclosed in JP 63-224258" (Remarks of 10/17/07, p. 5).
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`This argument is not persuasive. Even JP 63-224258 teaches etching, and thus,
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`inherently overetching, to arrive at its source and drain electrodes. JP 63-224258
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`specifically teaches that "[t]he source and drain electrodes 7, 8 are patterned using
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`photolithographic etching so as to have a gap between them, and to have no overlap
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`with the gate electrode 2" (see the beginning of the "Embodiments of the Invention"
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`section at the third page of the attached English translation). Note in JP 63-224258's
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`Figure 4(a) that the patterned electrodes 7, 8 are similar to the patterned electrodes 16,
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`17 in Figure 2 of the Mori '567 patent. Since etching is used by JP63-224258,
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`overetching inherently occurs, in view of the teaching in Van Zant that in any etch
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`process there is always some degree of overetch planned into the process (see page
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`222).
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`Patent Owner argues that "[t]here is no support in the prior art or statements
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`which establish the level of ordinary skill in the art at the time of the present invention
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`Exhibit 1011, page 16
`
`

`

`Application/Control Number: 95/000,246
`Art Unit: 3991
`
`Page 14
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`that support the arguments that 'there is no other technique that could be applied to
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`remove these portions'''; and that U[m]ere attorney argument alone, unsupported by
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`factual evidence, cannot form the basis of a prima facie case of unpatentability"
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`(Remarks of 10/17/07, pp. 5-6).
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`These arguments are not persuasive. As noted above, the JP 63-224258
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`reference cited by Patent Owner to rebut Third Party's statement actually uses etching,
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`and thus inherently overetching, to pattern its conductive layer and form electrodes 7, 8.
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`At pages6-7 of the Remarks of 10/17/07, Patent Owner argues that the Thomas
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`Testimony is taken out of context, and cites the following additional testimony of
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`Thomas:
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`In my opinion, the Mori references do not disclose every element of any
`claim of the '258 patent. As an initial matter, these references are altogether
`silent as to the processing steps used to form the disclosed structure. Therefore,·
`there is no disclosure of overetching the conductive layer to obtain the structures
`shown in FIG. 2 or FIG. 12. Because the Mori references do not teach
`overetching the conductive layers, at least one element of each claim is not
`disclosed by these references. Consequently, the claims of the '258 patent are
`not anticipated.
`
`In my opinion, the structure disclosed in the Mori references was not
`formed by overetching the conductive layer, but instead separate masking steps
`were used to form the source and drain electrodes (16 and 17 in FIG. 2, 36 and
`37 in FIG. 12) and the n-type source and drain regions (15 in FIG. 2, 35 in FIG.
`12) because the distance 13, which corresponds to the distance between the
`ends of the electrodes and the ends of the n-type amorphous silicon regions, is 9
`IJm. (See Mori '567 reference, col. 3, lines 35-37.) In my opinion, it is difficult to
`see how such a structure could be generated by using one mask to overetch the
`conductive layer because of the