United States Patent [19]
`Kato et al.
`
`Patent Number:
`[11]
`[45] Date of Patent:
`
`5,054,887
`Oct. 8, 1991
`
`[54] ACTIVE MATRIX TYPE LIQUID CRYSTAL
`DISPLAY
`
`[75]
`
`Inventors: Hiroaki Kato, Nara; Toshihiko
`Hirobe, Sakai; Yoshitaka Hibino,
`Nara, all of Japan
`
`[73] Assignee:
`
`Sharp Kabushiki Kaisha, Osaka,
`Japan
`
`[21] Appl. No.: 391,244
`
`[22] Filed:
`
`Aug. 9,1989
`
`[30]
`
`Foreign Application Priority Data
`Aug. 10, 1988 [JP]
`Japan
`
`63-200782
`
`Int. Cl.5
`[51]
`[52] U.S. Cl
`
`[58] Field of Search
`
`G02F 1/13
`359/59; 357/23.7;
`357/54; 359/79; 359/87
`350/334, 336, 339 R;
`357/23.7, 54
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,671,820 6/1972 Haering et al.
`4,571,816
`2/1986 Dingwall
`4,778,560 10/1988 Takeda et al.
`4,843,438
`6/1989 Koden et al.
`4,905,066
`2/1990 Dohjo et al.
`
`357/23.7
`357/23.7 X
`357/23.7 X
`357/23.7
`357123.7 X
`
`FOREIGN PATENT DOCUMENTS
`
`0136509
`0288011
`6343553
`
`8/1984 European Pat. Off..
`4/1988 European Pat. Off..
`8/1989 Japan.
`
`OTHER PUBLICATIONS
`1982 International Display Research Conference,
`Cherry Hill, N.J.; A. I. Lakatos, "Promise and Chal(cid:173)
`lenge of Thin-Film Silicon Approaches to Active Ma(cid:173)
`trices"; p. 148, Col. 2, lines 26-38.
`Primary Examiner-Andrew J. James
`Assistant Examiner-Sara W. Crane
`ABSTRACT
`[57]
`An active matrix type liquid crystal display device in(cid:173)
`cludes a substrate on which a matrix picture element
`electrodes reside, TFTs which are disposed in the vicin(cid:173)
`ity of each picture element electrodes, and capacitor
`electrodes are provided, each of which is opposed to
`one portion of each of the picture element electrodes. A
`dielectric lamination structure consisting of three insu(cid:173)
`lating layers is formed between the picture element
`electrode and the capacitor electrode. The dielectric
`lamination structure includes an anodic oxidation film, a
`gate insulating layer and a protective insulating layer.
`The protective insulating layer further extending over
`the associated TFT.
`
`13 Claims, 2 Drawing Sheets
`
`Exhibit 1005, page 1
`
`

`

`u.s. Patent
`
`Oct. 8, 1991
`
`Sheet 1 of 2
`
`5,054,887
`
`24
`
`23
`
`I
`-l
`
`I
`.J
`
`-- - -----1
`I
`I
`L
`
`I
`
`+_.
`-i ~--l
`
`' - - -_ - - . I
`
`IIII
`
`L
`
`23
`
`26
`
`340
`
`35
`
`27·
`
`FIG. 1
`
`Exhibit 1005, page 2
`
`

`

`u.s. Patent
`
`Oct. 8, 1991
`
`Sheet 2 of 2
`
`5,054,887
`
`FIG.
`PRiOR
`
`3
`ART
`
`3
`
`---------1
`I
`I
`L
`
`I
`
`-
`TIl
`
`, -
`I
`I
`J
`
`'--
`
`-
`
`_
`
`---;-,
`
`:IIII1
`
`FIG. 4
`PRIOR ART
`
`3
`
`"
`
`Exhibit 1005, page 3
`
`

`

`1
`
`ACTIVE MATRIX TYPE LIQUID CRYSTAL
`DISPLAY
`
`5,054,887
`
`2
`In a prior art active matrix type liquid crystal display
`device having such a configuration, the picture element
`electrode 4 is electrically insulated from the capacitor
`electrode 6 by the dielectric layer consisting of the
`5 anodic oxidation film 9 and the gate insulating layer 10.
`However, pinholes often form in the dielectric layer
`due to the presence of a foreign body in the dielectric
`layer. In such a case, the picture element electrode 4
`disposed on the dielectric layer falls into electrical con(cid:173)
`tinuity with the capacitor electrode 6 formed under the
`dielectric layer. As a result, when the TFT 5 connected
`to the picture element electrode 4 is ON, current leaks
`from the picture element electrode 4 to the capacitor
`electrode 6 to cause a display defect. In a prior art ac(cid:173)
`tive matrix type liquid crystal display device, therefore,
`the existence of a pinhole in the two-layered structure
`between the picture element electrode 4 and the addi(cid:173)
`tional capacitor electrode 6 causes an inferior produc(cid:173)
`tion yield.
`
`10
`
`BACKGROUND OF THE INVENTION
`1.. Field of the Invention
`This invention relates to an active matrix type liquid
`crystal display device in which thin film transistors are
`used as non-linear switching elements, and more partic-
`ularly to an active matrix type liquid crystal display
`device in which additional capacitors are formed.
`2. Description of the Prior Art
`In an active matrix type liquid crystal display device,
`thin film transistors (TFTs) are used as switching ele- 15
`ments for driving picture elements. It is often necessary
`to use an additional capacitor for each picture element
`in order to improve the display quality.
`FIG. 3 shows a substrate of a prior art active matrix
`type liquid crystal'display device. TFTs and additional 20
`capacitors are formed on the substrate. A plurality of
`parallel gate bus lines 2 are formed in horizontally, and
`a plurality of source bus lines 3 are formed vertically on
`an insulating substrate 7 (FIG. 4). In the vicinity of each
`. intersection of the gate bus lines 2 and source bus lines 25
`3, a TFT 5 is formed. Each TFT 5 drives a picture
`element electrode 4 which is disposed in each region
`surrounded by two adjacent gate bus lines 2 and source
`bus lines 3. Under the picture element electrode 4, a
`capacitor electrode 6 is formed. Between the substrate 30
`assembly of FIG. 4 and an opposing substrate assembly
`(not shown), a liquid crystal material is sealed to con(cid:173)
`struct a display device. Each picture element electrode
`4 constitutes a picture element.
`The structure of the substrate assembly will be de- 35
`scribed in more detail with reference to FIG. 4 which is
`a sectional view taken along line IV-IV of FIG. 3. The
`gate electrode 8 of the TFT 5 and the capacitor elec(cid:173)
`trode 6 are formed on the surface of the insulating sub(cid:173)
`strate 7. The gate electrode 8 is one part of the gate bus 40
`line 2. The gate electrode 8 and capacitor electrode 6
`can be formed simultaneously, and are made of the same
`material. An anodic oxidation film 9 is formed on each
`of the gate electrode 8 and capacitor electrode 6. A gate
`insulating layer 10 is formed on the anodic oxidation 45
`films 9 and the remaining surface of the insulating sub(cid:173)
`strate 7.
`The TFT 5 further comprises an i-amorphous silicon
`(a-Si) film 11. an insulating film 12. n--a-Si films 13. a
`source electrode 14a. and a drain electrode 14b which 50
`are laminated on the gate insulating layer 10. The
`source electrode 140 and drain electrode 14b are made
`of the same material as that of the source bus lines 3. and
`formed simultaneously with the source bus lines 3. The
`picture element electrode 4 is formed on the gate insu- 55
`Iating layer 10. and electrically connected to the drain
`electrode 14b.
`In the above-mentioned structure. a dielectric layer
`consisting of the anodic oxidation film 9 and the gate
`insulating layer 10 is formed between the picture ele- 60
`ment electrode 4 and the additional capacitor electrode
`6. so that the picture element electrode 4 and the capaci(cid:173)
`tor electrode 6 constitute.an additional capacitor which
`is connected in parallel to the capacitor caused by the
`liquid crystal. This additional capacitor store charges 65
`when the TFT 5 is On to drive the picture element
`electrode 4. and substantially retains the voltage applied
`to the electrode 4 until the next frame scanning period.
`
`SUMMARY OF THE INVENTION
`The active matrix type liquid crystal display of this
`invention, which overcomes the above-discussed and
`numerous other disadvantages and deficiencies of the
`prior art, comprises a substrate on which a m'atrix of
`picture element electrodes reside, switching elements
`TFT which are disposed in the vicinity of each of said
`picture element electrodes, capacitor electrodes each of
`which is opposed to at least one portion of each of said
`picture element electrodes, and a dielectric lamination
`structure consisting of three insulating layers is formed
`between said picture element electrode and said capaci(cid:173)
`tor electrode.
`In a preferred embodiment, the switching element is
`a thin film transistor, the gate electrode of said thin film
`transistor and said capacitor electrode are disposed on
`an insulating substrate, and a gate insulating layer is
`formed on both said gate electrode and said capacitor
`electrode, said gate insulating layer being one of said
`three laminated insulating layers.
`In a preferred embodiment, the protective insulating
`layer is formed on both said thin film transistor and said
`gate insulating layer, said protective insulating being
`another one of said three laminated insulating layers.
`In a preferred embodiment, the anodic oxidation film
`is formed on said capacitor electrode, said anodic oxida(cid:173)
`tion film being the further one of said three laminated
`insulating layers.
`In a preferred embodiment, the picture element elec(cid:173)
`trode is disposed on said protective insulating layer.
`In a preferred embodiment. the picture element elec(cid:173)
`trode is electrically connected to the drain electrode of
`said TFT. through a contact hole which is formed in
`said protective insulating layer.
`
`OBJECTS OF THE INVENTION
`Thus. it is an object of the present invention to pro(cid:173)
`vide an active matrix type liquid crystal display device
`in which there is no leakage between a picture element
`electrode and a capacitor electrode;
`It is another object of the present invention to pro(cid:173)
`vide an active matrix type liquid crystal display device
`which can effectively prevent the occurrence of a dis(cid:173)
`play defect; and
`It is a further object of the present invention to pro(cid:173)
`vide an active matrix type liquid crystal display device
`which can be manufactured in high yield.
`
`Exhibit 1005, page 4
`
`

`

`3
`BRIEF DESCRIPTION OF THE DRAWINGS
`This invention may be better understood and its nu(cid:173)
`merous objects and advantages will become apparent to
`those skilled in the art by reference to the accompany(cid:173)
`ing drawings as follows:
`FIG. 1 is a partial sectional view ofa substrate used in
`an embodiment of the invention.
`FIG. 2 is a plan view showing one portion of the
`substrate used in the embodiment.
`FIG. 3 is a plan view showing one portion of a sub(cid:173)
`strate assembly used in a prior art display device.
`FIG. 4 is a sectional view taken along line IV-IV of
`the substrate assembly FIG. 3.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`A preferred embodiment of the invention is shown in
`FIGS. 1 and 2. FIG. 2 is a partial plan view of a sub(cid:173)
`strate used in the embodiment, and FIG. 1 is a sectional 20
`view taken along line I-I of FIG. 2. On an insulating
`substrate 27, a plurality of gate bus lines 22 are formed
`in parallel and horizontally in FIG. 2, and a plurality of
`source bus lines 23 are formed vertically in the figure. In
`the vicinity of each intersection of the gate bus lines 22 25
`and source bus lines 23, a TFT 25 is formed. Each TFT
`25 drives a picture element electrode 24 which is dis(cid:173)
`posed in each region surrounded by two adjacent gate
`bus lines 22 and source bus lines 23. Under the picture
`element electrode 24, a capacitor electrode 26 is 30
`formed. On the surface of the insulating substrate 27, a
`gate electrode 28 of the TFT 25 and a capacitor elec(cid:173)
`trode 26 are formed. The gate electrode 28 is one part of
`the gate bus line 22. The gate electrode 28 and capacitor
`electrode 26 can be formed simultaneously, and made of 35
`the same material. The above-mentioned structure of
`the preferred embodiment may be the same as that of
`the device of FIG. 3.
`An anodic oxidation film 29 is formed on each of the
`gate electrode 28 and capacitor electrode 26. A gate 40
`insulating layer 30 is formed on the anodic oxidation
`films 29 and the remaining surface of the insulating
`substrate 27.
`In the region above the gate electrode 28, an i-a-Si
`film 31 and n~-a-Si films 33 are laminated on the gate 45
`insulating layer 30. The n -'--a-Si films 33 are electrically
`separated by an SiNx insulating film 32 formed on the
`i-a-Si film 31. A source electrode 34a and a drain elec(cid:173)
`trode 34b are formed on the n ~-a-Si films 33, respec(cid:173)
`tively. The source electrode 34a and drain electrode 34a 50
`are made of the same material as that of the source bus
`lines 23. and formed simultaneously with the source bus
`lines 23. The structure including the films 31. 32. and 33
`and electrodes 28. 34a and 34b constitute the TFT 25.
`One end portion of the drain electrode 34a extends over 55
`the gate insulating layer 30. A protective insulating
`layer 35 is formed to cover the TFT 25 and the gate
`insulating layer 30. The picture element electrode 24 is
`formed on the protective insulating layer 35. and elec(cid:173)
`trically connected to the drain dectrode 34b through a 60
`contact hole 40 which is formed in the protective insu(cid:173)
`lating layer 35.
`In the substrate of the embodiment having the above(cid:173)
`described structure. a three-layered dielectric lamina(cid:173)
`tion structure consisting of the anodic oxidation film 29. 65
`the gate insulating layer 30 and the protective insulating
`layer 35 is formed between the picture element elec(cid:173)
`trode 24 and the capacitor electrode 26. so that an addi-
`
`5,054,887
`
`4
`tional capacitor is formed by these two electrodes 24
`and 26 and the three-layered dielectric lamination struc(cid:173)
`ture.
`Since the additional capacitor comprises the three-
`S layered dielectric lamination structure,
`the insulation
`between the picture element electrode 24 and the capac(cid:173)
`itor electrode 26 will not easily fail as compared with
`that of the prior art which has a two-layered dielectric
`structure as mentioned above. Therefore, the possibility
`10 of producing electrical continuity between the picture
`element electrode 24 and the capacitor electrode 26
`which is caused by a pinhole can be greatly reduced.
`A production process of the preferred embodiment
`will also be described. On the insulating substrate 27
`15 such as a glass plate, a thin layer of a metal such as Ta.
`AI, or Ti is deposited in the thickness of 2000-4000 A by
`the sputtering or electron beam deposition technique.
`This thin metal film is patterned to simultaneously fo.rm
`the gate electrode 28 and the capacitor electrode 26.
`Then, the surface of the gate electrode 28 and the ca(cid:173)
`pacitor electrode 26 are subjected to anodic oxidation to
`make the anodic oxidation film 29 thereon. The thick(cid:173)
`ness of the anodic oxidation film 29 ranges from 1000 A
`to 3000 A. Thereafter, SiNx is deposited by a plasma
`CVD technique to form the gate insulating layer 30
`(thickness: 2000-5000 A). As a result, a two-layered
`dielectric lamination consisting of the anodic oxidation
`film 29 and the gate insulating layer 30 is formed.
`Furthermore, a semiconductor film of a-Si and an
`insulating film of SiNx are successively deposited, and
`then patterned by the photolithography technique to
`form the a-Si film 31 and the SiNx insulating film 32.
`Then, a semiconductor film of n + -a-Si is deposited, and
`then patterned by the photolithography technique to
`form the n +-a-Si films 33. A metal such as Ti, Mo or W
`is deposited by the sputtering or electron beam deposi-
`tion technique. and patterned by the photolithography
`technique to form the source electrode 34a and the
`drain electrode 34b. The protective insulating layer 35
`rpade of SiNx is deposited in the thickness of 2000-6000
`A by the plasma CVD technique, and the contact hole
`40 is opened in the layer 35 by the photolithography
`technique. Thereafter, a transparent conductive film
`which is mainly composed of indium oxide is deposited
`by the sputtering or electron beam deposition tech(cid:173)
`nique. and patterned to form the picture element elec-
`trode 24 which is electrically connected to the drain
`electrode 34b through the contact hole 40.
`In the substrate thus produced.
`the three-layered
`dielectric lamination structure which consists of the
`anodic oxidation film 29, the gate insulating layer 30 and
`the protective insulating layer 35 is disposed between
`the capacitor electrode 26 and the picture element elec(cid:173)
`trode 24. thereby forming an additional capacitor.
`The protective insulating layer 35 may be made of
`another insulating material such as SiO~ in place of
`SiN".
`It is understood that various other modifications will
`be apparent to and can be readily made by those skilled
`in the art without departing from the scope and spirit of
`this invention. Accordingly. it is not intended that the
`scope of the claims appended hereto be limited to the
`description as set forth herein. but rather that the claims
`be construed as encompassing all the features of patent(cid:173)
`able novelty that reside in the present invention. includ(cid:173)
`ing all features that would be treated as equivalents
`thereof by those skilled in the art to which this inven(cid:173)
`tion pertains.
`
`Exhibit 1005, page 5
`
`

`

`5
`
`5,054,887
`
`IO
`
`20
`
`What is claimed is:
`1. An active matrix type liquid crystal display device
`comprising:
`a substrate;
`a plurality of picture element electrodes arranged in a 5
`matrix on said substrate;
`a plurality of switching elements, each of said picture
`element electrodes being associated with a picture
`element electrode;
`capacitor electrodes, each of said picture element
`electrodes being partially opposed to at least one
`capacitor electrode to form a capacitor; and
`a dielectric lamination structure consisting essentially
`of three insulating layers between said picture ele- 15
`ment electrode and said capacitor electrode, a first
`the associated
`insulating layer extending over
`switching element to provide protection thereto.
`2. The device of claim 1 wherein said substrate is
`insulating and.said switching element is a thin film tran-
`sistor, a gate electrode of said thin film transistor and
`said capacitor electrode being disposed on the insulat(cid:173)
`ing substrate, and a gate insulating layer being formed
`on both said gate electrode and said capacitor electrode, 25
`said gate insulating layer being one of said three lami(cid:173)
`nated insulating layers.
`3. The device of claim 2 wherein a protective insulat(cid:173)
`ing layer is the first insulating layer and is formed on
`both said thin film transistor and said gate insulating 30
`layer, said protective insulating layer being another one
`of said three laminated insulating layers.
`4. The device of claim 3 wherein an anodic oxidation
`film is formed on said capacitor electrode, said anodic
`oxidation film being the further one of said three lami(cid:173)
`nated insulating layer.
`5. The device of claim 3 wherein said picture element
`electrode is disposed on said protective insulating layer.
`6. The device of claim 5 wherein said picture element 40
`electrode is electrically connected to the drain elec(cid:173)
`trode of said TFT,
`through a contact hole which is
`formed in said protective insulating layer.
`7. The device of claim 2. wherein a protective insulat(cid:173)
`ing layer is the first insulating layer formed on both said 45
`thin film transistor and said gate insulating layer and
`said picture element electrode is connected to the drain
`electrode of said thin film transistor through a hole
`formed on said protective insulating layer, said protec(cid:173)
`tive insulating layer being another one of said three 50
`laminated layers.
`8. The device of claim 3 wherein said protective
`insulating layer extends under said picture element elec(cid:173)
`trode.
`9. A substrate assembly for use in a flat panel display
`device in cooperation with a display material and a
`least one picture element
`second assembly having at
`electrode. said substrate assembly comprising:
`a substrate:
`
`6
`a picture element electrode provided on said sub(cid:173)
`strate, for cooperation with the picture element
`electrode of said another assembly;
`a thin film transistor formed on said substrate and
`driving said picture element;
`a protective insulating layer overlaying said thin film
`transistor to provide protection therefor;
`a capacitor electrode provided on said substrate and
`underlying said picture element electrode; and,
`a dielectric lamination structure having at least two
`insulative layers disposed between said picture
`element electrode and said capacitor electrode to
`provide electrical isolation therebetween;
`said protective insulating layer extending over said
`capacitor electrode and under said picture element
`electrode to further form one of said insulative
`layers of said dielectric lamination structure and
`contribute to the electrical
`isolation provided
`thereby.
`10. The substrate assembly of claim 9 wherein said
`thin film transistor includes a gate separated from a
`source and drain by a gate insulating layer, said gate
`insulating layer forming one of said at least two insulat(cid:173)
`ing layers.
`11. The substrate assembly of claim 10 wherein said
`dielectric lamination layer further includes an anodic
`oxidation film formed on said capacitor electrode, said
`oxidation film further being formed on said gate of said
`thin film transistor.
`12. The substrate assembly of claim 9 wherein said
`flat panel display device is a liquid crystal display de(cid:173)
`vice and said display material is a liquid crystal material.
`13. A substrate assembly for use in a matrix flat panel
`display device in cooperation with a display material
`35 and a second assembly having at least one picture ele(cid:173)
`ment electrode, said substrate assembly comprising:
`a substrate;
`a plurality of picture element areas each including a
`picture element electrode provided on said sub(cid:173)
`strate, for cooperation with the picture element
`electrode of said another assembly, each picture
`element area further including,
`a thin 'film transistor formed on said substrate and
`driving said picture element electrode: .
`a protective insulating layer overlaying said thin
`film transistor to provide protection therefor:
`a capacitor electrode provided on said substrate
`and underlying said picture element electrode:
`and.
`a dielectric lamination structure having at least two
`insulative layers disposed between said picture
`element electrode and said capacitor electrode to
`provide electrical isolation therebetween:
`said protective insulating layer extending over said
`capacitor electrode and under said picture ele(cid:173)
`ment electrode to further form one of said insula(cid:173)
`tive layers of said dielectric lamination structure
`and contribute to the electrical
`isolation pro-
`vided thereby.
`*
`
`55
`
`60
`
`* *
`
`* *
`
`65
`
`Exhibit 1005, page 6
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`: 5,054,887
`PATENT NO.
`: OCTOBER 8, 1991
`DATED
`INVENTOR(S) : H. KATO, et al.
`
`It is certified that error appears in the above-indentified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`In claim 1, column 5, lines 9-10, delete "picture element electrode;" and
`
`insert therefore -- said switching element;--
`
`Signed and Sealed this
`
`Twenty-frrst Day of October 1997
`
`Attest:
`
`Attesting Officer
`
`Commissiol1!'r of PalenlS and Trademark,,"
`
`IlRUCE LEHMAN
`
`Exhibit 1005, page 7
`
`

`

`---------------------------------~:---.~-
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`
`5,054,887
`October 8, 1991
`DATED
`INVENTOR(S): H. KATO et a1.
`
`It is certified that error appears in the above-indentified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`In claim 9, column 6,
`
`line 5, delete "said picture element" and
`
`insert --said picture element electrode--
`
`Attest:
`
`Signed and Sealed this
`
`Third Day ofFebruary, 1998
`fL.a~
`
`BRl'CE LEHMA:>;
`
`Attesting Officer
`
`C(Jmnli\".~IOIlt'r (~f PilUJrr.~ tlnd TruJt'Jtlark.'l
`
`Exhibit 1005, page 8
`
`