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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INNOLUX CORPORATION
`Petitioner
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`v.
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`PATENT OF SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
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`CASE IPR2013-00064
`PATENT 7,923,311
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`RESPONSE OF THE PATENT OWNER
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`TABLE OF CONTENTS
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`I. Background ........................................................................................................ 1
`II. Summary of Arguments ................................................................................... 1
`A. Claims 9, 10, 15, 48, and 51 of the ’311 patent are patentable over
`Taniguchi and Mori .............................................................................................. 1
`B. Claim 11 of the ’311 patent is patentable over Taniguchi, Mori, and Van
`Zant ........................................................................................................................ 6
`C. Claims 17-19 and 52 of the ’311 patent are patentable over Taniguchi,
`Mori, and Kato ...................................................................................................... 7
`III. The ’311 Patent .................................................................................................. 8
`A. Claims of the ’311 patent .............................................................................. 8
`B. The invention of the ’311 patent ................................................................. 10
`IV. Taniguchi ......................................................................................................... 14
`A. Taniguchi does not disclose a method for forming a step-like structure
`as recited in the claims of the ’311 patent ........................................................ 14
`B. Taniguchi teaches using the first conductive layer (d1) as a hard mask
`to etch the N-type semiconductor layer (d0) .................................................... 16
`C. Inherent overetch of the first conducting layer (d1)
`will not create the claimed step-like structure in Taniguchi .......................... 20
`D. A person of ordinary skill in the art would not create a step between the
`source/drain electrode and the N-type semiconductor layer of
`Taniguchi ............................................................................................................. 23
`E. Taniguchi solves the increased capacitance problem ............................... 25
`V. Mori .................................................................................................................. 27
`A. It is not clear that the teaching of Mori would have any impact on
`displays at the low frequency (60 Hz) at which they operate ......................... 28
`B. The Mori structure increases resistance and reduces ON current ......... 30
`VI. Claims 9, 10, 15, 48, and 51 are patentable over Taniguchi and Mori ...... 32
`A. Creating a step-like structure in Taniguchi is not obvious ...................... 34
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`i
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`B. There is no suggestion to those skilled in the art to combine Taniguchi
`with Mori ............................................................................................................. 36
`1. Taniguchi solves the parasitic capacitance problem ............................. 37
`2. Reducing the size of the electrode layer above the N-type
`semiconductor layer has little effect on parasitic capacitance .................... 38
`3. A person of ordinary skill in the art would likely not combine
`Taniguchi with Mori because the combined structure would have higher
`resistance and lower ON current ................................................................... 40
`4. There is no reasonable expectation of success if Taniguchi were
`modified as detailed by Dr. Kanicki .............................................................. 42
`a. The modified Taniguchi process does not connect
`the third conductive layer d3 to the first conductive layer d1 ................ 44
`b. The modified Taniguchi process has an undercut problem ............. 47
`c. Because of its complexity, the modified Taniguchi process would not
`have been obvious ........................................................................................ 50
`d. The modified Taniguchi process would change the principles of
`operation ....................................................................................................... 51
`5. Dr. Kanicki’s preference for tapering the TFT layers of Taniguchi
`is further evidence that the claimed step-like structure was not
`obvious .............................................................................................................. 54
`VII. Claim 11 is patentable over Taniguchi, Mori, and Van Zant ................. 56
`VIII. Claims 17-19 and 52 are patentable over Taniguchi, Mori, and Kato ... 57
`A. Taniguchi and Mori do not disclose element (h) “etching a portion of
`the patterned N-type semiconductor film to form source and drain regions
`using said resist” ................................................................................................. 57
`B. Claims 17-19 and 52 are patentable because Kato with Taniguchi and
`Mori also does not disclose or render obvious the claimed step-like
`structure............................................................................................................... 58
`IX. Conclusion ........................................................................................................ 59
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`ii
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`EXHIBIT LIST
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`
`Previously filed
`Exhibit 2001 – Complaint, Semiconductor Energy Laboratory Co., Ltd. v.
`Chimei Innolux Corp., et al., Case No. SACV 12-0021-JST (C.D. Cal).
`Exhibit 2002 – Defendants’ Motion to Stay Litigation Pending Outcome of Inter
`Partes Review, Semiconductor Energy Laboratory Co., Ltd. v. Chimei
`Innolux Corp., et al.
`Exhibit 2003 – Supplemental Declaration of Gregory S. Cordrey in Support of
`Defendants' Motion for Stay, Semiconductor Energy Laboratory Co., Ltd. v.
`Chimei Innolux Corp., et al.
`to Stay,
`their Motion
`in Support of
`Exhibit 2004 – Defendants’ Reply
`Semiconductor Energy Laboratory Co., Ltd. v. Chimei Innolux Corp., et al.
`Exhibit 2005 – Defendant Westinghouse Digital's Notice
`of
`Joinder,
`Semiconductor Energy Laboratory Co., Ltd. v. Chimei Innolux Corp., et al.
`Exhibit 2006 – ’311 Patent Prosecution History Excerpt - Prior Art considered
`by the Office
`Exhibit 2007 – United States Patent No. 4,857,907 (Koden)
`Currently filed
`Exhibit 2008 – Chun-sung Chiang, Chun-ying Chen, and Jerzy Kanicki,
`“Investigation of Intrinsic Channel Characteristics of Hydrogenated
`Amorphous Silicon Thin-Film Transistors by Gated-Four-Probe Structure,”
`Applied Physics Letters, Vol. 72, No. 22, pp. 2874-2876 (1998)
`Exhibit 2009 –U.S. Patent No. 5,270,567 to Mori annotated by Dr. Kanicki
`Exhibit 2010 – Chun-ying Chen and Jerzy Kancicki, “High Field-Effect-Mobility
`a-Si:H TFT Based on High Deposition-Rate PECVD Materials,” IEEE
`Electron Device Letters, Vol. 17, No. 9, pp. 437-439 (1996)
`Exhibit 2011 – Declaration of Alex Z. Kattamis, Ph.D.
`Exhibit 2012 - Willem den Boer, “Active Matrix Liquid Crystal Displays,”
`Elsevier, Chapter 2, pp. 23-48 (2005).
`
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`iii
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`Exhibit 2013 - Wang et al., “Cu/CuMg Gate Electrode for the Application of
`Hydrogenated Amorphous Silicon Thin-Film Transistors,” Electrochem.
`Solid-State Lett. Vol. 10 No. 8, pp. J83-J85 (2007).
`Exhibit 2014 - Zou, “Anisotropic Si Deep Beam Etching with Profile Control using
`SF6/O2 Plasma,” Microsystem Technologies, Vol. 10, pp. 603–607 (2004)
`Exhibit 2015 - Choi et al., “Simple Process for Making New Self-Aligned TFT
`with Improved On-Current,” Electrochemical Society Proceedings, Vol. 96-
`23, pp. 129-137, 1997
`Exhibit 2016 - Uchikoga et al., “The Effect of Contact Overlap Distance on a-Si
`TFT Performance,” Mat. Res. Soc. Symp. Proc., Vol. 258, pp. 1025-1030,
`1992
`Exhibit 2017 - Kuo et al., “Advanced Multilayer Amorphous Silicon Thin-Film
`Transistor Structure: Film Thickness Effect on Its Electrical Performance
`and Contact Resistance,” Jpn. J. Appl. Phys. Vol. 47, No. 5, pp. 3362–3367
`(2008)
`Exhibit 2018 – C. van Berkel, “Amorphous-Silicon Thin-Film Transistors: Physics
`and Properties, in Amorphous and Microcrystalline Semiconductor
`Devices,” Vol. 2 edited by J. Kanicki, Artech House, pp. 397-447 (1992).
`Exhibit 2019 –Chiang et al., “Electrical Instability of Hydrogenated Amorphous
`Silicon Thin-Film Transistors for Active-Matrix Liquid-Crystal Displays,”
`Jpn. J. Appl. Phys. Vol. 37 pp. 4704-4710 (1998)
`Exhibit 2020 – Transcript of Videotaped Deposition of Jerzy Kanicki
`Exhibit 2021 – U.S. Patent No. 6,104,042 to Wen-Jyh Sah
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`iv
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`Semiconductor Energy Laboratory Co., Ltd. (the “Patent Owner”) hereby
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`responds to the Decision to Initiate Trial for Inter Partes Review of claims 9-11,
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`15, 17-19, 48, 51, and 52 of United States Patent No. 7,923,311 (“the ’311 patent”).
`
`I.
`
`Background
`
`Petitioner Innolux Corporation requested inter partes review of claims 9-11,
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`15, 17-19, 48, 51, and 52 of the ’311 patent. Paper No. 2 (“Petition” or “Pet.”).
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`The Patent Owner submitted a preliminary response under 37 C.F.R. § 42.107(b)
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`on February 26, 2013. Paper No. 8 (“Preliminary Response” or “Preliminary
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`Resp.”). On April 30, 2013, the Patent Trial and Appeal Board (the “Board”)
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`issued a Decision to Initiate Trial for Inter Partes Review as to claims 9-11, 15, 17-
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`19, 48, 51, and 52 of the ’311 patent for obviousness over JP Patent Publication
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`02-234125 (“Taniguchi”), U.S. Patent No. 5,270,567 (“Mori”), U.S. Patent No.
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`5,054,887 (“Kato”), and Peter Van Zant, Microchip Fabrication: A Pratical Guide
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`to Semiconductor Processing, pp. 221-228 and 298 (2nd ed. 1990) (“Van Zant”).
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`Paper No. 11 (“Decision” or “Dec.”). The Board denied the Petition as to all other
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`grounds of unpatentability set forth in the Petition.
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`II.
`
`Summary of Arguments
`A. Claims 9, 10, 15, 48, and 51 of the ’311 patent are patentable over
`Taniguchi and Mori
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`Independent claim 9 and dependent claims 10, 15, 48, and 51 of the ’311
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`patent are patentable over Taniguchi and Mori. Independent claim 9 recites a
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`1
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`method of manufacturing a display device including a thin-film transistor (“TFT”)
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`having a step-like structure between the source/drain electrodes and the
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`source/drain regions. Patent Owner respectfully submits that forming a step-like
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`structure in the Taniguchi TFT is not obvious in view of Mori. Taniguchi teaches
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`away from forming a step-like structure between the first conductive layer d1 and
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`the N-type semiconductor
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`layer d0.
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` Petitioner’s expert, Dr. Kanicki,
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`acknowledged that it is not clear that the teaching in Mori would have any impact
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`on liquid crystal displays, given the low frequency at which they operate.
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`As shown in FIG. 22 of Taniguchi, the edges of the first conductive layer d1
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`(blue layer) and the N-type semiconductor layer d0 (yellow layer) are aligned (i.e.,
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`there is no step from layer d1 to layer d0). Taniguchi teaches away from forming a
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`step-like structure because the edges of the first conductive layer d1 of the
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`electrodes set the gate length of the TFT. Setting the gate length consistently
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`among TFTs in an active matrix display is of critical importance. See Ex. 2011,
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`Declaration of Alex Z. Kattamis
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`(“Kattamis Decl.”), at ¶¶ 64, 87,
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`and 88. The importance of
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`consistently setting
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`the gate
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`length
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`is
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`recognized
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`by
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`Taniguchi, which teaches that
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`the first conductive layer d1 (i.e., the layer directly on top of the source/drain
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`region) is to be used as a hard mask to etch the N-type semiconductor layer d0 in
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`order to consistently set the gate length of the TFTs. See Ex. 1006, Taniguchi, at p.
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`8. Etching the first conductive layer d1 of the electrode in Taniguchi laterally in
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`order to create a step-like structure would negatively affect the uniformity of the
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`gate length of the TFTs because the first conductive layer d1 could no longer act as
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`a hard mask when etching the N-type semiconductor layer d0.
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`In addition, Taniguchi teaches away from forming a step-like structure
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`because further etching the first conductive layer d1 to create a step-like structure
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`would reduce the overall size of the d1 layer, which may prevent the first
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`conductive layer d1 from making secure connection with the third conductive layer
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`d3 as taught by Taniguchi. When etching the first conductive layer d1 on the
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`channel side of the source electrode, the first conductive layer d1 will also be
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`etched on the opposite side of the source electrode shown in the red circle of
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`annotated FIG. 22 above. Any additional etching of the first conductive layer d1
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`would reduce the size of the first conductive layer on the left side of the source
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`electrode (red circle above), which may prevent a secure connection between the
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`third conductive layer d3 and the first conductive layer d1. Ex. 2011, Kattamis at
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`¶¶ 126, 127, and 129. Accordingly, Taniguchi teaches away from the claimed
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`3
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`invention because the claimed invention requires a step-like structure between the
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`source/drain electrode and the source/drain region of the TFT.
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`Not only does Taniguchi teach
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`away from forming a step-like structure as
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`recited in the claims of the ’311 patent,
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`but there is no motivation to combine
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`Taniguchi with Mori. Mori teaches a TFT
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`where the edges of the source/drain electrodes are formed at positions far removed
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`from the edges of the source/drain regions, such that the source/drain electrodes do
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`not overlap the gate electrode as shown in FIG. 2 of Mori. Ex. 1003, Mori at
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`Abstract; FIG. 2 (reproduced above). This is very different from what Taniguchi
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`teaches, which is that the lower portion of the source/drain electrodes (d1 layer)
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`completely covers the upper portion of the source/drain regions. In addition,
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`unlike Taniguchi, which teaches enlarging the gate electrode to cover the i-type
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`semiconductor layer, Mori teaches that the gate electrode 12 is relatively small and
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`does not cover the i-type semiconductor layer 14 or the source and drain electrodes
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`16 and 17. Ex. 2011, Kattamis Decl., at ¶¶ 67 and 152-153. Since Taniguchi’s
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`teaching is nearly opposite of Mori’s teaching, these two references teach
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`dramatically away from each other. Where the references teach away from their
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`combination, it is improper to combine them.
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`4
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`Furthermore, Mori also teaches that using an arrangement such as shown in
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`FIG. 2 can almost eliminate parasitic capacitance between the gate and the drain
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`electrodes. Ex. 1003, Mori, at col. 2, ll. 11-22. However, a person of ordinary
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`skill in the art would not look to Mori to modify the TFT disclosed in Taniguchi.
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`This is because a person of ordinary skill in the art would not understand that the
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`benefit taught by Mori (reducing parasitic capacitance) would have any impact on
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`the display at the low frequency (60 Hz) at which liquid crystal displays operate.
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`Petitioner’s expert Dr. Kanicki explains that liquid crystal displays operate at 60
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`Hz and that FIG. 7 of Mori (reproduced below) displays the frequency in terms of
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`kHz. Ex. 2020,
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`Videotaped Deposition of
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`Jerzy Kanicki
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`(“Kanicki
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`Dep.”), at p. 182, ll. 7-17.
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`Further, Dr. Kanicki, an
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`expert in this field, states
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`that it is not clear that the teaching of Mori would have any impact at the low
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`frequency (60 Hz) at which LCDs operate. Ex. 2020, Kanicki Dep., at p. 182, ll. 7-
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`17. Thus, it also would not be clear to a person of ordinary skill in the art that the
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`teaching of Mori would have any impact on LCDs given the low frequency
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`(typically 60 Hz or 120 Hz) at which they operate. Mori’s specification even states
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`5
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`that the “testing element in FIG. 6 has a capacitance almost equal to that of the
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`testing element in FIG. 5 in the low-frequency region, since the n-type
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`semiconductor layer 15a formed on the i-type semiconductor layer 14a … serves
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`as an electrode in the low-frequency region.” Ex. 1003, Mori, col. 4, ll. 25-31.
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`Accordingly, there would be no motivation for a person of ordinary skill in the art
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`to modify Taniguchi in hopes of reducing parasitic capacitance in TFTs used in
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`LCDs because Mori teaches (e.g. at FIG. 7) that there is no reduction in parasitic
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`capacitance at low frequencies (1000 Hz).
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`For all of these reasons, and the additional reasons discussed below, creating
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`a step-like structure between the first conductive layer d1 and the N-type
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`semiconductor layer d0 in Taniguchi would not have been obvious. The only
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`possible explanation for modifying Taniguchi to include a step-like structure as
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`recited in the claims of the ’311 patent is the impermissible use of hindsight. Even
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`Dr. Kanicki states that he would have tapered the TFT structure in Taniguchi
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`instead of forming a step-like structure. See Ex. 2020, Kanicki Dep., at p. 408, ll.
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`11-21; p. 409, ll. 8-13; p. 460, ll. 2-16. Thus, claims 9, 10, 15, 48, and 51 are
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`patentable over the combination of Taniguchi and Mori.
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`B. Claim 11 of the ’311 patent is patentable over Taniguchi, Mori,
`and Van Zant
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`The Patent Owner respectfully submits that dependent claim 11, which
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`depends from independent claim 9, is patentable over Taniguchi, Mori, and Van
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`6
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`Zant. As discussed in Section II.A., Taniguchi teaches away from forming a step-
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`like structure, and there is no motivation to combine Taniguchi with Mori.
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`Petitioner cites Van Zant only for its disclosure of overetching. Accordingly,
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`dependent claim 11 is also patentable over Taniguchi, Mori and Van Zant.
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`C. Claims 17-19 and 52 of the ’311 patent are patentable over
`Taniguchi, Mori, and Kato
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`The Patent Owner respectfully submits that independent claim 17 and
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`dependent claims 18-19 and 52 are patentable over Taniguchi, Mori, and Kato. As
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`discussed in Section II.A., Taniguchi teaches away from forming a step-like
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`structure and there is no motivation to combine Taniguchi with Mori.
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`Furthermore, independent claim 17 recites (in element h) “etching a portion
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`of the patterned N-type semiconductor film to form source and drain regions using
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`said resist.” The “resist” referred to in this claim element is the same resist used
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`to etch a portion of a conductive layer to form source and drain electrodes as
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`recited in element g of claim 17. That is, claim 17 provides that the same resist is
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`used to form the source and drain electrodes and to form the source and drain
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`regions. Taniguchi and Mori, either separately or combined, do not teach or
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`suggest this claim limitation. Instead, as discussed above, Taniguchi uses the first
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`conductive layer d1 as a hard mask to etch the N-type semiconductor layer d0 and
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`form the source and drain regions. See Ex. 1006, Taniguchi, at p. 8. Taniguchi
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`does not teach using a photoresist layer to etch the N-type semiconductor layer d0
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`7
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`because the Cr layer (d1) is used as a hard mask for etching the N-type
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`semiconductor layer (d0). No processing steps are disclosed in Mori. Kato does
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`not cure the foregoing deficiencies of Taniguchi and Mori.
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`Accordingly, claims 17-19 and 52 are patentable over Taniguchi, Mori, and
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`Kato.
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`It is respectfully submitted that the Petitioner cannot meet its burden of
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`proving that any of claims 9-11, 15, 17-19, 48, 51 and 52 is obvious over
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`Taniguchi, Mori, Van Zant and Kato. See 35 USC 316(e).1
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`III. The ’311 Patent
`A. Claims of the ’311 patent
`This proceeding involves independent claims 9 and 17, along with
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`dependent claims 10, 11, 15, 18, 19, 48, 51, and 52. Independent claims 9 and 17
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`recite the following2:
`
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`1 Patent Owner respectfully submits that the Board lacks statutory authority to
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`consider the Petition because Petitioner failed to identify all real parties-in-interest
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`according to 35 U.S.C. § 312(a)(2). Notably, Chi Mei Optoelectronics USA, Inc.,
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`Acer America Corporation, ViewSonic Corporation, VIZIO
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`Inc., and
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`Westinghouse Digital, LLC are real parties-in-interest, which Petitioner failed to
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`identify in its Petition. See Paper No. 8, Preliminary Response, at 3-10. The
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`Petition should have been denied on this ground.
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`8
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`Claim elements of claim 9
`
`Claim elements of claim 17
`
`Claim 9. A method of manufacturing a
`display device including a thin film
`transistor, the method comprising the
`steps of:
`(a) forming a gate electrode over a
`glass substrate;
`(b) forming a gate insulating film
`comprising silicon nitride on said gate
`electrode;
`(c) forming a first semiconductor film
`over said gate electrode with said gate
`insulating film interposed therebetween;
`
`(d) forming an N-type semiconductor
`film on said first semiconductor film;
`(e) patterning said first and N-type
`semiconductor films using a first
`photomask;
`(f) forming a conductive layer on at
`least the patterned N-type
`semiconductor film;
`(g) etching a portion of said conductive
`layer to form source and drain
`electrodes using a resist formed by a
`second photomask;
`(h) etching a portion of the patterned N-
`type semiconductor film to form source
`and drain regions by dry etching without
`removing said resist wherein a channel
`forming region is formed in said first
`semiconductor film between said source
`and drain regions; and
`
`Claim 17. A method of manufacturing a
`display device including a thin film
`transistor, the method comprising the
`steps of:
`(a) forming a gate electrode over a
`glass substrate;
`(b) forming a gate insulating film
`comprising silicon nitride on said gate
`electrode;
`(c) forming a first semiconductor film
`comprising amorphous silicon over said
`gate electrode with said gate insulating
`film interposed therebetween;
`(d) forming an N-type semiconductor
`film on said first semiconductor film;
`(e) patterning said first and N-type
`semiconductor films using a first
`photomask;
`(f) forming a conductive layer on at
`least the patterned N-type
`semiconductor film;
`(g) etching a portion of said conductive
`layer to form source and drain
`electrodes using a resist formed by a
`second photomask;
`(h) etching a portion of the patterned N-
`type semiconductor film to form source
`and drain regions using said resist
`wherein a channel forming region is
`formed in said first semiconductor film
`between said source and drain regions;
`
`
`2 Note that the reference numerals (a, b, c, …) used in claim chart herein
`
`correspond to those used in Section VII of the Petition. See Petition, at pp. 20-58.
`
`
`
`9
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`

`

`Claim elements of claim 9
`
`Claim elements of claim 17
`
`
`
`(i) forming a passivation film over said
`glass substrate to cover at least said
`source and drain electrodes, said
`channel forming region, a part of a
`surface of said source region not
`covered by said source electrode and a
`part of a surface of said drain region not
`covered by said drain electrode after
`removing said resist,
`
`
`(j) wherein an upper portion of each of
`said source and drain regions extend
`beyond a lower portion of each of said
`source and drain electrodes so that a
`distance between the source and drain
`regions
`is shorter
`than a distance
`between the source and drain electrodes.
`
`
`(i) forming a passivation film over at
`least said source and drain electrodes
`and said channel forming region after
`removing said resist; and
`
`(j) forming a pixel electrode over said
`passivation film wherein said pixel
`electrode is electrically connected to
`said source electrode or said drain
`electrode,
`(k) wherein an upper portion of each of
`said source and drain regions extend
`beyond a lower portion of each of said
`source and drain electrodes so that a
`distance between the source and drain
`regions
`is shorter
`than a distance
`between the source and drain electrodes.
`
`The invention of the ’311 patent
`
`B.
`The claims of the ’311 patent are directed to a method of manufacturing a
`
`thin film transistor (“TFT”) as shown in FIGS. 3(A)-3(H). See Ex. 1001, the ’311
`
`patent, col. 5, l. 55 – col. 7, l. 9. More specifically, the claims of the ’311 patent
`
`recite a method for manufacturing a display device including a thin film transistor
`
`having a “step-like structure.” This step-like structure is recited in the claims 9 and
`
`17 as follows: “an upper portion of each of said source and drain regions extend
`
`beyond a lower portion of each of said source and drain electrodes so that a
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`
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`10
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`

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`distance between the source and drain regions is shorter than a distance between
`
`the source and drain electrodes.” Id; Ex. 2011, Kattamis Decl., at ¶¶ 40-43. An
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`annotated version of FIG. 3(H) from the ’311 patent reproduced below shows the
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`
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`claimed step-like structure.
`
`
`
`
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`As shown in the above figure, the ends of the source and drain regions 11
`
`and 12 extend beyond the ends of the source and drain electrodes 9 and 10, so the
`
`distance between the source and drain regions (distance between the red lines) is
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`shorter than the distance between the source and drain electrodes (distance between
`
`blue lines). The claimed manufacturing method of the ’311 patent used to form the
`
`step-like structure includes forming a gate electrode 3 over a glass substrate 1 and
`
`forming a gate insulating film 4, which may include silicon nitride, over the gate
`
`electrode 3. Next, a first semiconductor film (or intrinsic amorphous silicon film
`
`5) is formed over the gate insulating film 4 and the gate electrode 3, followed by
`
`forming an N-type semiconductor film (or doped amorphous silicon layer 6, which
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`
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`11
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`

`

`is the layer from which source region 11 and drain region 12 are formed) over the
`
`first semiconductor film. See Ex. 1001, the ’311 patent, col. 5, l. 55- col. 6, l. 50
`
`
`
`and FIGS. 3(A)-3(C).
`
`Subsequently,
`
`the
`
`first
`
`semiconductor film and the N-type
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`semiconductor film are patterned
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`using a resist formed by a photomask P2 to form a TFT island as shown in FIG.
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`3(D), and a conductive layer, such as a chromium layer 7, is then formed over the
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`patterned N-type semiconductor film as shown in FIG. 3(E). Id., at col. 6, ll. 50-
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`55. A portion of the conductive
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`layer 7 is then etched to form source
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`and drain electrodes 9 and 10 using a resist 8 formed by a photomask P3. Without
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`removing the resist 8, a portion of the patterned N-type semiconductor film is
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`etched to form a source region 11, drain region 12, and a channel formation region
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`between
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`the source and drain
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`regions. Id., at col. 6, ll. 55-62;
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`FIG. 3(F).
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`In one embodiment, a wet etching process may be carried out without
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`peeling the resist 8 off to perform an overetching process to make the distance
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`between the source and drain electrodes 9 and 10 larger than the distance between
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`
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`12
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`

`

`
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`the source and drain regions 11 and 12 as shown in FIG. 3(G) of the ’311 patent
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`reproduced herein. Id,. at col. 6, ll. 63-66.
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`As noted above, the ’311 patent teaches using the same resist for etching
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`both the source and drain electrodes 9 and 10 and the source and drain regions 11
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`and 12. Using the same resist for these etching processes reduces the number of
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`photomask processes necessary to form the TFT and helps to control accurately the
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`length of the channel formation region. Ex. 2011, Kattamis Decl., ¶¶ 29 and 50-
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`54. Also, using the same resist for these etching processes prevents a mask
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`misalignment when forming the source and drain electrodes 9 and 10 and source
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`and drain regions 11 and 12, which would cause an undesirable variation of TFT
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`performance characteristics. Id.
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`The claimed method also includes removing the resist 8 as shown in FIG.
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`3(G) and then forming a passivation
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`film 13 to cover the source and
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`drain electrodes 9 and 10, channel
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`formation region 5, and a part of the
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`source and drain regions 11 and 12
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`as shown in FIG. 3(H). Ex. 1001, the ’311 patent, at col. 7, ll. 1-9.
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`
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`13
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`

`

`
`
`IV. Taniguchi
`A. Taniguchi does not disclose a method for forming a step-like
`structure as recited in the claims of the ’311 patent
`
`Taniguchi does not disclose a step-like structure between the source and
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`drain electrodes and the source and drain regions as claimed in the ’311 patent.
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`Instead, Taniguchi discloses a TFT having a different structure where the edges of
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`the source and drain electrodes are aligned with the edges of the source and drain
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`regions, respectively. In addition, Taniguchi discloses a TFT having multilayered
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`source and drain electrodes SD3 and SD4 that include a first conductive layer d1, a
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`second conductive layer d2, and a third conductive layer d3. Ex. 1006, Taniguchi,
`
`at p. 22. As shown in FIG. 22 of Taniguchi, it is these three layers of the source
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`and drain electrodes that appear to form a step-like structure with one another but
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`not with the source and drain regions as required by the claims of the ’311 patent.
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`As shown below in the annotated portion of Taniguchi’s FIG. 22, the first
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`conductive layer d1 (shown in
`
`blue) of the source and drain
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`electrodes SD3
`
`and SD4
`
`entirely covers
`
`the N-type
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`semiconductor layer d0 (shown
`
`in yellow), which corresponds
`
`
`
`14
`
`

`

`
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`to the source and drain regions as claimed in the ’311 patent. In other words, the
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`ends of the first conductive layer d1 are aligned with the ends of the N-type
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`semiconductor layer d0.
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`Accordingly, element (j) of claim 9 and element (k) of claim 17 (“wherein
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`an upper portion of each of said source and drain regions extend beyond a lower
`
`portion of each of said source and drain electrodes so that a distance between the
`
`source and drain regions is shorter than a distance between the source and drain
`
`electrodes”) is not disclosed or suggested in Taniguchi.
`
`Petitioner’s expert, Dr. Kanicki, ignored the d1 layer of Taniguchi in stating
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`that Taniguchi discloses creating a step-like structure as recited in claim elements
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`9(j) and 17(k) between layer d2 and layer d0. See Exhibit 1014, Declaration of
`
`Jerzy Kanicki, Ph.D (“Kanicki Decl.”) at ¶ 74. However, Dr. Kanicki’s argument
`
`completely ignores the existence of the first conductive layer (d1), which
`
`Taniguchi discloses to be the lower portion of the source and drain electrodes SD3
`
`and SD4. See Ex. 1006, Taniguchi, at p. 22 and FIG. 22. When asked why he did
`
`not discuss layer d1 in paragraph 70 of his declaration for IPR2013-00065
`
`regarding claim elements 31(e) and 35(e), which are identical to claim elements
`
`9(j) and 17(k), Dr. Kanicki did not have an explanation and only could answer: “I
`
`don't know. Maybe I was not -- I was not -- I didn't think about it, you know.” See
`
`Ex. 2020, Kanicki Dep., at p. 452, ln. 17 – p. 453, ln. 22. Thus, Dr. Kanicki’s
`
`
`
`15
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`

`
`
`assertion in paragraph 74 of his declaration that Taniguchi discloses claim
`
`elements 9(j) and 17(k) is incorrect. The Board should give no weight to Dr.
`
`Kanicki’s foregoing assertion.
`
`B.
`
`Taniguchi teaches using the first conductive layer (d1) as a hard
`mask to etch the N-type semiconductor layer (d0)
`
`As is well known in the art, gate lengths are perhaps the most critical
`
`dimension in a transistor. Ex. 2011, Kattamis Decl., at ¶¶ 64 and 87. Dr. Kanicki
`
`agrees that control of the gate length is very important because if the gate length
`
`varies from one TFT to another, then the drain current would vary, which as Dr.
`
`Kanicki states is an important, undesirable effect for the performance of the
`
`transistor. See Ex. 2020, Kanicki Dep., at p. 347, ll. 6-18. The control of gate
`
`lengths in the manufacturing process is a critical concern because slight variations
`
`in the gate lengths can lead to non-uniform TFT characteristics across the display
`
`area. Id.
`
`In an effort to address this issue, Taniguchi teaches that the first conductive
`
`layer d1 (i.e., the layer on top of the source/drain region) is to be used to define the
`
`gate length of the TFT device to ensure the best accuracy. Taniguchi teaches using
`
`the first conductive layer d1 as a hard mask to etch the N-type semiconductor layer
`
`d0 in order to consis