SEL EXHIBIT NO. 2020
`
` PART 2
`
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
`
`
`
` PART 2
`
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
`
`
`
` UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Page 241
`
` INNOLUX CORPORATION,
`
` Petitioner,
`
` vs. No. IPR2013-00064
`
` Patent 7,923,311 PATENT
`
` OF SEMICONDUCTOR,
`
` ENERGY LABORATORY CO., LTD.,
`
` Patent Owner.
`
` ------------------------------------------------------
`
` VIDEOTAPED DEPOSITION OF JERZY KANICKI
`
` Irvine, California
`
` Wednesday, June 26, 2013
`
` Volume 2
`
` Reported by:
`
` ANGELA METZ
`
` CSR No. 12454
`
` JOB No. 1684556
`
` PAGES 241 - 472
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` UNITED STATES PATENT AND TRADEMARK OFFICE
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` BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`Page 242
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` INNOLUX CORPORATION,
`
` Petitioner,
`
` vs. No. IPR2013-00064
`
` Patent 7,923,311 PATENT
`
` OF SEMICONDUCTOR,
`
` ENERGY LABORATORY CO., LTD.,
`
` Patent Owner.
`
` ------------------------------------------------------
`
` Deposition of JERZY KANICKI, Volume
`
` II, taken on behalf of Patent Owner, at 3
`
` Park Plaza, Suite 1100, Irvine,
`
` California, beginning at 9:08 a.m. and
`
` ending at 5:57 p.m. on Wednesday, June
`
` 26, 2013, before ANGELA METZ, Certified
`
` Shorthand Reporter No. 12454.
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` APPEARANCES:
` FOR THE PETITIONER:
` JEFFER MANGELS BUTLER & MITCHELL LLP
` BY: GREGORY S. CORDREY, ESQ.
` 3 Park Plaza
` Suite 1100
` Irvine, CA 92614
` 949.623.7236
` GCordrey@jmbm.com
`
` FOR THE PATENT OWNER:
`
` STEPTOE & JOHNSON LLP
` BY: STANLEY A. SCHLITTER, ESQ.
` DOUGLAS R. PETERSON, ESQ.
` TERRY TSAI, ESQ.
` 115 South LaSalle Street
` Suite 3100
` Chicago, IL 60603
` 312.577.1250
` Sschlitter@steptoe.com
` Dpeterson@steptoe.com
`
` VIDEOGRAPHER: SCOTT SLATER
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` INDEX
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`WITNESS EXAMINATION
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`Page 244
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`JERZY KANICKI
`
`VOLUME II
`
` BY MR. SCHLITTER 246
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` EXHIBITS
`
`Exhibit 1006 Japanese Unexamined Patent 286
`
`Exhibit 1014 Declaration of Jerzy Kanicki, 285
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` Ph.D.
`
`Exhibit 2009 United States Patent 5,270,567 280
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`Exhibit 2010 High Field-Effect-Mobility a-Si:H 370
`
`12
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` TFT Based on High Deposition-Rate
`
` PECVD Materials
`
` INFORMATION REQUESTED
`
` (None.)
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` INSTRUCTION NOT TO ANSWER
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` (None.)
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` Irvine, California, Wednesday, June 26, 2013
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` 9:08 a.m.
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`Page 245
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` THE VIDEOGRAPHER: Good morning. 09:08AM
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` We are on the record at 9:08 a.m. on
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` June 26th, 2013.
`
` This is the video-recorded deposition of
`
` Mr. Jerzy Kanicki, Volume 2.
`
` My name is Scott Slater here with our court 09:08AM
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` reporter, Angela Metz. We are here from Veritext
`
` Legal Solutions at the request of counsel for the
`
` patent owner.
`
` This deposition is being held at 3 Park
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` Plaza, Suite 1100, in the City of Irvine, California 09:09AM
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` 92614.
`
` The caption of this case is Innolux
`
` Corporation versus Patent of Semiconductor Energy
`
` Laboratory Co., dot LTD, Case No. IPR 2013-0006 --
`
` what are we doing now -- 64 -- thank you -- Patent 09:09AM
`
` No. 7923311.
`
` Please note that audio and video recording
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` will take place unless all parties agree to go off
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` the record. The microphones are sensitive and may
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` pick up whispers, private conversations, or cellular 09:09AM
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` interference.
`
` I am not authorized to administer an oath.
`
` I am not related to any party in this action, nor am
`
` I financially interested in the outcome in any way.
`
` May I please have an agreement from all 09:10AM
`
` parties that we may proceed.
`
` MR. SCHLITTER: We agree.
`
` MR. CORDREY: That's fine.
`
` THE VIDEOGRAPHER: Thank you.
`
` At this time, will counsel and all present 09:10AM
`
` please identify themselves for the record.
`
` MR. SCHLITTER: For the patent owner,
`
` Semiconductor Energy Laboratory, Stan Schlitter,
`
` Doug Peterson, and Terry Tsai.
`
` MR. CORDREY: For petitioner Innolux 09:10AM
`
` Corporation, Greg Cordery of Jeffer Mangels Butler &
`
` Mitchell.
`
` THE VIDEOGRAPHER: Thank you very much.
`
` Will the court reporter please administer
`
` the oath.
`
` JERZY KANICKI,
`
` having been administered an oath, was examined and
`
` testified as follows:
`
` EXAMINATION
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` BY MR. SCHLITTER:
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` Q Okay. I have a few more questions on 60,
`
` on the first of the IPR petitions, and then we'll go
`
` to the second one. 09:10AM
`
` A Okay.
`
` Q Although there's a lot of overlap, but --
`
` What does the word "channel" mean in
`
` connection with a thin-film transistor?
`
` A Channel? That's -- it's -- would be 09:11AM
`
` defined as an area of the semiconductor below gate
`
` electrodes at the interface between a gate insulator
`
` -- gate insulator on the semiconductor. It means
`
` the channel will be extended inside the amorphous
`
` silicon up to a certain depth. 09:11AM
`
` Q What is -- have you heard the term
`
` "channel-forming region"?
`
` A Channel-forming region will be -- my
`
` opinion -- same area that I just defined early on.
`
` It means the area located below the gate electrode 09:12AM
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` at the interface, between the gate insulator and the
`
` semiconductor.
`
` And so in order to form the channel, you
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` will have to apply the gate voltage. And the gate
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` voltage, in the case of the amorphous silicon, which 09:12AM
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` is anti-polymorphous (phonetic) silicon will be
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` positive.
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` The gate voltage will make the band bending
`
` amorphous silicon in such a way that there will be
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` accumulation of the electrodes within the channel. 09:12AM
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` And that -- and the gate voltage will allow
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` formation of the -- of the channel in forming region
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` of the channel will be -- then the region between
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` source and the drain regions within -- below --
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` sorry -- below -- 09:13AM
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` THE REPORTER: I'm sorry. "Regions"?
`
` THE WITNESS: Regions below gate electrode.
`
` BY MR. SHCLITTER:
`
` Q Did I hear the word right, "band bending"?
`
` A Yes. In amorphous silicon, okay, amorphous 09:13AM
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` silicon is a semiconductor. A semiconductor would
`
` be characterized by conduction with the valance
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` band.
`
` For amorphous silicon specifically, it's
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` the bands that are modifying because of the 09:13AM
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` existence of disorder (phonetic). And they're
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` modified by existence of this so-called telestate
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` and the recap state that we discussed yesterday.
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` Then if you apply the voltage on the gate,
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` then a difference -- at least a potential difference 09:13AM
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` -- will be responsible for the band bending at the
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` interface with the gate insulator.
`
` Q When a band bends, what does that mean?
`
` A That means that you -- in this specific
`
` case you will have an accumulation of these 09:14AM
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` electrons, because when you have a band bending, in
`
` the case of the amorphous silicon, the Fermi level
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` that exists in amorphous silicon in the middle of
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` the gap will go closer to the conduction band. And
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` because of that, you have accumulation of the 09:14AM
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` carriers, which will be the electrons in this
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` specific case.
`
` Q What does "channel length" mean?
`
` A Channel length we discussed yesterday, and
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` it's -- there are at least two definitions, you may 09:14AM
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` say, of the channel length.
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` There is a definition, as we discussed
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` yesterday, the designers would use, and that would
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` be the channel length would be defined by the width
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` of the gate electrode. 09:14AM
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` And then you have an intrinsic channel
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` length that we discussed yesterday also when you
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` gave me the past publication.
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` And that intrinsic channel length, that
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` would be the channel length of the device. That 09:15AM
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` would be corrected for Delta L -- with Delta L would
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` be, then, the change in the channel length
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` associated with the source drain-contacted
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` resistances.
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` Q Would you take a look at Figure 2 in Mori? 09:15AM
`
` A Figure 2 in Mori? Yes.
`
` Q Where would the channel-forming region be
`
` in Figure 2?
`
` A The channel-forming region in Figure 2
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` would be below the gate electrodes as region defined 09:15AM
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` in the semiconductor, which is Label 14. And it's
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` at the interface with the gate insulator, which is
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` Labeled 13. And so that would be at the interface
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` between the gate insulator and the semiconductor in
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` -- in the area where you have a gate electrode. 09:16AM
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` Q When you say "below the gate," do you mean
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` in the figure, actually is above the gate?
`
` A Yeah, above the gate. Above the gate.
`
` Q Okay.
`
` A So it's at the interface between the 09:16AM
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` semiconductor gate and insulator just above the
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` gate. Yes, you are correct.
`
` Q So where would the ends of the
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` channel-forming region be in Figure 2?
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` A Yeah. It's -- as I mentioned, that -- that 09:17AM
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` would be a definition of the design channel length.
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` That is where people who are engineers will use --
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` the intrinsic channel length will have to be
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` corrected by -- for the contact resistance. Then it
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` will be very close to the design channel length with 09:17AM
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` some modification of Delta L.
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` Q Where are the ends of the channel-forming
`
` region in Figure 2?
`
` A Well, that would be L minus Delta L. That
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` means you have -- if you have an L, a Delta L will 09:17AM
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` be in the -- the different -- not different -- I
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` would say reduction or increase of channel length
`
` due to a contact resistance.
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` Then it depend on the devices. Either the
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` channel length would be slightly smaller or slightly 09:18AM
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` larger than the design channel length.
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` Q And the design channel length again is
`
` what?
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` A And the design channel length will be the
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` width of the gate electrode. 09:18AM
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` Q 12?
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` A Label 12, yes.
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` Q Is there no difference, then, in
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` channel-forming region between Figure 1 and
`
` Figure 2? 09:18AM
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` A Yes, that would be correct. That would be
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` -- the region would be -- as long as the Figure 1,
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` the gate electrode, Label No. 2, has the same design
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` channel length as in Figure 2, Label 12.
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` As long as in both cases the channel length 09:19AM
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` -- design channel length is the same, then
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` channel-forming region would be the same.
`
` Q So the channel-forming region isn't
`
` affected by whether the electrodes are positioned as
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` in Figure 1 where they overlap the gate, or 09:19AM
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` Figure 2, where they are set back away from the gate
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` vertically?
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` A Yeah. The channel-forming regions, they
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` are defined by the band bending of the
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` semiconductor. Hence, the capacities of between the 09:19AM
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` source draining gate pass the capacitance of this
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` case, based on this invention, looks like it will be
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` influenced by the position of the metal gate with
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` respect to N-Plus amorphous silicon.
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` In other words, in the Figure 1, the metal 09:20AM
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` gate in numeral 7 and numeral 6, it's aligned with
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` the N-Plus region. Figure 2, numeral 17 and numeral
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` 16 represents cells contacts is not aligned with
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` N-Plus regions. Then based on this invention, at
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` least based on the data that they are providing, 09:20AM
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` then pass the capacity or CGS, is reduced.
`
` Q But the -- but the channel-forming region
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` isn't affected, whether it's the structure Figure 1
`
` or Figure 2; am I correct?
`
` A Yes. The channel-forming region will -- 09:20AM
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` will be as I mentioned, dictated by band and
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` bending. And then for a given gate bias that would
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` be applied in Figure 1 on the gate, numeral 2, and
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` the Figure 2 on the gate numeral 12.
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` If the gate bias is the same, and the 09:21AM
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` channel length the same, the on current will be the
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` same in both devices.
`
` Q What would be the path that the electrons
`
` would take in Figure 1?
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` A Figure 1? Yeah. The path would be once 09:22AM
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` you accumulate the electrons in the -- within the
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` channel, it would be at the interface between the
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` gate insulator number -- Label No. 3, and the
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` semiconductor, Label No. 4 in Figure 1 in that
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` interface. 09:22AM
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` Then it's -- you will -- those electrons
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` will have to be extracted in one contact and
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` injected on the other contact.
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` If it's extraction is taking place on the
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` source electrode, then injection will take place on 09:22AM
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` the drain electrode.
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` Then the electrons will have to go through
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` the thickness of the amorphous silicon, will have to
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` go through the interface between amorphous silicon
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` and N-Plus region. 09:23AM
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` We have to go through the N-Plus. We have
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` to go through the interface between N-Plus and the
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` metal. And that would be true in both cases on the
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` source -- on the source side and drain side in the
`
` Figure 1. 09:23AM
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` Q Because the -- do the electrons flow from
`
` the semiconductor layer to the N-Plus layer equally
`
` distributed along the length of the N-Plus layer?
`
` A I think I would like you to clarify that
`
` question. It's not quite clear what you're asking. 09:23AM
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` Q Well, if you look at the N-Plus layer five
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` in Figure 1.
`
` A Yes.
`
` Q So the chart is that accumulate when a gate
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` voltage is applied at the interface of the amorphous 09:24AM
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` layer four, amorphous silicon layer four and the
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` gate insulator three --
`
` A Yes.
`
` Q -- you said travel up to the -- ultimately
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` to the source drain electrodes? 09:24AM
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` A That's correct.
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` Q So do they travel along -- through the
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` N-Plus layer along the entire length of the N-Plus
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` layer equally?
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` A No. I think yesterday when we had 09:24AM
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` discussed about the contact resistance and the
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` source and drain, and we had discussed about the
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` channel length -- design channel length and
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` intrinsic channel length, I also mentioned or
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` introduced another concept which was the carrier 09:25AM
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` charge transfer length.
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` THE REPORTER: I'm sorry. Carrier?
`
` THE WITNESS: Carrier charge transfer
`
` length.
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` And that means that the length that the 09:25AM
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` carriers in the amorphous silicon can be transferred
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` from the channel to the source or drain contacts.
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` And then once those carriers, they are
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` transferred from the channel to the source drain
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` contacts, then if the metal that's just above, then 09:25AM
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` of course the carriers will go vertically and they
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` will be collected by the metal electrode because the
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` resistance electrode is smaller than N-Plus. That
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` is Figure 1.
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` But then Figure 2, on the other hand, then 09:25AM
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` the carriers, once they are transferred to the
`
` N-Plus region, since we have the electrode -- source
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` drain electrode recessed with respect to the etch of
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` the N-Plus region, then they will have to be -- they
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` will transfer along the layer of N-Plus before they 09:26AM
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` can at least be collected by the -- by the metal.
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` Then in Figure 2, the carriers will have to
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` at least travel through the N-Plus depending on the
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` offset between the gate, numeral 12, and the
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` electrode, numeral 16. 09:26AM
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` If that offset is larger than -- I would
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` say probably .2 micron, they will travel because the
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` transfer length for the amorphous silicon is about
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` .2 -- .2 length.
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` That's why you need the overlap. Yesterday 09:26AM
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` we discussed about that overlap between the gate and
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` source and drain. So that overlap is needed because
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` of that transfer length.
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` It's different from amorphous. You know,
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` it is different from the amorphous case in the 09:27AM
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` crystalline silicon because in the crystalline
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` silicon amorphous case you have accumulation -- you
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` have a depletion region being formed --
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` THE REPORTER: I'm sorry. Because you have
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` a? 09:27AM
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`Page 257
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` THE WITNESS: Depletion region being formed
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` in the case of the amorphous silicon we have
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` accumulation that being formed, and that will
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` accumulate electrons.
`
` BY MR. SHCLITTER: 09:27AM
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` Q So the transfer length in Figure 1, for
`
` example --
`
` A Yes.
`
` Q -- will be sort of a horizontal distance in
`
` Figure 1? 09:27AM
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` A Yes. In Figure 1, that will be a
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` horizontal -- yeah, it can be some horizontal
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` distance, yes.
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` Q Measured from the respective ends of the
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` N-Plus layer? 09:27AM
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` A Respective ends of the gate electrode -- of
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` the ends of gate electrode.
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` Q Well, they're the same in Figure 1, are
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` they not?
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` A Yeah, but the transfer length, that means 09:27AM
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` that you have to -- at least the carriers can be
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` collected vertically, but also can be collected also
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` on the up to about certain distance which will be
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` transfer length outside of the edge of the gate
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` electrode. 09:28AM
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` Q Okay.
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` A But it's small anyway.
`
` Q Okay. So are you saying the transfer
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` length is?
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` A .2 micron. 09:28AM
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` Q .2 microns along the vertical etch of the
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` N-Plus gate electrode layer or -- I mean source
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` drain electrode metal?
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` A It's -- if I -- yeah. If I have -- yes.
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` If you have a gate -- can I maybe -- okay. 09:28AM
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` Okay. This is my gate electrode. And that
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` would be my source drain electrode. And now I have
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` a source and drain -- or drain electrode, gate
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` electrode right now, and this specific gate is
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` perfectly aligned, okay, what I'm showing right now. 09:28AM
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` Q That's not Figure 1?
`
` A I know, no. But they're perfectly aligned.
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` Then another for the carriers to be
`
` collected from the channel region there is a certain
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` transfer length from that channel region. And that 09:29AM
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` transfer length is about .2 micron, I mentioned.
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` What that means now -- that means now I
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` will have to now move my drain electrode .2 micron
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` to the left or .2 to your right.
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` Q To overlap -- 09:29AM
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`Page 259
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` A To overlap.
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` And that would be a minimum that would be
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` required for the electrons to be transferred from
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` the channel to the drain electrode.
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` Q Do the electrons transfer mainly through 09:29AM
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` the transfer length?
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` A In the case of the amorphous silicon on
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` this agreement is that because amorphous silicon is
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` high resistant material, there is a confinement
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` region where the carriers can be injected and 09:29AM
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` extracted. And that's its region, which is about,
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` as I mentioned, transfer length.
`
` Q That's the transfer length?
`
` A Yeah, because the transfer length, it's
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` related -- there's a relation between transfer 09:30AM
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` length and the Debye length.
`
` THE REPORTER: I'm sorry?
`
` THE WITNESS: Debye. Debye length.
`
` Debye length is associated --
`
` BY MR. SHCLITTER: 09:30AM
`
` Q How do you spell that?
`
` A Debye? Oh, D-a-b-y-e (sic), I believe.
`
` Debye length.
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` And Debye length is associated directly
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` with the density of trap states or deep gap states 09:30AM
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` in the amorphous silicon.
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` Then if you have a large density of -- of
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` -- of trap states, then the Debye length is small,
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` transfer length is small. That's why amorphous
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` silicon, you like to have as small as possible 09:30AM
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` density of interface states to be able to extract
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` large number the carriers, the largest number
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` possible of carriers.
`
` Q So I'm not sure you said this, but -- in
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` other words, the transfer length is the horizontal 09:31AM
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` distance with reference to Figure 1 --
`
` A Yes.
`
` Q -- in the N-Plus and metal electrode
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` layers?
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` A It's -- maybe put it differently. 09:31AM
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` That is the minimum required overlap
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` distance between the source drain and gate electrode
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` in order to extract maximum of the carriers that
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` being accumulated within the channel.
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` Q Do most of the carriers pass from the 09:31AM
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` semiconductor layer to the -- to the N-Plus layer
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` through the transfer length?
`
` A Based on the experimental data, and based
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` on the simulations, that would be the case. That's
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` -- that's accepted knowledge, at least today, to the 09:32AM
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`Page 261
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` best -- to my best knowledge.
`
` Q So in Figure 1, most of the electrons would
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` pass -- or carriers would pass from -- or they would
`
` travel from the interface between the semiconductor
`
` layer four and the gate insulator, up to the N-Plus 09:32AM
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` and metal electrode layers at the transfer length,
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` mostly?
`
` A The most of this carriers will be confined
`
` for the extraction with the transfer length, yes;
`
` yes. But it's very difficult, as I'm discuss 09:32AM
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` yesterday, to control .2 micron overlap because of
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` the lithography requirements, because of the process
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` control, because of the edging.
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` Then if you have very good equipment,
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` edging -- for edging, if you have very good 09:33AM
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` equipment for lithography, then you can minimize
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` that overlap to one micron or .5 micron, that would
`
` be fantastic because that's -- it's enough.
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` But because of that difficulties, then it's
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` most of the engineers will try to give a little bit 09:33AM
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` of leeway, and they will go for the overlap between
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` source drain gate of two micron. But .2, .5 micron
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` is sufficient on the overlap.
`
` Q So in Figure 1, is it the case that not
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` many carriers will travel from the interface between 09:33AM
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`Page 262
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` the semiconductor layer and the gate insulator layer
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` to the metal electrode six and seven through the
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` regions of layers 5, 6, and 7 that are offset from
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` the gate electrode?
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` A Are they offset? You mean if they will be 09:34AM
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` outside of the etches of the gate electrodes?
`
` Q Right. So in Figure 1 --
`
` A Yes. Yes.
`
` Q -- the portions of the metal electrode
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` layer and the N-Plus layer that are not vertically 09:34AM
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` over --
`
` A Yes. Yes.
`
` Q -- the gate electrode?
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` A Most of the charge transfer would be
`
` confined within the transfer length, yes. At least 09:34AM
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` that is my understanding.
`
` Q Right. So in Figure 2, where would the
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` transfer length be measured?
`
` A It would be the same thing. There would be
`
` no difference between Figure 1 and Figure 2 from 09:35AM
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` transfer length point of view.
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` Q So it's that little length of the N-Plus
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` layer?
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` A Yes, you can say that. That's correct.
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` And then at that moment, the carriers, as 09:35AM
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` we just discussed, the difference between Figure 1
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` and 2 will be -- I would say the measure difference
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` that the carriers, when they are transferred, they
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` still have to travel along N-Plus before they reach
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` the metal. Then there will be some additional 09:35AM
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` resistance.
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` But that additional resistance will very
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` much depend, I would say, on the dimension of the
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` devices and the current density. Then if you have
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` at least different current densities, then the drop 09:35AM
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` voltage could be different within that N-Plus
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` region.
`
` Q How would you get a different current
`
` density?
`
` A Oh, if you change the gate bias. 09:35AM
`
` Q Okay. If the gate bias is the same --
`
` A Yeah.
`
` Q -- in Figure 1 and Figure 2, is the
`
` transfer length -- assuming the dimensions -- see
`
` the dimension L1 between the N-Plus layers -- 09:36AM
`
` A Yeah, yeah, yeah.
`
` Q -- in Figure 2?
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` Assuming that that dimension between the
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` N-Plus layers and the metal electrode layer in
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` Figure 1 is the same as L1, would the transfer 09:36AM
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` length in Figure 2 be the same -- in the same place
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` as in Figure 1?
`
` A Assuming everything equal; assuming that
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` amorphous silicon is same quality, assuming that the
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` gate insulator is the same quality, assuming that 09:36AM
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` all thickness is the same, assuming that the
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` geometry of the transistor channel length and width
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` is the same, then the transfer length for the
`
` Figure 2 and the Figure 1 would be very much the
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` same. It would be maybe -- could be some slight 09:36AM
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` difference for the Figure 2, but I don't -- I don't
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` believe it. We have to do experimental -- collect
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` experimental data to see it, but I don't believe it.
`
` I think the source drain contact resistance
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` for the Figure 1 and 2 would be very close for the 09:37AM
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` amorphous silicon transistor -- for the amorphous
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` silicon transistor. If it's different
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` semiconductor, what I said would be most likely not
`
` true.
`
` Q So in both Figure 1 and Figure 2 09:37AM
`
` structures, the path that the carriers would take
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` would be from the interface between the
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` semiconductor layer four and the gate insulator
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` three in the case of Figure 1 --
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` A Uh-huh. 09:37AM
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` Q -- or the semiconductor layer 14 and the
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` gate insulator 13 in Figure 2 along that interface,
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` up to the transfer length, which would be at the
`
` inner edges of the gap between the two N-Plus layer
`
` regions? 09:38AM
`
` A To simplify, I would say probably even our
`
` discussion, I would just say that transfer length
`
` for the Figure 1 and Figure 2 will take place where
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` you have overlap between source drain and gate, as
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` long as that overlap the same transfer length, the 09:38AM
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` carrier transfer will be the same.
`
` Q And Figure 2, the overlap, is with the
`
` N-Plus layer?
`
` A Yes; that's correct. That's correct.
`
` Q So moving the electrodes away from the 09:38AM
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` gate, so that they are not offset vertically with
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` the gate in Figure 2, does not affect the path that
`
` the carriers take from the gate insulator
`
` semiconductor interface up to the N-Plus layer, all
`
` dimensions being equal -- 09:38AM
`
` A Yes.
`
` Q -- and voltages and everything being equal?
`
` A Then assuming, as you said, that
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