SEL EXHIBIT NO. 2018
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
`
`

`

`‘Amorp
`
`hous &
`
`Volume II
`ials and DeVIce
`
`demy Kan
`
`Sem
`
`icondUcto‘r
`
`Mater
`
`kK;
`
`I' 7 Editor
`
`

`

`Amorphous and Microcrystalline
`Semiconductor Devices
`Volume II
`Materials and Device Physics
`
`Jerzy Kanicki, Editor
`
`Library
`
`ume I: Optoelectronic
`
`rume II: Materials and
`
`ry. and Devices,
`
`Perris-Prabhu
`
`Diagnostics, Edward B.
`
`Assurance,
`
`:d.
`
`Artech House
`Boston • London
`
`

`

`Ubrary of Congress Cataloglng-ln-PubUcation Data
`
`Amorphous and microcrystalline semiconductor devices : materials and
`device physics I Jerzy Kanicki.
`em.
`p.
`Includes bibliographical references and index.
`ISBN 0-89006-379-6
`1. Amorphous semiconductors. 2. Optoelectronics. I. Title.
`
`QC611.8.A5K36 1992
`537.6'22--dc20
`
`92-19374
`CIP
`
`<0 1992 ARTECH HOUSE, INC.
`685 Canton Street
`Norwood, MA 02062
`
`All rights reserved. Printed and bolUld in the United States of America. No part of this book may be
`reproduced or utilized in any form or by any means, electronic or mechanical, including photocopy(cid:173)
`ing, recording, or by any information storage and retrieval system, without permission in writing
`from the publisher.
`
`International Standard Book Number: 0-89006-379-6
`Ubrary of Congress Catalog Card Number: 92-19374
`
`10 9 8 7 6 s 4 3 2 1
`
`

`

`lmulation gate voltage
`dectostatic potential induced
`
`electostatic potential induced
`
`1ltage
`111e
`ne
`~ristic time for flat band (or
`1ld) voltage instability
`)n energy of r,
`
`roscopy
`
`r memory
`tructurc
`
`onductor
`
`effect transistor
`deposition
`
`Chapter 8
`Amorphous-Silicon Thin-Film Transistors:
`Physics and Properties
`C. van Berkel
`Philips Research Laboratories, Redhi/1, Surrey, UK
`
`Thin-film transistors (TFf) made with hydrogenated amorphous silicon (a-Si:H)
`represent an interesting field of study for several reasons. First, there is fundamental
`interest in amorphous silicon itself. Because in TFfs the Fermi level in the amor(cid:173)
`phous silicon can be controlled at will, they can be used as powerful tools to
`investigate various material properties, including density-of-states distribution,
`photoconductivity, mobility, and stability. Second, interest in a-Si:H TFfs receives
`commercial impetus because of application in liquid crystal displays, image sensors,
`and printer arrays. Finally, the device physics of a-Si:H shows many similarities
`but also striking differences, with established (c-Si) device physics, thus proving
`useful by throwing established concepts into relief and adding new insight.
`In this chapter we will discuss the application of a-Si:H TFfs, review theories
`and models that have been developed to describe the physics, and, finally, analyze
`in detail some special issues in the physics of a-Si:H TFfs.
`The first section of this chapter gives a brief outline of the main applications
`of a-Si:H TFfs: liquid crystal displays, printer arrays, and image sensors. We will
`then discuss the structure and some technological aspects of the transistors. This
`will be done with reference to standard devices, but a discussion of important
`topics, such as alternative structures and the choice of gate insulator, is also
`included. In the third section, the device theory is discussed. Because amorphous
`silicon is characterized by a continuous distribution of localized states in which the
`space charge resides and because the distribution of localized states is not necessarily
`given by a simple expression, solutions of a complete and self-contained theory
`can only be calculated numerically with the aid of a computer. Here, we will discuss
`instead a simple model first to establish basic concepts. These will then be used in
`a qualitative discussion of recent theoretical developments in the literature. Fol-
`
`397
`
`

`

`398
`
`lowing that, some issues in the device physics will be discussed in more detail; these
`include a review of the transistors as a spectroscopic tool to measure the density
`of states (DOS) in amorphous silicon and the physics of interface between amor(cid:173)
`phous silicon and silicon nitride. The following section deals with the device physics
`under nonequilibrium conditions, such as during transient switch-on and switch(cid:173)
`off and under illumination. Finally, the important and scientifically exciting subject
`of device stability is discussed in detail.
`
`8.1 APPLICATIONS
`
`Before discussing amorphous silicon TFTs in detail, it will be helpful to provide
`some understanding of the various applications of the transistors.
`The single most important application of a-Si:H TFTs is in active matrix
`addressing of liquid crystal displays (LCD). This application has received massive
`interest from many industrial laboratories [4] and has led to commercial products
`ranging from pocket televisions to compact video projection systems. The use of
`the active matrix allows the high information content required by video. Figure
`8.1 is a schematic diagram of the active matrix. The light transmission of the liquid
`
`0 View
`
`~direction
`
`cry
`tro
`the,
`tim
`ad<'
`ele'
`ren
`gat
`wit'
`but
`lim
`pas
`[5),
`[6-
`
`it c
`gla!
`
`this
`in t
`tra1
`cry!
`
`can
`tad
`cha
`vol1
`
`lines
`
`Pixel
`electrode
`
`Figure 8.1 Diagram of (typical) a-Si:H TFT active matrix display. Optical transmission of liquid crystal
`depends on voltage on pixel electrode. Each pixel can be charged individually by turning
`only transistors on one gate line, one at a time.
`
`Fig111
`
`

`

`scussed in more detail;
`tool to measure the
`of interface between
`deals with the device
`1sient switch-on and
`scientifically exciting
`
`it will be helpful to nrn''""~
`• transistors.
`H TFTs is in active
`ication has received massi'<'e
`led to commercial I-'1\JUUil:tl\
`1jection systems. The use
`t required by video.
`~ht transmission of the
`
`·ce
`s
`
`399
`
`crystal between the two glass plates is controlled by the voltage on the pixel elec(cid:173)
`trode. The transistors act as switches that pass the potential on the source lines to
`the drain pixel electrodes. By turning only the transistors on one gate line at a
`time, information can be passed to each pixel individually in a one line-at-a-time
`addressing mode. When the transistors in a gate line are switched off, the pixel
`electrodes are almost completely isolated from the source lines, and the information
`remains on the pixels throughout the frame time during which pixels on the other
`gate lines are addressed. With the active matrix, m x n pixels can be addressed
`with only m + n connections. This can also be achieved by direct multiplexing,
`but the nearly 100% duty ratio of the active matrix allows for many more picture
`Jines without loss of gray-scale capability, thus making display of television pictures
`possible. To date, up to 14-in diagonal television displays have been demonstrated
`[5], as have high-definition displays with more than 1,000 gate and source lines
`[6-8].
`Hydrogenated amorphous silicon is the preferred transistor material because
`it combines good electronic properties with the capability of being deposited on
`glass, thus keeping the important substrate costs low.
`Active matrix addressing can also be used in page-width printer heads. In
`this case the a-Si:H TFTs are used to address a linear array of output transducers
`in the same way as the two-dimensional displays discussed above [9]. A variety of
`tranducers can be used, such as a-Si:H high voltage transistors [10] and liquid
`crystal shutter arrays [11, 12].
`An application that combines the good photoconductors and transistors that
`can be made with a-Si:H are linear sensor arrays. In this application a-Si:H pho(cid:173)
`todiodes are used as transducers and the TFTs as switches to pass the voltage or
`charge on the photodiodes to the external circuits in very much the same way as
`voltage is multiplexed to the pixel elements in an active matrix display (Figure 8.2).
`
`Block 1
`
`2
`
`n-1
`
`n
`
`Photo diodes
`
`Gate lines G~ -18
`
`Data
`lines
`
`D,
`D2
`
`Dn-1
`Dn
`
`1
`
`lptical transmission of liquid
`be charged individually by turning
`
`Figure 8.2 Diagram of a-Si:H TFT/diode image sensor. Signal from array of photo-sensitive diodes is
`read out through 11 data lines in as many blocks, thus reducing number of external connections
`to twice the square root of number of diodes.
`
`

`

`400
`
`First proposed by Matsumura [13] and developed further by others [14-17], the
`advantage of TFfs is again to reduce the number of external connections while
`maintaining a maximum integration time. Also, a second set of transistors can be
`added to amplify the signal of the photodiode [18]. The large area-processing
`capability of a-Si:H allows the manufacture of sensors as large as the page to be
`scanned. This means that optics to reduce the image onto a much smaller sensor
`are not necessary; the a-Si:H sensor is in direct contact with the scanned page and
`is therefore called a contact type linear sensor [19].
`In all the applications discussed above, the transistor acts as a switch. Key
`performance parameters are therefore those that qualify the transistor to operate
`as an efficient switch. The on/off ratio must at least be larger than the number of
`lines in the matrix, with an on-current that provides sufficient pixel charging within
`the line time [20]. Also, the threshold voltage has to be small to allow low gate(cid:173)
`voltage driving levels. Other performance issues, like flicker and uniformity, place
`further demands on the transistor properties [20, 21]; however, a-Si:H TFTs are
`well able to satisfy these demands while also (thanks to the glass substrate) being
`cost effective.
`In the following we will look closely at the technology, structure, and physics
`of these transistors.
`
`8.2 DEVICE STRUCTURE
`
`8.2.1 Fabrication
`
`Since the first proposal by LeComber [22] to use a-Si:H TFfs for liquid crystal
`displays, much technological development and scientific investigation have taken
`place, and a-Si:H active matrix-addressed LCDs are now used in many consumer
`products. The basic transistor structure, however, has not changed much, and
`today's mainstream technology uses transistors that, apart from minor variations,
`are similar to the inverted staggered structures made in the early days [22, 23].
`Figure 8.3 illustrates two types of inverted staggered transistors that can be
`found in many of today's products [24]. They are called, for convenience, Type A
`and Type B, and differ in the order of deposition of n + contacts and top-passivation
`nitride [25]. The transistors are fabricated on a substrate of low alkaline glass using
`standard semiconductor processing techniques such as photolithographic patterning
`and etching. Typical dimensions of the transistors are a source-drain separation
`(channel length) of 8 J.tm, and an overlap between source/drain contacts and gate
`of 1 to 5 J.tm. Typical layer thicknesses for the various metal and semiconductor
`layers range from 500A to 5000A. The fabrication process of the transistor itself
`starts with the evaporation of (typically) Cr onto the substrate. This metal layer is
`then patterned by defining a photoresist pattern on the metal layer and etching
`away the metal outside the photoresist regions. The samples are then introduced
`
`(a)
`
`(b)
`
`Figure So:
`
`into th
`PECVJ
`such a!
`of a fev
`gas rae
`transisl
`amorpl
`reactot
`the re<
`
`

`

`(a)
`
`A-type
`
`Drain
`
`a-Si:H
`
`Source
`
`401
`
`Gate
`
`(b)
`
`B-type
`
`Drain
`
`a-Si:H
`
`Source
`
`Gate
`
`Figure 8.3 (a) Structure of A-type transistor in which gate insulator SiN, a-Si:H, and 11' are deposited
`in one vacuum pump-down. Top passivation layer (in this case SiN, but others like polyimide
`are also used) is deposited in a separate run. (b) Structure of B-type transistor in which
`gate insulator SiN. a-Si:H, and top passivation layer of SiN are deposited in one vacuum
`pump-down. The 11' is deposited in a separate run.
`
`into the plasma-enhanced chemical vapor deposition (PECVD) reactor. In the
`PECVD reactor source gases for the silicon nitride and amorphous silicon layers,
`such as silane (SiH4) and ammonia (NHJ), flow over the substrates at a pressure
`a few millitorr, and an RF-plasma is struck to decompose the gases. The resultant
`radicals then grow into a film on the substrates. In the fabrication of Type A
`transistors, the gate insulator silicon nitride, the active layer a-Si:H, and then+
`silicon for the contacts arc deposited consecutively in the PECVD
`reactor under continuous vacuum conditions. The samples are then taken out of
`the reactor and a metal layer (e.g., Cr or AI) is evaporated on the semiconductor
`
`hers [ 14-17], the
`:onnections while
`transistors can be
`! area-processing
`as the page to be
`ch smaller sensor
`;canned page and
`
`as a switch. Key
`1sistor to operate
`an the number of
`el charging within
`o allow low gate-
`uniformity, place
`a-Si:H TFTs are
`; substrate) being
`
`:ture, and physics
`
`for liquid crystal
`:ation have taken
`11 many consumer
`mged much, and
`minor variations,
`y days [22, 23).
`istors that can be
`venience, Type A
`1d top-passivation
`lkaline glass using
`~raphic patterning
`:-drain separation
`contacts and gate
`11d semiconductor
`1e transistor itself
`this metal layer is
`layer and etching
`e then introduced
`
`

`

`402
`
`layers. The transistor channel is then defined by etching away the top metal and
`n +. A peculiarity of this step is that the etch ant for the n + also etches into the
`amorphous silicon itself; etching must therefore be carefully timed to avoid remov(cid:173)
`ing the a-Si:H layer completely on the one hand while at the same time making
`sure that all of then+ is removed. In order to allow sufficient tolerance, a relatively
`thick ( ~0.3 J,tm) a-Si:H layer must be used.
`The disadvantage of a thick a-Si:H layer is that it makes the transistors
`relatively light sensitive. Using a thin layer ( ~ lOOA) of a-Si:H reduces this photo
`sensitivity substantially [26, 27); the transistor of Type B in Figure 8.3 illustrates
`a structure incorporating such a thin amorphous silicon layer. For this type of
`transistor a sequence of silicon nitride, amorphous silicon, and again silicon nitride
`is deposited in the first PECVD deposition run. The top silicon nitride is then
`patterned with an etch that does not attack a-Si:H, and the a-Si:H is then patterned
`with an etch that, in turn, does not attack the silicon nitride. The n+ is then
`deposited in a second PECVD deposition run. The thickness of the a-Si:H in the
`channel is now determined by the growth time of the a-Si:H in the PECVD reactor
`(rather than by the etching time) and can be controlled to much greater accuracy.
`The disadvantage of the B-type structure is that the a-Si:H and n + must be deposited
`in separate PECVD runs. Although a-Si:H has a relatively slow oxidation rate in
`air [28, 29), a thin oxide layer and impurities are thought to affect the interface
`between two layers deposited in separate growth runs; consequently, the two types
`of transistors are expected to have different characteristics [25].
`These two types of transistors form the basic structures in many of the appli(cid:173)
`cations of a-Si:H TFTs. Depending on each particular application, additional pro(cid:173)
`cess steps are needed to provide transparent pixel electrodes, storage capacitors,
`diodes, and so forth.
`
`8.2.2 Device Operation
`
`The basic device operation of both these transistors, as indeed of most other types
`too, is identical to that of the insulated gate field effect transistor (IGFET) or
`metal-oxide semiconductor field-effect transistor (MOSFET) [30]. A positive volt(cid:173)
`age applied to the gate will induce C;Viq electrons in the amorphous silicon. For
`small gate voltages, these electrons will be localized in the deep states of the
`amorphous silicon, but above a threshold voltage, a constant proportion of the
`induced electrons will be mobile, which means that the conductivity increases
`linearly with gate voltage; the transistor switches on, and a current flows between
`the source and drain. Then+ layers are necessary to reduce the contact resistance
`between contact metal and intrinsic amorphous silicon. Measurements have shown
`that, depending on the metal work function, a reduction of between 1.5 and 3.5
`orders of magnitude can be obtained [31]. Figure 8.4 shows the transfer charac(cid:173)
`teristic of a typical a-Si:H TFT.
`
`Figure 8.4 Tra
`cur
`0.6
`
`If a ne
`at the interf
`n+ contacts
`then+ laye1
`little practic
`of magnitud
`channel op<
`mechanisms
`This d
`the theory c
`will discuss •
`been investi
`
`8.2.3 Alte
`
`In the abov
`silicon, but
`second gate
`If both inte
`transistor. 1
`double-gate
`
`

`

`1y the top metal and
`also etches into the
`tmed to avoid remov(cid:173)
`te same time making
`olerance, a relatively
`
`takes the transistors
`H reduces this photo
`Figure 8.3 illustrates
`rer. For this type of
`:l again silicon nitride
`ilicon nitride is then
`li:H is then patterned
`·ide. The n+ is then
`i of the a-Si:H in the
`1 the PECVD reactor
`Jch greater accuracy.
`n + must be deposited
`low oxidation rate in
`) affect the interface
`uently, the two types
`~5].
`in many of the appli(cid:173)
`ltion, additional pro(cid:173)
`;, storage capacitors,
`
`:l of most other types
`ansistor (IGFET) or
`[30]. A positive volt(cid:173)
`torphous silicon. For
`e deep states of the
`nt proportion of the
`:mductivity increases
`urrent flows between
`he contact resistance
`uements have shown
`between 1.5 and 3.5
`. the transfer charac·
`
`403
`
`1.0
`
`lo IJA
`
`0.5
`
`w,L = 7.5
`dins= 4000A
`
`10"6
`
`10·8
`
`Io(A)
`
`10·10
`
`10·12
`
`-5
`
`0
`
`5
`VG (V)
`
`10
`
`15
`
`Figure 8.4 Transfer characteristics for typical A-type a-Si:H TFT. On/off ratio of 6 orders and linear
`current dependence above threshold voltage at 3.5V are obtained. Field-effect mobility is
`0.6 cm 2/V/S. From: [21 ].
`
`If a negative voltage is applied to the gate, hole accumulation will be induced
`at the interface. This hole channel is, however, not normally observed because the
`n+ contacts cannot supply enough holes to sustain a significant current; instead,
`the n + layers must be replaced with p + doped layers. Hole channel operation has
`little practical significance because the hole mobility in a-Si:H is nearly two orders
`of magnitude less than the electron mobility. But, as discussed in Section 8.6, hole
`channel operation has been extremely useful in identifying different instability
`mechanisms in a-Si: H.
`This describes the device operation in simple terms; in a following section
`the theory of device operation will be discussed further. Before that, however, we
`will discuss in more detail some other device structures and technologies that have
`been investigated.
`
`8.2.3 Alternative Structures
`
`In the above structures the channel is induced on one side only of the amorphous
`silicon, but, by putting an extra metal layer over the top passivating nitride, a
`second gate can be formed and a channel induced on the top side of the a-Si:H.
`If both interfaces are identical, this doubles the current-carrying capability of the
`transistor. Tuan and fellow investigators [32] were the first to manufacture such a
`double-gated transistor. They found that the source-drain current of the device
`
`

`

`404
`
`was higher than the sum of the currents through the individual channels obtained
`from single-mode operation, that is, from measurements in which only one of the
`gates is used while the other is kept at ground. Apparently the two channels interact
`to enhance the total current. This can be understood as follows. In dual gate mode
`the field lines originating from the gates cannot penetrate as deeply into the a-Si:H
`as they can in single gate mode because of the field from the opposite gate. This
`means that charge is distributed closer to the interface, and this increases the
`fraction of the total charge that is in the extended states. In other words, the
`threshold voltage of the transistor decreases, which enhances the current over and
`above the expected sum of the single-channel modes.
`A similar effect occurs if field lines are terminated on electrons in interface
`states rather than in bulk states. Indeed, the effect can be impressive. lbaraki [33]
`presented a double-gate transistor, shown in Figure 8.5, which has a bottom channel
`that is much inferior to the top channel (Figure 8.6). In double-channel mode,
`however, the total current increased to more than double the current of the top(cid:173)
`single-channel mode alone. The poor characteristics of the single bottom channel
`were ascribed to the large number of interface states, and this, in turn, was due
`to the fact that the deposition run was interrupted at this interface to allow for
`necessary patterning steps. Calculations with a model incorporating these surface
`states [33, 34] showed that, in dual-channel operation, the effect of these surface
`states is almost completely cancelled, creating two nearly equal channels. Thus,
`double-gate transistors result in a larger current-carrying capability and are useful
`as diagnostic tools for evaluation of interface states between a-Si:H and insulators.
`Whether these devices will be used in practice depends on the tradeoff between
`the first advantage and the extra cost of producing the second gate. To date, no
`double-gated devices are used in commercial products.
`
`Vs
`
`Vo
`
`SiNx
`
`a-Si
`
`Figure 8.5 Dual-gate TIT structure. A second gate is placed on top of silicon nitride; electron accu(cid:173)
`mulation layers can be induced on both sides of a-Si:H, doubling current through device.
`From [33).
`
`Figure 8.1
`
`Ar
`the dev
`length i
`niques r
`large ar,
`length b
`limit, th
`Now th<
`which, i
`channel.
`He
`the SOUl
`many fi<
`an elect
`be adde
`complicc
`
`

`

`dual channels obtained
`1 which only one of the
`1e two channels interact
`::>ws. In dual gate mode
`; deeply into the a-Si:H
`the opposite gate. This
`and this increases the
`s. In other words, the
`es the current over and
`
`n electrons in interface
`mpressive. Ibaraki [33]
`:h has a bottom channel
`double-channel mode,
`the current of the top(cid:173)
`single bottom channel
`I this, in turn, was due
`; interface to allow for
`rporating these surface
`effect of these surface
`equal channels. Thus,
`1pability and are useful
`1 a-Si:H and insulators.
`n the tradeoff between
`~ond gate. To date, no
`
`;ilicon nitride; electron accu(cid:173)
`>ling current through device.
`
`405
`
`1o· 4 r-----------------------------~
`
`Top- gate---
`
`0 -
`
`d=2oooA
`W/L = 12
`V0 = 15V
`
`10·12
`
`-10
`
`0
`VG (V)
`
`10
`
`20
`
`Figure 8.6 Transfer characteristic of dual-gate structure of Figure !\.5. On-current in dual-gate mode
`is more than sum of currents obtained in single-gate mode, illustrating interaction between
`top and bottom channel. From: [331.
`
`Another way to increase the current is by shortening the channel length of
`the device. In the horizontal structures discussed above, the minimum channel
`length is determined by the photolithographic patterning process. Special tech(cid:173)
`niques may be applied to achieve very short(< lJ.Lm) lengths [35], but over the
`large area necessary in displays and printers, it is difficult to reduce the channel
`length below the 10 J.Lm that is generally used. To overcome this photolithographic
`limit, the device structure can be turned 90 deg, as shown in Figure 8. 7 [36-39].
`Now the channel length is determined by the thickness of the spacing insulator,
`which, in turn, is determined by the growth time. Thi~ means that submicron
`channel lengths can be easily attained.
`However, as described by Okada [ 40], because the large horizontal area of
`the source and drain contacts relative to the thickness of the spacing insulator,
`many field lines from the drain will terminate on the back of the a-Si:H, creating
`an electron channel that results in a higher off current. Engineering features can
`be added to the structure to minimize these effects [ 41]; however, the result is a
`complicated structure that is costly to make.
`
`

`

`406
`
`a-Si: H
`
`Figure 8.7 Vertical TFT structure. Source and drain contacts are formed in horizontal layers, separated
`by spacer silicon nitride. Gate, insulator, and active layer lean against this pile of source,
`spacer, and drain.
`
`A different type of vertical transistor, similar to an MOS power device, was
`first proposed by Ichikawa [42] and later independently by Hack [43, 44]. In this
`structure, shown in Figure 8.8, the gate, source, and drain are all horizontal but
`the current flow is vertical. The function of the p+ layer is to minimize the off(cid:173)
`current. Without this layer, the edge of the source n + layer couples directly into
`the drain potential, resulting in a substantial off-current. The actual channel length
`in this device is a poorly defined quantity, because the bulk of the a-Si:H is not
`modulated by the gate, it represents a resistive component in the current path.
`The current distribution will therefore fan out around the edge of the p + and there
`will be a horizontal component to the effective channel length. A further qualifi(cid:173)
`cation on this device is that the source metal must be chosen to ensure that an
`effective Schottky barrier is formed for positive drain voltage [44]; for negative
`drain voltage, the transistor character is, of course, completely lost. This represents
`no difficulty in imaging or printing applications but would be a drawback for liquid(cid:173)
`crystal-related applications, which require an ac drive.
`We will now turn back to horizontal structures. To reduce cost and increase
`the chance of successfully making more than a million transistors over a large area,
`researchers can either try to make the device as simple as possible in the hope that
`a simple production process will reduce the chance of production-related errors,
`
`or
`sue
`
`rna
`giv
`pol
`is,
`a p
`an'
`
`alil
`gat
`tra
`swi
`US(
`tra
`[47
`
`of
`COl
`th~
`
`

`

`407
`
`Drain
`
`a-Si: H
`
`Source
`
`Figure 8.8 Vertical TFT structure. Source, drain, and gate are all formed in horizontal layers. Current
`flow is vertical. Emission of electrons from the source 11' contact into bulk a-Si: H, separating
`source and drain contacts, is modulated by gate voltage.
`
`or they can try to incorporate into the device features that will compensate for
`such errors and/or material liabilities.
`Le Contellec made a display with simple staggered transistors using just two
`masks [45]. The reduction from the standard four or five masks is achieved by
`giving up such luxuries as metal source lines and accepting the inconvenience of a
`potentially higher edge gate leakage current and crosstalk. The fabrication process
`is, however, very simple, and acceptable display performance can be achieved. In
`a process involving slightly more steps but still only two masks, Miyata developed
`an inverted staggered transistor (46] that showed good characteristics.
`The techniques used in these simple processes can also be used to make self(cid:173)
`aligned TFTs, in which case the primary aim is to reduce the overlap between the
`gate and source or drain contacts. This overlap adds extra capacitance to the
`transistor, which has a detrimental effect on the performance of the TFT as a
`switch. Self-aligned structures have minimal overlap because the gate pattern is
`used as a mask to define the contacts by exposing the photoresist through the
`transparent substrate. Both A- and B-type transistors can be made in this way
`(47-50].
`Even though two mask processes yield working displays, the trend for many
`of today's prototypes is toward more rather than fewer masks and, overall, a more
`complicated structure (24]. Apart from some notable exceptions (8], almost all of
`these transistors are classed as inverted staggered with a SiN/a-Si:H channel inter-
`
`Source
`
`::_j
`
`J
`
`10rizontallayers, separated
`against this pile of source,
`
`)S power device, was
`Hack (43, 44]. In this
`are all horizontal but
`i to minimize the off(cid:173)
`: couples directly into
`actual channel length
`k of the a-Si:H is not
`t in the current path.
`ge of the p + and there
`~th. A further qualifi(cid:173)
`sen to ensure that an
`age [44]; for negative
`:y lost. This represents
`a drawback for liquid-
`
`luce cost and increase
`tors over a large area,
`ssible in the hope that
`luction-related errors,
`
`

`

`408
`
`face, but they have other features that reduce the possibility of transistor failure.
`For example, a gate metal track of separately deposited and patterned Cr and AI
`will reduce the possibility of open lines as well as reducing line resistivity [51].
`Using a tantalum (Ta) alloy as gate line material also helps to substantially reduce
`line resistivity [52]. Furthermore, using double insulator layers of tantalum oxide
`and silicon nitride avoids the problem of pinholes in the nitride while still using
`the good interface properties of the silicon nitride/amorphous silicon interface [53].
`Also, the high dielectric constant of tantalum oxide is advantageous, as it allows
`for a smaller gate voltage. Indeed, there are many variations of the basic inverted
`staggered transistor [5, 7, 54-56], such as raising the number of masks to eight or
`even nine, thus including masks for transparent electrodes and bus lines.
`
`8.2.4 The Gate Insulator/Semiconductor Interface
`
`Finally we will look more closely at the important insulator/semiconductor inter(cid:173)
`face. The choice of insulator depends on the quality of the insulator and its com(cid:173)
`patibility with the a-Si:H processing technology. Silicon nitride meets these require(cid:173)
`ments because, when deposited with PECVD at a temperature close to that of the
`a-Si:H, it provides a good insulator. The inverted staggered structure incorporates
`the "silicon-on-nitride" [57] or "bottom nitride" [58] interface. When both silicon
`nitride and a-Si:H are deposited within one vacuum pump-down, this silicon-on(cid:173)
`nitride interface has the best properties within the class of possible combinations.
`Although the reverse interface (nitride-on-silicon) is preferable from a processing
`point of view (fewer masks), it has poorer electrical qualities [58] and therefore
`gives poorer transistor performance. The poorer interface quality is thought to be
`due to ion bombardment from the plasma during the deposition of the top silicon
`nitride. This bombardment is stronger for the top-nitride interface because of the
`higher power densities used in the deposition of nitride as compared with a-Si:H.
`Note that for the double-gated transistor in Figure 8.5, the nitride-on-silicon inter(cid:173)
`face was actually better than the silicon-on-nitride because the latter interface was
`not produced within a single vacuum pump-down. The composition of the silicon
`nitride is generally near stoichiometry (SiNu). Lustig [59] fabricated devices with
`overstoichiometric nitride (SiN Lo) grown at temperatures between 2500C and 450°C,
`which had better device performance than devices with understoichiometric (SiN 1.2)
`nitride.
`Transistors with low-temperature silicon oxide, whether deposited by plasma(cid:173)
`enhanced CVD or grown in an anodic oxidation process, have not been reported
`extensively, but it is generally accepted that the prethreshold slope of these devices
`is low, giving a high threshold voltage. Recent evidence suggests that a low prethres(cid:173)
`hold slope is inherent in the oxide/a-Si:H interface [60]. The insulator properties
`of the low-temperature oxide are also generally poor.
`Silicon oxide is alluring, however, because of the superior and proven quality
`of thermal (high-temperature) silicon oxide in c-Si technology. But temperatures
`
`in the
`a-Si:H
`and co•
`sample
`162] th2'
`the oxi.
`to mak
`deposit,
`a stabl<
`chemic
`of the 1
`
`8.3 T
`
`In the I
`of the
`the DC
`66], fol
`lr
`ex pone
`above ·
`The d'
`handga
`F
`actual ·
`
`Figure 8.
`
`

`

`· of transistor failure.
`patterned Cr and AI
`~ line resistivity [51].
`) substantially reduce
`~rs of tantalum oxide
`tride while still using
`silicon interface [53].
`1tageous, as it allows
`. of the basic inverted
`r of masks to eight or
`nd bus lines.
`
`/semiconductor inter(cid:173)
`nsulator and its com(cid:173)
`e meets these require(cid:173)
`re close to that of the
`;tructure incorporates
`~e. When both silicon
`down, this silicon-on(cid:173)
`ossible combinations.
`ble from a processing
`es [58] and therefore
`Jality is thought to be
`tion of the top silicon
`:erface because of the
`ompared with a-