SEL EXHIBIT NO. 2017
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
`
`

`

`Japanese Journal of Applied Physics
`Vol. 47, No. 5, 2008, pp. 3362–3367
`#2008 The Japan Society of Applied Physics
`
`Advanced Multilayer Amorphous Silicon Thin-Film Transistor Structure:
`Film Thickness Effect on Its Electrical Performance and Contact Resistance
`
`
`Alex KUO, Tae Kyung WON1, and Jerzy KANICKI
`
`Organic and Molecular Electronic Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan,
`Ann Arbor, MI 48109, U.S.A.
`1Applied Komatsu Technology America Inc., Santa Clara, CA 95054, U.S.A.
`
`(Received December 4, 2007; accepted February 4, 2008; published online May 16, 2008)
`
`We report the intrinsic and extrinsic electrical characteristics of advanced multilayer amorphous silicon (a-Si:H) thin-film
`transistor (TFT) with dual amorphous silicon nitride (a-SiNX:H) and a-Si:H layers. The thickness effect of the high electronic
`quality a-Si:H film on the transistor’s electrical property was investigated; with increasing film thickness, both field-effect
`mobility and subthreshold swing show improvement and the threshold voltage remain unchanged. However, the contact
`resistance increases with the a-Si:H film thickness. Using the two-step plasma enhanced chemical vapor deposition process,
`we fabricated TFT’s with acceptable field-effect mobility (1 cm2 V1 s1) and threshold voltage (<1:5 V) with enhanced
`throughput.
`[DOI: 10.1143/JJAP.47.3362]
`KEYWORDS: amorphous silicon thin-film transistor, dual layer, thickness effect, contact resistance
`
`1.
`
`Introduction
`
`As the active-matrix liquid crystal display (AM-LCD)
`industry begins to introduce large-size and high-pixel-
`density displays,
`the demand for a high performance
`amorphous silicon thin-film transistor mounts. In order for
`the hydrogenated amorphous silicon (a-Si:H)
`thin-film
`transistor (TFT) to remain competitive in the flat-panel
`display industry, it is necessary to realize transistors with a
`high field-effect mobility and a low threshold voltage while
`being able to be fabricated at a high deposition rate.1) These
`qualities allow the possibility of manufacturing large dis-
`plays with low power consumption at relatively low costs.
`Fabricating high performance a-Si:H TFT requires a high
`electronic quality a-Si:H film, as the electrical characteristics
`of a TFT is intimately related the electronic quality of the
`a-Si:H film.2) Even though a high electronic quality film can
`be achieved by lowering its plasma-enhanced chemical
`vapor deposition (PECVD) rate, doing so increases the
`overall device fabrication time. In the AM-LCD industry,
`the inverted staggered back-channel-etched type transistor
`structure is preferred over
`the tri-layer
`type transistor
`structure because of its reduced photolithography steps and
`improved source/drain contact quality.3) This structure
`requires the deposition of a thicker amorphous silicon film
`for better control of the back channel etch step.4) However,
`a thicker amorphous silicon film for TFT means longer
`deposition time, which also leads to a lower production
`output and higher overall costs for the AM-LCD industry.5)
`The PECVD time can be shortened by increasing the
`deposition rate of the film, but doing so degrades the
`mobility and threshold voltage of the transistor.6) Similarly,
`the gate insulator amorphous silicon nitride (a-SiNX:H)
`should exceed 4000 A˚ to reduce the gate leakage. Also its
`PECVD rate needs to be low in order for the a-Si:H TFT to
`have a high electronic quality a-SiNX:H/a-Si:H interface for
`optimum threshold voltage, subthreshold swing, and elec-
`trical stability.7) It is therefore desirable to search for a
`compromise between device electrical performance and
`production throughput by depositing thick a-SiNX:H and a-
`
`
`E-mail address: kanicki@eecs.umich.edu
`
`Si:H films in the shortest possible time without degrading
`the overall electrical characteristics of the a-Si:H TFT. One
`potential solution is depositing two amorphous silicon films
`as the active layers of the TFT: a thin layer of a low
`deposition rate film near the gate insulator interface in order
`to obtain high electronic quality a-Si:H film near the electron
`conduction channel, and a thick layer of high deposition rate
`film in the back channel to be used as the sacrificial layer
`during the etch back process. The a-SiNX:H deposition is
`also separated into a two-step process: a thin layer of low
`deposition rate film near the high electronic quality a-Si:H
`film for optimum electrical performance and stability, and a
`thick layer of high deposition rate film near the gate metal to
`reduce gate leakage current.
`The concept of double a-Si:H layer structure for TFT
`was first proposed by Takeuchi and Katoh for the purpose
`of reducing a-Si:H TFT photo-response.8,9) Characteristic
`of dual amorphous silicon TFT was explored further by
`Kashiro et al., and it was concluded that the field-effect
`mobility is highly sensitive, and linearly proportional (up to
`15 nm), to the thickness of the high electronic quality a-Si:H
`layer.10) A reduction in the thickness of the high quality film
`allows the defect states from the low quality film to interfere
`with the band bending at the a-SiNX:H/a-Si:H interface,
`which causes the TFT’s mobility to decrease. Tsai et al.
`investigated the effect of a low electronic quality film
`deposition rate on the overall electrical performance of the
`a-Si:H TFT.11) and concluded that with the increasing
`deposition rate the TFT’s field-effect mobility decreases for
`the same reasoning as proposed by Kashiro. From these
`results it is clear that dual a-Si:H layer TFT’s electrical
`performance can suffer due to the inclusion of the low
`quality film away from the a-SiNX:H/a-Si:H interface.
`However, previous studies report only on the extrinsic
`characteristics of the a-Si:H TFT, which do not take source/
`drain contact resistances into consideration; yet it is well
`known that the presence of significant contact resistance
`can mask the true electrical characteristics, or the intrinsic
`characteristics, of an a-Si:H TFT.12) Moreover it is not clear
`how the film thickness of a high quality a-Si:H affects the
`intrinsic and extrinsic properties of the advanced multilayer
`a-Si:H TFT structure. Our present work analyzes in some
`
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`

`Jpn. J. Appl. Phys., Vol. 47, No. 5 (2008)
`
`A. KUO et al.
`
`Table I. A1 and A2 a-Si:H film thicknesses of the substrates used in this
`study.
`
`Plate ID
`
`Var-1
`
`Var-2
`
`Var-3
`
`Var-4
`
`Var-5
`
`Var-6
`
`tA1
`(A)
`
`100
`
`200
`
`300
`
`400
`
`500
`
`600
`
`tA2 (A)
`
`As deposited
`
`Channel region
`
`1600
`
`1500
`
`1400
`
`1300
`
`1200
`
`1100
`
`900
`
`800
`
`700
`
`600
`
`500
`
`400
`
`on as tA1 and tA2 respectively. It is important for readers to
`remember that the tA2 values presented are the deposited
`thicknesses, not the final A2 thicknesses in the channel
`region of the TFTs after the back channel etch. Electrical
`measurements were conducted using HP 4156 at the room
`temperature, and the detail of experimental techniques has
`been discussed elsewhere.13)
`
`3. Parameter Extraction Methodology
`
`Since the goal of this study focuses on the change in a-
`Si:H TFT performance with respect to tA1, it is imperative
`that we develop accurate parameter extraction techniques
`that represent the true TFT electrical behaviors. Changes
`observed, if any, should be solely due to the differences
`caused by electrical properties change originating from
`varying tA1, not artificial effects contributed by the param-
`eter extraction method. We use two different methods of
`extrinsic parameter extraction, which does not take contact
`resistance of a-Si:H TFT into consideration, to minimize
`linear15,16) and
`the possibility of
`introducing artifacts:
`conductance17) methods. When extracting the a-Si:H TFT
`parameter via the linear method, a line fits the experimental
`data points of the ID–VGS, or transfer, characteristic in the
`linear regime (Fig. 2) or the I1=2
`D –VGS characteristic in the
`saturation regime (Fig. 3); the data range selected is between
`10 – 90% of the maximum drain current. The fitting line
`represents metal–oxide–semiconductor field-effect transistor
`(MOSFET) square law equations:
`
`
`ID-LIN ¼ W
`CINSFE1-LINðVGS VT1-LINÞVDS-LIN;
`L
`1=2ðVGS VT1-SATÞ;
`D-SAT ¼ W
`I1=2
`2L
`
`ð1Þ
`
`ð2Þ
`
`CINSFE1-SAT
`
`details the advanced multilayer a-Si:H TFT with dual a-Si:H
`and dual a-SiNX:H layers. We extract the electrical behav-
`iors of the a-Si:H TFT and analyze the effect of a high
`quality amorphous silicon film thickness on the overall
`transistor performance by evaluating its
`intrinsic and
`extrinsic electrical characteristics. Based on our experimen-
`tal results, we can i) quantify the effect of a high electronic
`quality a-Si:H thickness on the transistor’s field-effect
`mobility, threshold voltage, subthreshold swing, and contact
`resistance, and ii) identify a minimum thickness of a high
`electronic quality a-Si:H layer required for the TFT to
`exhibit promising device electrical performance without
`unnecessarily extending the PECVD time. To our best
`knowledge this study is the first full analysis on the thickness
`effect of a high electronic quality amorphous silicon film,
`which include both the intrinsic and extrinsic properties
`of the transistor, on the dual a-Si:H and a-SiNX:H layers
`transistors.
`
`2. Experimental Methods
`
`We fabricated back channel etched type inverted stag-
`gered transistor13) with patterned chromium gate (2000 A˚
`thick) consisting of two layers of a-SiNX:H and two layers
`of a-Si:H (Fig. 1): PECVD was used to deposit 3500 A˚ of
`nitrogen-rich hydrogenated a-SiNX:H at 1800 A˚ /min (G2),
`500 A˚ of a-SiNX:H deposited at 1000 A˚ /min (G1), 100 –
`600 A˚ of a-Si:H deposited at 600 A˚ /min (A1), 1100 –1600
`A˚ of a-Si:H deposited at 1200 A˚ /min (A2), and 700 A˚ of
`phosphorous doped amorphous silicon (n+ a-Si:H). The
`active island was dry-etched (SF6 : Cl2 : O2 : He in 6 : 24 :
`20 : 5 ratio) using a LAM 9400 TCP-RIE. Source and drain
`metallization includes the deposition and definition of
`sputtered molybdenum. Since the phosphorous from the
`n+ layer diffuses into the amorphous silicon film in the back
`channel etch TFT, it is necessary to perform dry over-etch to
`remove a fraction of the amorphous silicon film in order to
`reduce the leakage current between the source and drain;14)
`we dry-etched (HBr : Cl2 in 1 : 1 ratio) 700 A˚ of A2 in the
`channel region of the transistor using the LAM 9400 TCP-
`RIE. All patterning steps were performed using contact
`photolithography via a MA-6 mask aligner. The bi-layer a-
`SiNX:H surface roughness (RMS value) above the gate
`dielectric is about 1.1 nm. Both films have slightly different
`film stoichiometry, but are both N-rich (N=Si > 1:3); the Si–
`H content in the gate dielectric deposited at the lower rate is
`rather small (<0:5%). Total hydrogen content in the silicon
`nitride deposited at the higher rate (36  4%) is signifi-
`cantly larger in comparison to the film deposited at the lower
`rate (28:5  1:5%). The Tauc optical gap for the film
`deposited at higher and lower rates is about 4.6 and 5.2 eV,
`respectively. Table I shows the plates fabricated with
`different A1 and A2 a-Si:H thicknesses, denoted from here
`
`n+ a-Si:H
`G1 a-SiNx:H
`G2 a-SiNx:H
`
`Mo
`
`A2 a-Si:H
`A1 a-Si:H
`
`Cr
`
`Substrate
`
`Fig. 1.
`work.
`
`(Color online) Schematic cross-section of a-Si:H TFT used in this
`
`where W, L, and CINS symbolize the a-Si:H TFT channel
`width, length, and gate insulator capacitance, respectively.
`Field-effect mobility values in the linear and saturation
`regime are denoted as FE1-LIN and FE1-SAT; similarly
`threshold voltage values in each regime of operation are
`represented by VT1-LIN and VT1-SAT. The symbols VGS and
`VDS-LIN are the gate and drain biases with respect to the
`source terminal of the TFT. From the equations above it is
`clear that from the slope of the fitting line to the transfer
`characteristic we can extract the field-effect mobility values,
`and the x-intercept yields the threshold voltage.
`The second method of parameter extraction is based on
`the conductance of the a-Si:H TFT. We begin by defining
`the linear regime channel conductance (CH-LIN) of the
`device from the square law current equation:
`
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`
`

`

`Jpn. J. Appl. Phys., Vol. 47, No. 5 (2008)
`
`A. KUO et al.
`
`1/2 (10-3 A1/2)
`
`ID-SAT
`
`1/2 (10-3 A1/2)
`
`ID-SAT
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0.0
`
`1.5
`
`1.0
`
`0.5
`
`W/L=116/96
`VDS=VGS
`
`tA1
`
`tA1 a-Si:H = 300Å
`W/L=116/96
`VDS=VGS
`S-1
`
` ∝ μFE1-SAT
`
`90%
`
`10%
`
`VT1-SAT
`
`10-5
`
`10-6
`
`10-7
`
`10-8
`
`10-9
`10-5
`
`10-6
`
`10-7
`
`10-8
`
`10-9
`
`|ID-SAT| (A)
`
`|ID-SAT| (A)
`
`ID-LIN (nA)
`
`ID-LIN (nA)
`
`-2)
`
`30
`
`20
`
`01
`
`0
`
`30
`
`20
`
`0
`
`10-8
`
`W/L=116/96
`VDS=0.1V
`
`tA1
`
`tA1 a-Si:H = 300Å
`W/L=116/96
`VDS=0.1V
`
`S-1
`
`90%
`
` μFE1-LIN
`
`VT1-LIN
`
`10%
`
`10-10
`
`10-12
`
`ID-LIN (A)
`
`10-14
`10-8
`
`10-10
`
`10-12
`
`ID-LIN (A)
`
`-1)
`
`-2)
`
`2 (10-9 S VGS
`
`δ2σCH-SAT / δVGS
`
`0.0
`
`10
`
`5
`
`0
`20
`
`20
`
`15
`
`10
`
`tA1 a-Si:H = 300Å
`W/L=116/96
`VDS=VGS
`VT2-SAT
`
` ∝ μFE2-SAT
`
`-5
`
`0
`
`10
`
`15
`
`5
`VGS (V)
`
`05
`
`-10
`
`-1)
`
`CH-SAT / δVGS (10-9 S VGS
`
`δσ
`
`Fig. 3. Saturation regime transfer characteristics of the a-Si:H TFTs with
`different A1 and A2 a-Si:H thicknesses (top). Experimental data points
`are intentionally displayed as thin lines to show the variations among
`different transistors. Demonstration of the parameter extraction using the
`linear method for TFTs with tA1 of 300 A˚ : figures represent data points
`collected and lines represent fitting equations. Demonstration of the
`parameter
`extraction using the
`conductance method:
`calculated
`CH-SAT=VGS and 2CH-SAT=V 2
`GS curves for TFTs (bottom) used in
`this experiment.
`
`2 (10-9 S VGS
`
`CH-LIN / δVGS
`
`δ2σ
`
`01
`
`10
`
`5
`
`0
`20
`
`10-14
`20
`
`15
`
`10
`
`tA1 a-Si:H = 300Å
`W/L=116/96
`VDS=0.1V
`VT2-LIN
`
` μFE2-LIN
`
`-5
`
`0
`
`10
`
`15
`
`5
`VGS (V)
`
`05
`
`-10
`
`CH-LIN / δVGS (1x10-9 S VGS
`
`δσ
`
`Fig. 2. Linear regime transfer characteristics of the a-Si:H TFTs with
`different A1 and A2 a-Si:H thicknesses (top). Experimental data points
`are intentionally displayed as thin lines to show the variations among
`different transistors. Demonstration of the parameter extraction using the
`linear method for TFTs with tA1 of 300 A˚
`is also included: figures
`represent data points collected and lines represent fitting equations.
`Demonstration of the parameter extraction using the conductance method:
`calculated CH-LIN=VGS and 2CH-LIN=V 2
`GS curves for TFTs (bottom)
`used in this experiment.
`
`ð3Þ
`ð4Þ
`
`ID-LIN ¼ W
`CINSFE2-LINðVGS VT1-LINÞVDS-LIN;
`L
`CH-LIN  ID-LIN
`¼ W
`CINSFE2-LINðVGS VT1-LINÞ;
`VDS-LIN
`L
`where FE2-LIN is the linear regime field-effect mobility. To
`obtain the field-effect mobility we take derivative of the
`channel conductance with respect to the gate bias (Fig. 2):
`¼ W
`ð5Þ
`L
`
`CH-LIN
`VGS
`
`CINSFE2-LIN:
`
`we incorporate a physical origin to the threshold voltage
`parameter as the specific point where the maximum change
`in channel conductance with gate bias occurs.
`Field-effect mobility extraction in the saturation regime
`(FE2-SAT) also begins with the square law current equation:
`ID-SAT ¼ W
`CINSFE2-SATðVGS VT1-SATÞ2:
`ð6Þ
`2L
`Since VDS-SAT ¼ VGS VT1-SAT and dVDS-SAT ¼ dVGS, the
`channel conductance in the saturation regime is
`CH-SAT  ID-SAT
`¼ W
`CINSFE2-SATðVGS VT-SATÞ;
`VDS-SAT
`L
`
`ð7Þ
`
`and the change in channel conductance with respect to the
`gate bias is
`
`CH-SAT
`VGS
`
`¼ W
`L
`
`CINSFE2-SAT:
`
`ð8Þ
`
`Figure 3 shows the extractions of field-effect mobility from
`the CH-SAT=VGS plot and threshold voltage (VT2-SAT) from
`
`It should be clarified that two separate field effect mobility
`notations are used for the same square law equation to
`distinguish the difference in extraction method: FE1-LIN in
`eq. (1) is a constant value with respect to VGS and FE2-LIN
`from eq. (5) varies with gate bias. Threshold voltage
`extraction from the conductance method (VT2-LIN) is done
`by taking derivative of eq. (5) with respect to VGS, and
`defining the maximum value as the threshold voltage. This
`choice is based on the fact that channel conductance changes
`with gate bias, as shown in Fig. 2. By defining threshold
`voltage as the maximum value on the 2CH-LIN=V 2
`GS plot,
`3364
`
`

`

`Jpn. J. Appl. Phys., Vol. 47, No. 5 (2008)
`
`A. KUO et al.
`
`μFE1-SAT
`
`VT1-LIN
`
`VT2-LIN
`
`0
`
`ΔL (μm)
`
`024681
`
`VDS=0.1V
`
`VDS=VGS
`
`RC(VGS=5V)
`
`RC(VGS=10V)
`
`RO
`500
`
`600
`
`1.2
`
`1.1
`
`1.0
`
`0.9
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0.0
`
`W/L=116/96
`
`μ
`i
`
`μFE2-SAT
`μFE2-LIN
`
`μFE1-LIN
`VT1-SAT
`
`VT-i
`
`VT2-SAT
`
`-0.5
`0.55
`
`0.50
`
`0.45
`
`0.40
`3.0
`
`2.5
`
`2.0
`
`1.5
`
`1.0
`
`0.5
`
`0.0
`
`100
`
`200
`
`400
`300
`tA1 (A)
`
`μ (cm2V-1sec-1)
`
`VT (V)
`
`S (V/dec)
`
`R (MΩ)
`
`Intrinsic mobility and threshold voltage, and linear and saturation
`Fig. 6.
`regimes field-effect mobility,
`threshold voltage, subthreshold swing,
`contact resistances, and channel length deviation values for a-Si:H TFTs
`with different A1 thicknesses investigated in this work.
`
`lity, and intrinsic threshold voltage, respectively. From
`Fig. 4, we can obtain the values of rCHðVGSÞ and RCðVGSÞ for
`a given gate voltage from the slope and the y-intercept,
`respectively, of a fitted line for the total resistances of the
`transistors with different channel lengths. The minimum
`length
`contact resistance (R0) and the effective channel
`change ( L) are extracted from the intersection of all the RT
`fitted lines. Channel conductivity, SCHðVGSÞ, is equal to the
`inverse value of the channel resistivity. One point worth
`noting is that due to the geometry of the TFT near its source
`and drain contacts, the actual transistor channel length is not
`the masked channel length L, but L þ L. From plotting the
`channel conductance values with respect to the gate bias,
`and performing a linear fit to the data points, we can extract
`the intrinsic mobility and threshold voltage values respec-
`tively from the slope and the x-intercept of the best-fit line
`(Fig. 5).
`
`4. Results and Discussion
`
`From the linear regime transfer characteristics of the a-
`Si:H TFTs shown in Fig. 2 (top), there is a slight increase in
`drain current with tA1. The same trend can be seen from the
`saturation regime transfer characteristics from Fig. 3 (top).
`Changes in extrinsic threshold voltage and subthreshold
`swing, however, are inconspicuous from observing the I–V
`characteristics. Figure 4 shows the values of RCðVGSÞ, R0,
`SCHðVGSÞ, and L of the a-Si:H TFT with tA1 300 A˚ . Both
`
`VGS=5V
`
`2RC(VGS)
`
`tA1=300Å
`VDS=0.1V
`W=116μm
`(-2ΔL, 2RO)=
`(-15.23, 0.216)
`
`15
`
`10
`
`5
`
`RTotal (MΩ)
`
`20V
`
`0
`-50
`
`50
`0
`Channel Length (μm)
`(Color online) Example of the RTOTAL, rCH, RCðVGSÞ, R0, and L
`Fig. 4.
`values extraction using TLM.
`
`100
`
`VDS=0.1V
`W=116μm
`
`μi = 1.16
`
`VTi = 1.12V
`
`tA1 a-Si:H=
` 100Å
` 300Å
` 600Å
`
`01234
`
`SCH (10-9 S-cm)
`
`0
`
`5
`
`15
`
`20
`
`10
`VGS (V)
`Fig. 5. Extraction of a-Si:H TFTs (tA1 ¼ 100, 300, 600 A˚ ) intrinsic
`mobility and threshold voltage by using channel conductivity versus gate
`voltage plot: symbols and lines represent experimental data and the best-
`fit line, respectively. Values of intrinsic mobility and threshold voltage
`shown belong to TFT with tA1 of 600 A˚ .
`
`the 2CH-SAT=V 2
`GS plot. Both FE2-LIN and FE2-SAT values
`are extracted from the conductance curves at the maximum
`conductance value; in both cases maximum values occur at
`VGS ¼ 20 V. Subthreshold swings for the linear and satu-
`ration regimes of operation are defined as the inverse values
`of the steepest slopes of the respective ID–VGS semi-log
`plots.
`For the intrinsic parameter extraction, we use the trans-
`mission line method (TLM) described by Kanicki et al.18)
`Detail description of the method will not be repeated here;
`instead we show examples of the data obtained by utilizing
`TLM in Figs. 4 and 5, plus the equation for total resistance
`(RT) of a-Si:H TFT during the linear regime of operation:18)
`RT ¼ VDS
`ID¼ rCHðVGSÞL þ 2RCðVGSÞ
`WiCINSðVGS VT-iÞ þ 2RCðVGSÞ:
`¼
`In eq. (9) rCHðVGSÞ, RCðVGSÞ, i, and VT-i represent the
`channel resistivity, total contact resistance, intrinsic mobi-
`
`ð9Þ
`
`L
`
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`

`Jpn. J. Appl. Phys., Vol. 47, No. 5 (2008)
`
`A. KUO et al.
`
`threshold voltage remains about the same with change in tA1.
`Subthreshold swing values, in both regimes of operation,
`decrease by 10% with increasing tA1; the decrease, however,
`saturates between 300 to 500 A˚ . Since S is a function of both
`a-Si:H bulk states and a-SiNX:H/a-Si:H interface states, and
`we assume that TFT with different tA1 values have identical
`interface states density (NSS), the lowering of S with the
`increasing tA1 originates from a decrease in neutrally
`charged deep-gap state density (Nbs) in the amorphous
`silicon bulk.20) From the subthreshold equation derived by
`
`Rolland et al.,21)
`q logðeÞ 1 þ qxi
`S ¼ kTMEAS
`
`
`
`þ qNssÞ
`
`;
`
`ð10Þ
`
`ffiffiffiffiffiffiffiffiffiffiffi
`
`"sNbs
`
`p
`
`ð
`
`"i
`
`channel resistivity and contact resistance values decrease as
`VGS increases. Figure 5 shows the channel conductivity plots
`and the values of the intrinsic mobility and threshold voltage
`for the TFTs with tA1 of 100, 300, and 600 A˚ . Summary of
`the results for the TFT extrinsic and intrinsic extractions are
`shown in Fig. 6.
`We can make five important observation regarding the
`influence of amorphous silicon thickness on the performance
`of the TFT: i) both linear and saturation regime field-effect
`mobility values increase linearly by 5 – 9%, depending on
`the extraction method, when tA1 increases from 100 to
`300 A˚ , and remains the same beyond that
`thickness,
`ii)
`a-Si:H thickness has a different effect on the threshold
`voltage, which depends on the extraction method,
`iii)
`subthreshold swing decreases with the increasing tA1, iv)
`the contact resistance does change with tA1, but such change
`depends on the applied gate bias, and v) L increases from
`6.5 to 10 mm with the increasing tA1.
`Firstly we address the 5 – 9% increase in the field-effect
`mobility. The increase is observed repeatedly and falls
`within the standard deviation value of our measurement
`(2%). This means that as tA1 increases from 100 to 600 A˚ ,
`the short range order of the amorphous silicon film increases,
`and the width of the band-tail states along the electron
`conduction channel of the transistor decreases.3) The effect
`of this trend has been studied in single layer a-Si:H TFTs;
`there is a lowering in field-effect mobility with the
`increasing film deposition rate caused by the increasing
`formation of the Si–H2 bonds versus the ideal Si–H or Si–Si
`tetrahedral a-Si:H bonds.19) Non-ideal bondings, such as the
`Si–H2 bonds or a large concentration of Si–H bonds, distort
`the short range order of the amorphous silicon lattice (e.g.,
`disorder is enhanced), thus leading to a lower field-effect
`mobility. We expect our A1 film to have a slightly higher
`density and lower content of the Si:H bonds, or a lower total
`hydrogen content than the A2 film because of its lower
`deposition rate; the Tauc gap for the A1 a-Si:H film is about
`1:8  0:1 eV. Also the film stress of the A1 a-Si:H film is
`lower in comparison to the A2 a-Si:H film, promoting better
`short range ordering near the interface. Indeed, according
`to the FTIR peak of the Si–H bond, the full-width at half-
`maximum (FWHM) values are 94 and 98 cm1 for the
`A1 and A2 films, respectively. The Urbach edge value for
`such film is about 90  10 meV. This explains the improve-
`ment
`in field-effect mobility that
`is associated with the
`increasing tA1. Moreover, the increase saturates at about
`300 A˚ , which suggests that
`the electron conduction is
`confined within that thickness because further increase in
`tA1 does not lead to higher TFT field-effect mobility; this is
`consistent with the channel thickness value reported pre-
`viously for single layer a-Si:H TFTs.
`The values and trend of the threshold voltage change with
`to tA1 varies with different extraction methods.
`respect
`Using the linear method, the extrinsic threshold voltage
`increases by 0.08 V as tA1 increase from 100 to 600 A˚ ; the
`same percentage of increase can be observed in the intrinsic
`voltage extraction. However, when using the conductance
`method, there is a decrease in the threshold voltage by
`0.12 V. More importantly these slight changes are close to
`the standard deviation value (0.1 V) of three measurements.
`Therefore, based on our observation we conclude that the
`
`and assuming a constant interface state density for all a-Si:H
`TFTs, we can calculate the decrease in effective bulk state
`density from the decrease in subthreshold swing values with
`tA1. Based on the measured S values in the linear regime for
`TFTs with different tA1, for Nss of 1  1011 cm2 eV1, the
`effective Nbs changes from 9.5 to 7:7  1018 cm3 eV1,
`while using the saturation regime S values, Nbs decreases
`from 5.7 to 4:3  1018 cm3 eV1; for Nss of 1  1012
`cm2 eV1, the Nbs changes from 9.3 to 7:5  1018 cm3
`eV1 for the linear regime and 5.6 to 4:2  1018 cm3 eV1
`for the saturation regime S values.
`At a low gate voltage (VGS ¼ 5 V), the contact resistance
`increases with tA1. As VGS increases to 10 V, the contact
`resistance is invariant to tA1 and maintains a mean value of
`0.67 M
`. However, minimum contact resistance R0 decreas-
`es with tA1 from 0.11 to 0.02 M
`. To analyze the above
`observations we will discuss the change in RCðVGSÞ and R0
`based on the a-Si:H bulk and junction resistances of the
`TFT: contact resistance is the sum of the a-Si:H bulk
`resistance and the a-Si:H/n+ a-Si:H/Mo junction resistance.
`It is well known that an amorphous silicon deposited at a
`higher rate, therefore containing larger density of deep-gap
`states, has a higher dark conductivity than a-Si:H films
`deposited at a lower rate.22) This indicates that film A1 has a
`higher bulk resistivity than A2 due to its lower deposition
`rate. All the TFTs fabricated in this study have the same
`overall a-Si:H thickness of 1700 A˚ ; transistors made on plate
`with the thinnest tA1 (100 A˚ ) has the thickest tA2 (1600 A˚ ),
`and vice versa. As tA1 increases from 100 to 600 A˚ , the
`thickness of the high resistivity film increases while the
`thickness of the low resistivity film decreases, resulting an
`increase in the overall contact resistance. The increase in
`RC(VGS ¼ 5 V) with increasing tA1
`suggests that bulk
`resistivity of the amorphous silicon film dominates at lower
`gate voltages (VGS < 5 V). As the gate bias increases (VGS 
`10 V), the bulk resistivity diminishes due to increasing space
`charge region in the amorphous silicon. With decreasing
`contribution from the bulk resistivity, the junction resistivity
`begins to dominate, and RCðVGSÞ becomes invariant to the
`thickness of tA1 or tA2. The origin of the decrease in R0 is
`still being investigated. One possibility for such observation
`could be due to extraction artifact. Lastly the L of the
`advanced transistor increases with A1 a-Si:H film thickness.
`This increase is a response to the contact resistance increase:
`since the bulk resistivity of the film goes up with tA1 at gate
`biases below 10 V, the cross-sectional area (W  L) for the
`current flow has to increase to compensate for this change.
`
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`
`

`

`Jpn. J. Appl. Phys., Vol. 47, No. 5 (2008)
`
`A. KUO et al.
`
`From the minimum contact resistance and L values, we
`calculate the specific contact resistance of the TFT with tA1
`of 300 A˚
`to be 0.79
` cm2, which is quite close to the
`suggested value of 0.5
` cm2 provided by Kanicki et al.18)
`
`5. Conclusions
`
`We have fabricated and characterized the intrinsic and
`extrinsic electrical properties of the advanced a-Si:H TFT
`with the dual a-Si:H and a-SiNX:H layers. Based on our
`investigation,
`the film thickness of the high electronic
`quality a-Si:H should be near 300 A˚ for the TFT to exhibit
`adequate characteristics without requiring long PECVD
`time. At tA1 of 300 A˚ , our TFT has a linear regime field-
`effect mobility of 0.94 cm2 V1 s1, threshold voltage of
`1 V, subthreshold swing of 0.51 V/dec, R0 of 0.1 M
`, and
`specific contact resistance of 0.79
` cm2. For tA1 thinner
`than 300 A˚ we observe an increase in S while additional tA1
`does not improve mobility, threshold voltage or subthreshold
`swing significantly.
`
`Acknowledgement
`
`One author (A. Kuo) would like to thank AKT America
`Inc. for financial support.
`
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