SEL EXHIBIT NO. 2009
`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
`
`IPR2013-00064
`
`

`

`United States Patent
`Mori et al.
`
`[191
`
`[54] THIN FILM TRANSISTORS WITHOUT
`CAPACITANCES BETWEEN ELECrRODES
`THEREOF
`[71 Inventors: Hisatoshi Mori, Fussa; Nobuyuki
`Yamamura, Hanno, both of Japan
`f73] Assignee: Casio Computer Co., Ltd., Tokyo,
`Japan
`[21) App!. No.: 845,771
`
`[22] Filed:
`
`Mar. 3, 1992
`
`[63]
`
`[30]
`
`Related U.S. Application Data
`Continuation of Ser. No. 574,657. Aug. 28. 199G, aban-
`doned.
`Foreign Application Priority Data
`Japan
`Sep. 6, 1989 [3?]
`
`I-229227
`
`[SI] mt. CI.5
`[52] u.s. a.
`[58] Field of Search
`
`HOIL 49/02
`257/412; 257/66
`357/23.4, 4, 23.7;
`257/61, 59, 66, 72, 412
`References Cited
`U.S. PA1tNT DOCUMENTS
`4,951.113 8/1990 Huang eta].
`
`257/61
`
`[56]
`
`17
`
`15
`
`-
`
`t
`
`111111 I1iI1IlIi1iIIliIIIl liii! III
`lIllIllIll 1111 III!! litiO Iii 11111 EllI
`US5270567A
`Patent Number:
`[11]
`[45] Date of Patent:
`
`5,270,567
`Dec. 14, 1993
`
`357/23.7
`257/61
`
`5/L991 Tanaka et a!,
`5.017,984
`5,109,260 4/1992 Tanaka et al.
`FOREIGN PATENT DOCUMENTS
`53.26584 3/1978 Japan
`Japan
`56-15063
`2/1981
`58-28870 2/1983 Japan
`60-117881 6/1985 Japan
`61-105863 5/1986 Japan
`61-156106 7/1986 Japan
`62-15857 1/1987 Japan
`62-213165 9/1987 Japan
`63-131569 6/1988 Japan
`I-9 1461 4/1989 Japan
`Primary ExaminerMartin Lerner
`Assistant ExaminerHung Dang
`Attorney, Agent, or FirmFrishauf, Holtz, Goodman &
`Woodward
`
`357/23.7
`357/23.7
`357/4
`357/23.7
`357/4
`350'334
`357/4
`357/4
`337/4
`357/23.7
`
`ABSTRACT
`[57)
`In this film transistor used for a liquid crystal display
`element, etc., the source and drain electrodes are
`formed at positions which do not overlap the gate dcc-
`trode. Capacitances between the gate and source elec-
`trodes and between the gate and drain electrodes can be
`almost eliminated.
`
`5 Claims, 6 Drawing Sheets
`
`,-16
`
`15
`
`i*aS
`-- -
`
`13
`
`11
`
`14
`
`12
`
`tEXHIbIT
`
`Exhibit 1003, page 1
`
`

`

`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet I of 6
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`5,270,567
`
`L.
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`Exhibit 1003, page 2
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`

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`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 2 of 6
`
`5,270,567
`
`ID (A)
`i X i o-
`1X10-6
`1 Xl g-8
`1x10-10
`1x10-12
`1x10 14
`-40
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`Vo =10 V)
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`+40
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`VG ( V)
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`FIG. 3
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`ID (X106A)
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`(VG=15V)
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`Exhibit 1003, page 3
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`

`

`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 3 of 6
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`5,270,567
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`US. Patent
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`Dec. 14, 1993
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`Sheet 3 of 6
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`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 4 of 6
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`5,270,567
`
`ELEMENT OF FIG.5
`
`ELEMENT OF FIG.6
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`i
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`t
`100
`1000
`FREQUENCY (kHz)
`
`(CICmax)
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`Exhibit 1003, page 5
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`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet S of 6
`
`5,270,567
`
`29
`
`22
`FIG. 9
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`23
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`Exhibit 1003, page 6
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`U.S. Patent
`
`Dec. 14, 1993
`
`Sheet 6 of 6
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`5,270,567
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`23
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`Exhibit 1003, page 7
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`

`

`5
`
`30
`
`5,270,567
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`i
`THIN FILM TRANSISTORS WITHOUT
`CAPACITANCES BrrWEEN ELECFRODES
`THEREOF
`
`2
`istics during a one-frame period until the next pixel
`electrode is selected are degraded.
`SUMMARY OF THE INVENTION
`The present ¡nventiori has been made in consideration
`This application is a Continuation of application Ser.
`or the above problem. and has as its object to provide a
`No. 07/574,657 flIed on Aug. 28, 1990 now abandoned.
`thin film transistor having almost no capacitances be-
`BACKGROUND OF THE INVENTION
`tween a gate electrode and a source eketrodes and
`10 between the gate electrode and a drain electrode.
`L Field orthe Invention
`In order to achieve the above object, according to the
`The present invention relates to a thin film transistor
`present invention, there is a thin fdm transistor compris-
`and, more particularly, to a thin filai transistor which is
`ing a gate electrode, a gate insulating film, an i-type
`improved not to have capacitances between a gate elec-
`ti-ode and source and drain electrodes.
`semiconductor layer. an n-type semiconductor layer, a
`2. Description of the Related Art
`15 source electrode, and a drain electrode, wherein the
`Thin film transistors (TFTS) include inverted-stag-
`source and drain electrodes are formed at positions
`ger, stagger, inverted-coplanar, coplanar transistors.
`which do not overlap the gate electrode. Using the
`FIG. i shows a conventional thin film transistor. and,
`above arrangement, capacitances between the gate and
`in this case inverted-stagger transistor. In FIG. I, refer-
`drain electrodes and between the gate and drain eke-
`ence numeral i denotes a substrate made ofgiass or the 20 trodes can be almost eliminated. In addition. character-
`like, and a gate electrode 2 made of a metal such as Cr
`of the thin filai transistor can be confirmed.
`is formed on the substrate 1. Reference numeral 3 dc-
`Additional objects and advantages of the invention
`notes a gate insulating film made of SiN or the like
`will be set forth in (he description which follows, and in
`formed on the gate electrode 2 throughout the entire
`surface of the substrate 1, and reference numeral 4 de- 25 part will be obvious from the description, or may be
`learned by practice of the invention. The objects and
`notes an i-type a-Si semiconductor layer formed on the
`advantages of the invention may be realized and ob-
`gate insulating film 3. The i-type semiconductor layer 4
`thS by means of the instrumentalities and combina-
`is opposite to the gate electrode 2 through the gate
`tions particularly painted out in the appended claims.
`insulating film 3. Reference numeral 5 denotes n+.type
`a-Si semiconductor layers formed on the i-type semi-
`BRIEF DESCRIPTION OF THE DRAWINGS
`conductor layer 4, and the n-type semiconductor layers
`The accompanying drawings. which are incorpo-
`s are formed to vertically oppose the gate electrode 2
`rated in and constitute a pan of the specification, illus-
`and separated from each other on a channel portion.
`Reference numerals 6 and 7 denote source and drain
`trate presently preferred embodiments ofthe invention,
`electrodes made of a metal such as Cr and formed on
`and together with the general description given above
`the n-type semiconductor layers 5. The source and
`and the detailed description of the preferred embodi-
`drain electrodes 6 and 7 are formed to have the same
`ments given below, serve to explain the principles of the
`pattern as those of the n-type semiconductor layers S
`invention.
`and connected to the i-type semiconductor layer 4
`FIG. i is a sectional view showing a conventional
`through the n-type semiconductor layers 5. Note that
`thin film transistor;
`this thin film transistor is used as a pixel electrode selec-
`FIG. 2 s a sectional view showing a thin film transis-
`tion switching element of a TFT active matrix liquid
`tor according to the first embodiment of the present
`crystal display element. When the thin film transistor is
`-Invention;
`employed to the TFT active matrix liquid crystal dis-
`FIG. 3 is a graph showing Vc-ID characteristic
`play element, the gate electrode 2 of the thin film tran-
`curves of the thin film transistor in FIG. 2;
`sistor is connected to a gate line (scanning line), and the
`FIG. 4 is a graph showing a Vo-I& characteristic
`drain and source electrodes 7 and 6 are connected to a
`curve of the thin film transistor in FIG. 2
`data line and a pixel electrode, respectively,
`FIGS. 5 and 6 are views showing a testing element
`In the above thin film transistor, however, since the
`for measuring frequency characteristics of the thin film
`source and drain electrode 6 and 7 are vertically oppe-
`site to the gate electrode 2 through the n-type and i-type
`transistor;
`semiconductor layers S and 4 and the gate insulating
`FIG. 7 is a graph showing frequency characteristics
`film 3, respectively, large capacitances C0sand CaDare
`of the testing element in FIGS. 5 and 6;
`generated between the gate electrode 2 and the source 55
`FIG. S is a sectional view showing a thin film transis-
`electrode 6 and between the gate electrode 2 and the
`tor formed such that source and drain electrodes and an
`drain electrode 7.
`n-type semiconductor layer do not vertically overlap a
`For this reason, when the thin film transistor is used
`gate electrode;
`as, e.g., a pixel electrode selection switching element of
`FIG. 9 is a plan view showing a thin film transistor
`a TFT active matrix Liquid crystal display element, a 60
`according to the second embodiment of the present
`voltage is applied from the data line to the pixel elec-
`invention;
`trode when the thin transistor is turned on upon applica-
`FIGS, IO and Il are enlarged sectional views show-
`tion of a gaie voltage. When the thin film transistor is
`ing the thin film transistor taken along lines XX and
`turned oli, this voltage is immediately distributed in
`accordance with a rate of the gate-source capacitance 65 X1Xl in FIG. 9; and
`FIG. 12 is a sectional view showing a thin film tran-
`(Ccs) to the Liquid crystal capacitance (Ctc). For this
`reason, since the voltage at the pixel electrode is de-
`sistor according to the third embodiment of the present
`creased lower than the data voltage, display character-
`invention.
`
`Exhibit 1003, page 8
`
`

`

`5 .270, 567
`
`5
`
`4
`3
`element in FIG- 6 is obtained by forming the upper
`DETAILED DESCRIPTION OF THE
`metal film 18 to have a j area of the lower metal film
`PREFERRED EMBODIMENTS FIRST
`1k Note chat, in FIGS. 5 and 6, reference numeral 19
`EMBODIMENT
`denotes an opening which is formed in a part of the
`The first embodiment of the present invention will be
`stacked film from the upper metal film 18 to the insulat-
`described below.
`ing film iSa and which is formed for applying a voltage
`FIG. 2 is a sectional view showing a thin film transis-
`to the lower metal film 12«,
`tar according to this embodiment. Reference numeral
`When the frequency characteristics of the two types
`Il denotes a substrate made of glass or the like, and a
`of testing elements are measured by applying a testing
`pte electrode Il made of a metal such as Cr is formed
`IO voltage of 35 V to the Lower metal film 12a the fre-
`on the substrate IL Reference numeral 13 denote a gate
`quency characteristics of the testing element in FIG. 5
`insulating film formed on the gate electrode 12 through-
`obtained by forming the upper metal film IS to have an
`out the almost entire surface of the substrate II, and
`area which is almost equal to that of the lower metal
`reference numeral 14 denotes an i-type semiconductor
`film 12a has characteristics indicated by a broken line in
`layer roide of amorphous silicon or polysilicon and
`15 FIG. 7, and the testing element in FIG. 5 has a mni-
`formed on the gate insulating film 13. The i-type semi-
`mum capacitance of about 65 pF. The frequency char-
`conductor layer 14 is opposite to the gate electrode 12
`acteristics of the testing element in FIG. 6 obtained by
`through the gate insulating film 13. Reference numerals
`forming the upper metal film 18 co have a area of the
`15 denote n-type semiconductor layers made of amor-
`lower metal film 12a are characteristics indicated by a
`phous silicon or polysilicon and formed on the i-type
`20 solid line in FIG. 7. The testing element in FIG. 6 has a
`semiconductor layer 14, and the n-type semiconductor
`maximum capacitance 0(63 pF which is equal to that of
`layers 15 are formed to vertically oppose the gate elec-
`the testing element in FIG. Sin a low- frequency region
`trode 12 and separated from each other on a channel
`(1.0 kHz), but the testing element has a maximum capac-
`portion. Reference numerals 16 and 17 respectively
`itance of 19 pF (C/Cmax=0.3) in a high-frequency
`denote source and drain electrodes made of a metal such
`25 region (1.0 MHz), The testing element in FIG. 6 has a
`as Cr formed on the n-type semiconductor layer 15. The
`capacitance almost equal to that of the testing element
`source and drain electrodes 16 and 17 are formed at
`in FIG- 5 in the low-frequency region, since the n-type
`positions which do not vertically overlap the gate elec-
`semiconductor layer 15« formed on the i-type semicon-
`trode 12. The source and drain electrodes 16 and 17 are
`ductor layer 14o to have the same pattern as that of the
`connected to the i-type semiconductor layer 14 through
`30 lower metal film 12« serves as an electrode in the low-
`the n-type semiconducror layers 15. In this embodiment,
`frequency region. A region constituted by a single layer
`a length l of an isolated portion (channel portion) of the
`of the n-type semiconductor layer 15« does not have a
`n-type semiconductor is set to be 5 gm, a horizontal
`capacitance in the low-frequency region.
`interval 2 between the source or drain electrode 16 or
`That is, the capacitances between the gate and source
`17 is set to be 5 jim, and a length 13 of the extended
`35 electrodes 12 and 16 and between the gate and drain
`portion of the n-type semiconducLor layer 15 from the
`electrodes 12 and 17 depend on a portion where the
`source or drain electrode 16 or 17 is set to be 9 jim.
`drain and gate electrodes 16 and 17 overlap the gate
`FIGS. 3 and 4 show static characteristics of the thin
`electrode 12. As the thin film transistor of the first em-
`film transistor, wherein FIG. 3 shows VG (gate vol.
`bodiment, when the source and drain electrodes 16 and
`t.age)ID (drain current) characteristics when V1,
`40 17 are formed at a positions which do not vertically
`(drain voltage) =10 V, and FIG. 4 shows VDIn
`overlap the gate electrode 12, capacitances between the
`characteristics when VG = 15V.
`gate and source electrodes 12 and 16 and between the
`gate and drain electrodes 12 and 17 in the high-fre-
`In the thin film transistor, since the source and drain
`electrodes 16 and 17 are formed at positions which do
`quency region are lower than those characteristics indi-
`not vertically overlap the gate electrode 12. capaci- 45 cated by the solid line in HG. 7.
`tances at high-frequency regions between the gate elec-
`In addition, in the thin film transistor according to the
`trode 12 and the source electrode 16 and between the
`first embodiment, the n-type semiconductor layers 15
`gate electrode 12 and the drain electrode 17 can be
`for connecting the gate electrode 12 to the source and
`almost eliminated.
`drain electrodes 16 and 17 are formed to vertically
`FIG. 7 shows a result obtained by measuring the two
`so oppose the gate electrode 12, and the source and drain
`types of testing elements shown in FIGS. 5 and 6,
`electrodes 16 and 17 are connected to the i-type semi-
`wherein the abscissa indicates frequencies (kHz), and
`conductor layer 14 through the n-type semiconductor
`the ordinate indicates a rate (C/Cmax) of a measuring
`layen IS. Therefore, as described above, the n-type
`capacitance (C) corresponding to each frequency to a
`semiconductor layers 15 serve as source and drain cloe-
`maximum capacitance (Cmax obtained by changing
`55 trodes to obtain satisfactory transistor characteristics.
`frequencies. Each of the testing elements is formed by
`flat is, in order to eliminate the capacitances be-
`the following manner. A lower metal fm 12a is formed
`tween the gate and source electrodes 12 and 16 and
`on a glass substrate lia, and an insulating film ¡So made
`between the gate and drain electrodes 12 and 17, as in
`of SiN and an i-type semiconductor layer 1 made of
`the thin film transistor shown in FIG. 8, the source and
`amorphous silicon or polysilicon are stacked thereon.
`60 drain electrodes 16 and 17 and the n-type semiconduc-
`An n-type semiconductor layer 15« made of amorphous
`tor layers 15 may be formed at the positions which do
`silicon or polysilicon is formed on the i-type sernicon-
`not vertically overlap the gate electrode 12. However,
`ductor layer 14« to have the same pattern as the lower
`when a gate voltage is applied to the gate electrode 12,
`the thin film transistor is not operated, and any ON
`metal film 12«, and an upper metal film 1$ is formed on
`the ntype semiconductor layer ISa. The testing ele-
`65 current (Ion) does not flow. For this reason, in the thin
`ment in FIG. 5 is obtained by forming the upper met-al
`film transistor of the above embodiment, the n-type
`film 18 to have an area (3.6 x ìo
`cm2) which is almost
`semiconductor layers IS for connecting the gate elec-
`equal to chat of the lower metal film 12a. and the testing
`trode 12 to che source and drain electrodes 16 and 17 are
`
`Exhibit 1003, page 9
`
`

`

`5,270,567
`
`5
`formed to vertically oppose the gate electrode 12, and
`only the source and drain electrodes 16 and 17 are
`formed at positions which do not vertically overlap the
`gate elects-ode 12. In this manner, as shown in FIGS. 3
`and 4, since the drain current ID of about 1.5 jzA flows 5
`when the drain voltage VD= 10V and the gate voltage
`Vç IS V, satisfactory transistor characteristics can be
`obtained.
`In a thin film transistor used as, cg., a pixel electrode
`selection switching element of a TFT active matrix 10
`liquid crystal display element, a gate ON time required
`for the ON current 'ON is about 60 p.sec, which cone-
`spends to a frequency of 17 kHz, and a fall tüte of a gate
`pulse which adversely affects the gate-source capaci-
`tance (Cas) is about 60 Fssec, which corresponds to a IS
`frequency of 20 MHz. As in the thin film transistor of
`the first embodiment, when a portion where the source
`and drain electrodes are opposite to the gate electrode
`12 is formed by only the n-type semiconductor layers
`15, the n-type semiconductor layen 15 serve as source 20
`and drain electrodes in the gate ON time (17 kHz) to
`flow the ON current (ION). Since the n-type semicon-
`ductor layer 15 has a gate-source capacitance (Cas) in
`the fall time (20 MHz), when the thin film transistor is
`turned off, the pixel electrode voltage is not distributed 25
`at a rate of the gate-source capacitance (CaS) to a liquid
`crystal capacitance (CLC). Therefore, a display state can
`be continued during a one-frame period until the next
`pixel electrode is selected.
`The inverted-stagger thin film transistor has been 30
`described in the above first embodiment, but the present
`invention can be applied to stagger, inverted-coplanar,
`and coplanar thin transistors. In addition, the present
`invention can be applied to not only a thin film transis-
`tor used as a pixel electrode selection switching element 35
`of a TET active matrix liquid crystal display clement,
`but a thin film transistor used in other applications.
`
`Second Embodiment
`The second embodiment of the present invention will 40
`he described below. FIGS. 9 to 11 show a thin film
`transistor of a TFT panel used ¡n a TEr active matrix
`liquid crystal display element according to the second
`embodiment of the present invention.
`Referring to FIGS. 9 to II. reference numeral 21 45
`denotes an insulating transparent substrate made of
`glass, reference numeral 22 denotes a gate electrode
`formed on the substrate 21, and reference numeral 23
`denotes a gate line (scanning line) wired on the substrate
`21 and made of a metal such as chromium. The gate 50
`electrode 22 is connected to the gate line 23. The gate
`electrode 22 is formed by an n-type semiconductor
`layer made of amorphous silicon or polysilicon. The
`gate electrode 22 and the gate line 23 constituted by the
`n-type semiconductor layer are formed as follows. An 55
`n-type semiconductor and a metal such as chromium are
`sequentially deposited on the substrate 21, the metal
`film is patterned to have a shape of the gate line 23, and
`then the deposited n-type semiconductor film is pat-
`tuned to have a shape of the gate electrode 22. The 60
`deposited n-type semiconductor film is
`linearly left
`under the gate line 23 throughout the entire length of
`the gate line 23, and the gate electrode 22 is connected
`to the gate line 23 at a line portion 22a under the gate
`line 23. Note that the thickness of the n-type semieon- 65
`ductor layer serving as the gate electrode 22 is about
`250 A, and the thickness of the gate line 23 is about
`l,0» A.
`
`6
`Reference numeral 24 denotes a transparent gate
`insulating film formed on the entire surface of the sub-
`strate 21 on the gate electrode 22 and the gate line 23
`and made of silicon nitride (SiN). An i-type setnicon-
`ductor layer 25 made of amorphous silicon or polysili-
`con is formed to oppose the gate electrode 22 on the
`gate insulating film 24. Reference numeral 26 denotes an
`n-type semiconductor layer formed on the i-type semi-
`conductor layer 25 and made of amorphous silicon or
`polysilicon, and the n-type semiconductor layers 26 are
`isolated froni each other on a channel portion. Refer-
`ence numerals 27 and 28 denote source and drain elec-
`trodes made of a metal such as chromium. The source
`and drain electrodes 27 and 28 are formed on the n-type
`semiconductor layers 26 and connected to the i-type
`semiconductor layer 25 through the n-type semiconduc-
`tor layen 26. An inverted-stagger thin film transistor is
`constituted by the gate electrode 27, the gate insulating
`film 24, the i-type semiconductor layer 25, the n-type
`semiconductor layers 26, and the source and drain elec-
`trodes 27 and 2R. The drain electrode 28 is connected to
`a data line 29 wired perpendicularly to the gate line 23
`on the gate insulating film 24. Reference numeral 30
`denotes a pixel electrode constituted by a transparent
`conductive film such as ITO formed on the gate insulat-
`ing film 24. The pixel electrode 30 is connected to the
`source electrode 27 such that a terminal of the pixel
`electrode 30 is formed to overlap the source electrode
`27.
`That is, in the thin film transistor of the second em-
`hodiment, the source and drain electrodes 27 and 28 are
`formed to vertically oppose the gate electrode 22, and
`the gate electrode 22 is made of an n-type setniconduc-
`tor and connected to the gate line 23 made of a metal.
`According to the thin film transistor of the second
`embodiment, since the gate electrode 22 is made of an
`n-type semiconductor, capacitances between the gate
`electrode 22 and the source electrode 27 and between
`the gale electrode 22 and the drain electrode 28 can be
`eliminated. That is, when the gate electrode 22 is made
`of an n-type semiconductor, the source and drain dcc-
`trodes 27 and 28 are metal electrodes and capacitances
`are not formed between the gate electrode 22 and the
`source electrode 27 and between the gate electrode 22
`and the drain electrode 28 even if the gate electrode 22
`is vertically opposite to the source and drain electrodes
`27 and 28. This is because one of the gate electrode 22
`and the source or drain electrode 27 or 28 which inter-
`poses the gate insulating film 24, the i-type semiconduc-
`tor layer 2$, and the n-type semiconductor layer 26 with
`the gate electrode 22 comprises only an n-type semicon-
`ductor electrode. Therefore, as in the thin film transis-
`tor of the first embodiment, capacitances between the
`gate electrode 22 and the source electrode 27 and be-
`tween the gate electrode 22 and the drain electrode 28
`can be eliminated. According to this thin film transistor.
`the capacitances are not formed between the gate elec-
`trode 22 and the source electrode 27 and between the
`gate electrode 22 and the drain electrode 28. Unlike a
`conventional thin film transistor, when the thin 1dm
`transistor is turned off, a voltage applied from the data
`line to the pixel electrode by turning on the thin 1dm
`transistor upon application of the gate voltage is not
`immediately distributed at a rate of a gate-source capac-
`itance to a liquid crystal capacitance. Therefore, since
`the pixel electrode voltage during a one-frame period
`until the next pixel electrode 30 is selected can be kept
`at a voltage almost equal to a data voltage applied dur-
`
`Exhibit 1003, page 10
`
`

`

`5,270,567
`
`7
`Ing the selection a display state during the one-frame
`period can be properly maintained, thereby improving
`display characteristics of a liquid crystal display ele-
`ment.
`In addition, in the above thin film transistor of the
`second embodiment since metal electrodes are used as
`the source and drain electrodes 27 and 28 and the source
`and drain electrode 27 and 28 are vertically opposite to
`the gale electrode 22, an ON current larger than that of
`the thin fUni transistor of the first embodiment can be
`obtained.
`In the thin film transistor of the second embodiment,
`only the gate electrode 22 is made of an n-type semicon-
`ductor and the gate line 23 connected to the gate elec-
`trode 22 is a metal line. Although the gate electrode 22
`is made of an n-type semiconductor, the electric resis-
`tance of the gate line 23 can be decreased, and voltage
`drop across the gate line 23 can be reduced.
`Note that, in the second embodiment, an n-type semi-
`conductor layer serving as the gate electrode 22 is lin-
`early formed throughout the entire length of the gate
`line 23, and the n-type semiconductor serving as the
`gate electrode 22 may be provided to only the transistor
`element portion. The gate electrode 22 may be formed
`such that a portion of the electrode 22 overlaps the gate
`line 23 to connect the gate line 23. In addition, an invert-
`ed-stagger thin film transistor has been described in the
`above second embodiment. The present invention can
`be applied to stagger, inverted-coplanar, and coplanar
`thin rum transistors. The present invention can be
`widely applied to not only a thin film transistor of a
`TET panel for a Tri' active matrix liquid crystal dis-
`play element, but thin firm transistors for various pur-
`poses such as a thin film transistor used as a memory
`element of a TV!' memory array.
`
`Third Embodiment
`The third embodiment of the present invention will
`be described below, FIG. 12 is a sectional view showing
`a thin film transistor according to the third embodiment
`of the present invention.
`In the thin film transistor of the third embodiment,
`the n-type semiconductor layer described in the second
`embodiment is used as the gate electrode of the thin film
`transistor described in the first embodiment.
`That is, as a substrate, a gate electrode 32 constituted
`by an n-type semiconductor layer made of amorphous
`silicon or polysilicon is formed. Reference numeral 33
`denotes a gate insulating film made of SiN or the like
`and formed on the gate electrode 32 throughout the
`almost entire surface of the substrate 31, and reference
`numeral 34 denotes an i-type semiconductor layer
`which is opposite to the gate electrode 32 through the
`gate insulating film 33. Reference numerals 35 denote
`n-type semiconductor layen made of amorphous silicon
`or polysilicon and deposited on the i-type seniiconduc-
`tor layer 34, and the n-type semiconductor layers 35 are
`formed to vertically oppose the gate electrode 32 and
`isolated from each other on a channel portion. Refer-
`ence numerals 36 and 37 denote source and drain elec-
`trodes made of a metal such as Cr and formed on the
`n-type semiconductor layers 35. The source and drain
`electrodes 36 and 37 ar formed at positions which do
`not vertically overlap the gate electrode 32, and the
`source and drain electrodes are connected to the i-type
`
`8
`semiconductor layer 34 through the n-type semiconduc-
`tor layers 35.
`As described above, according to this embodiment, as
`in the first embodiment, capacitances between the gate
`5 and source electrodes and between the gate and drain
`electrodes can be almost eliminated, and satisfactory
`thin film transistor characteristics can be properly ob-
`tainS.
`Although an inverted-stagger thin film transistor has
`lo been described in the third embodiment, this embodi-
`ment can be applied to stagger, inverted-coplanar, and
`coplanar thin film transistors.
`In addition, this embodiment can be applied to not
`only a thin film transistor used as a pixel electrode selec-
`IS tion switching element of a TF'T active matrix liquid
`crystal display element. but a thin film transistor used
`for other purposes.
`As described above, according to the present 'mven-
`tion, since the source and drain electrodes are formed at
`lo positions which do not overlap the gate electrode, ca-
`pacitances between the gate and source electrodes and
`between the gate and drain electrodes can be almost
`eliminated. in addition, satisfactory thin film transistor
`characteristics can be properly obtained.
`Additional advantages and modifications will readily
`occur to those skilled in the art. Therefore, the inven-
`tion in its broader aspects is not limited to the specific
`details, and representative devices, shown and de-
`scribed herein. Accordingly, various modifications may
`30 be made without departing from the spirit or scope of
`the general inventive concept as defined by the ap-
`pended claims and their equivalents.
`What is claimed is:
`A thin film transistor comprising:
`an I-type semiconductor;
`a gate electrode facing said I-type semiconductor
`with a gate insulating film therebetween;
`a pair of n-type semiconductor layers formed on a
`surface of said l-type semiconductor, said n-type
`semiconductor layers being separated from each
`other so as to form a channel portion in said I-type
`semiconductor, such that said n-type semiconduc-
`tor layers partially overlap said gate electrode,
`each of said n-type semiconductor layers having a
`first portion, overlapping said gate electrode, and a
`second portion, which does not overlap said gate
`electrode: and
`source and drain electrodes partially formed on the
`second portions of said n-type semiconductor lay-
`ers, such that said source and drain electrodes do
`not overlap said gate electrode.
`A thin film transistor according to claim 1, wherein
`said source and drain electrodes are situated outside of
`outer edges of said gate electrode.
`3. A thin film transistor according to claim 1. wherein
`said gate electrode is formed only on an n-type semicon-
`ductor layer.
`A thin film transistor according to claim 1, wherein
`each of said I-type semiconductor and said n-type semi-
`W conductor layers is formed of a thin film semiconductor
`of amorphous silicon.
`A thin film transistor according to claim 1, wherein
`each of said l-type semiconductor and said n-type semi-
`conductor layers is formed of a thin 61m semiconductor
`65 of polysilicon.
`
`40
`
`25
`
`35
`
`45
`
`50
`
`55
`
`Exhibit 1003, page 11
`
`