IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`In re Inter Partes Review of:
`
`US. Patent No.
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`7,956,978
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`US. Class: 349/153
`
`Issued:
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`Jun. 7, 2011
`
`Inventor:
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`Hongyong Zhang
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`App. Filed:
`
`Jul. 1, 2008
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`12/165,783
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`For: Semiconductor Energy
`
`PER 37 C.F.R. § 42.6(ii)
`
`Laboratory Co., Ltd.
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`FILED ELECTRONICALLY
`
`Mail Stop Patent Board(37 C.F.R. § 42.6(b)(ii))
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`Patent Trial and Appeal Board
`U.S.P.T.O.
`
`PO. Box 1450
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`Alexandria, VA 22313-1450
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`DECLARATION OF MILTIADIS HATALISI Ph.D.
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`I.
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`Background and Qualifications
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`(1)
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`My name is Miltiadis Hatalis.
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`I am currently a Professor at Lehigh
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`University in the Department of Electrical and Computer Engineering.
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`l have
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`studied, taught, and practiced in the relevant flat panel display technology for
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`over 25 years.
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`(2)
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`I received my Doctor of Philosophy (Ph.D.) degree in the field of
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`Electrical and Computer Engineering from Carnegie Mellon University in 1987.
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`In re Inter Partes Review of:
`
`US. Patent No.
`
`7,956,978
`
`US. Class: 349/153
`
`Issued:
`
`Jun. 7, 2011
`
`Inventor:
`
`Hongyong Zhang
`
`App. Filed:
`
`Jul. 1, 2008
`
`12/165,783
`
`For: Semiconductor Energy
`
`PER 37 C.F.R. § 42.6(ii)
`
`Laboratory Co., Ltd.
`
`FILED ELECTRONICALLY
`
`Mail Stop Patent Board(37 C.F.R. § 42.6(b)(ii))
`
`Patent Trial and Appeal Board
`U.S.P.T.O.
`
`PO. Box 1450
`
`Alexandria, VA 22313-1450
`
`DECLARATION OF MILTIADIS HATALISI Ph.D.
`
`I.
`
`Background and Qualifications
`
`(1)
`
`My name is Miltiadis Hatalis.
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`I am currently a Professor at Lehigh
`
`University in the Department of Electrical and Computer Engineering.
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`l have
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`studied, taught, and practiced in the relevant flat panel display technology for
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`over 25 years.
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`(2)
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`I received my Doctor of Philosophy (Ph.D.) degree in the field of
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`Electrical and Computer Engineering from Carnegie Mellon University in 1987.
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`The topic of my Ph.D. dissertation research was "Crystallization of Amorphous
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`Silicon Films and its Application in Bipolar and Thin Film Transistors." I received
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`my Masters of Science (M.S.) degree in Electrical and Computer Engineering in
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`1984 from the State University of New York at Buffalo and my Bachelor of Science
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`(BS) degree in Physics in 1982 from the Aristotle University of Thessaloniki in
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`Greece.
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`(3)
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`Upon receiving my Ph.D. degree, ljoined the faculty of Lehigh
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`University in the Department of Electrical and Computer Engineering as an
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`Assistant Professor.
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`l was promoted to the rank of Associate Professor with
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`tenure in 1991 and to the rank of Professor in 1995. From 1987-1992, I served as
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`Associate Director of Lehigh's ”Microelectronics Research Laboratory.”
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`(4)
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`In 1992, | founded and became Director of the ”Display Research
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`Laboratory,” which was the first academic laboratory in the United States
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`dedicated to research and development of Thin Film Transistors (TFTs) for Active
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`Matrix Liquid Crystal Displays (AMLCDs) and Active Matrix Organic Light Emitting
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`Diode (AMOLEDs) displays. As Director of Lehigh's ”Display Research Laboratory,”
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`l have raised over $10 million through research contracts and grants to support
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`the laboratory's research and development activities on thin film transistors and
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`their application to flat panel displays. These contracts and grants were funded
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`by the Defense Advanced Research Program Agency (DARPA), the Army Research
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`Laboratory (ARL), the National Science Foundation (NSF), the National
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`Aeronautics and Space Administration (NASA), the State of Pennsylvania, and a
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`variety of industrial companies including IBM, Kodak, Sharp, Northrop Grumman,
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`and others.
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`(5)
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`Since becoming a faculty member in 1987, l supervised the
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`research of eighteen Ph.D. dissertations in the technical field of TFTs and, along
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`with my graduate students, published over 150 technical publications in scientific
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`journals or conferences in the field of thin film transistors and their applications in
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`flat panel displays.1 In addition to the aforementioned Ph.D. dissertations, l have
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`also supervised a large number of graduate student master’s theses and
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`undergraduate research projects.
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`l have taught a number of different
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`undergraduate and graduate level courses in the Electrical and Computer
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`Engineering department at the Lehigh University dealing with the physics,
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`technology, and the design of solid—state devices and circuits.
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`l have also
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`introduced and regularly teach a course on ”Semiconductor Material and Device
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`Characterization,” and l have also reorganized a course on ”Introduction to Design
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`of Very Large Scale Integration (VLSI).”
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`1 More information on this subject can be found on my research group web
`pages: www.ece.lehigh.edu/DRL
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`(6)
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`As part of my research, | utilize much of the same equipment and
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`many of the same microfabrication processes that are relevant to US. Patent No.
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`7,956,978 (hereinafter referred to as the "’978 patent"), including: Plasma—
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`Enhanced Chemical Vapor Deposition (PECVD) for intrinsic hydrogenated-
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`amorphous silicon, silicon nitride and silicon dioxide films; sputter and e—beam
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`deposition tools for aluminum, indium-tin—oxide, tantalum and other metallic thin
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`films; photolithographic tools for spinning, exposure and developing photoresist
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`patterns; as well as plasma or wet etching tools for removing various thin film
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`materials from the substrate. Furthermore, I also utilize several tools for the
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`characterization of the materials and structures used in thin film transistors
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`including: optical microscopes, Scanning Electron Microscopy (SEM),
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`Transmission Electron Microscopy (TEM), and Atomic Force Microscopy (AFM).
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`I
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`also utilize a variety of electrical characterization techniques and instruments for
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`testing the electrical performance of completed TFT circuits and flat panel
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`displays.
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`(7)
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`As part of my research, I pioneered a technique for crystallizing
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`amorphous silicon. The technique I pioneered has been used in the manufacture
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`of small polysilicon TFT AMLCDs for over a dozen years, and, more recently,
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`polysilicon TFTs have also been used for AMOLED displays.
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`In addition, many
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`industrial and academic laboratories have recently initiated R&D activities related
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`to the fabrication of polysilicon thin film transistors on flexible metal foil
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`substrates and their application to flexible displays. Such research flows from the
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`accomplishments of my research group in this technical field.
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`(8)
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`My industrial experience includes work at the XEROX Palo Alto
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`Research Laboratory and various consulting projects with flat panel display
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`companies as well as companies producing equipment for the manufacture of flat
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`panel displays. All of these projects were related to the thin film transistors and
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`their application to flat panel displays.
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`(9)
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`lam a member of several professional organizations including the
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`Society for Information Display (SID), and the Electron Device Society of the
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`Institute of Electrical and Electronics Engineers (IEEE).
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`l have also been the chair
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`or co—chair at numerous national and international conferences/symposiums
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`including several SID sponsored Workshops on Active Matrix Liquid Crystal
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`Displays and a Materials Research Society Symposium on Flat Panel Displays.
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`l
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`have co-authored two book chapters, one dealing with the ”Polysilicon TFT
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`Technology” and another on application of ”Polysilicon TFTs in AMOLED Displays.”
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`l have served as a reviewer for technical papers submitted to several scientific
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`journals and have also served as a reviewer for several years for the National
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`Science Foundation Small Business Innovative Research (SBIR) program.
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`(10)
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`A copy of my latest curriculum vitae (C.V.) is attached as Appendix
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`A and includes a list of my publications.
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`II.
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`My Status as an Independent Expert Witness
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`(11)
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`I have been retained in this matter by Chimei lnnolux Corp.
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`(”Petitioner”) to provide an analysis of the scope and content of the ’978 patent
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`relative to the state of the art at the time of the earliest application underlying
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`the ’978 patent.
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`(12)
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`lam being compensated at the rate of $300 per hour for my work.
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`My fee is not contingent on the outcome of any matter or on any of the technical
`
`positions I explain in this declaration.
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`l have no financial interest in Petitioner.
`
`(13)
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`l have been informed that Semiconductor Energy Laboratory Co.,
`
`Ltd. (hereinafter referred to as ”Patentee”) owns the ’978 patent.
`
`l have no
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`financial interest in the Patentee or the ’978 patent nor have I ever had any
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`contact with the Patentee, or the inventors of the ’978 patent, Yoshiharu Hirakata
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`and Shunpei Yamazaki.
`
`||l.
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`Description of the Relevant Field and the Relevant Timeframe
`
`(14)
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`l have carefully reviewed the ’978 patent.
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`(15)
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`For convenience, all of the information that I considered in
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`6
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`arriving at my opinions is listed in Appendix B.
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`(16)
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`Based on my review ofthese materials, I believe that the relevant
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`field for purposes of the ’978 patent is microelectronic fabrication processes and
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`devices related to flat panel displays and in particular to Active Matrix Liquid
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`Crystal Displays (AMLCD) .
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`l have been informed that the relevant timeframe is
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`March December 21, 1995.
`
`(17)
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`As described in Section | above, I have extensive experience in the
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`relevant field. Based on my experience, I have a good understanding of the
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`relevant field in the relevant timeframe.
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`IV.
`
`The Person of Ordinary Skill in the Relevant Field in the Relevant
`Timeframe
`
`(18)
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`I have been informed that ”a person of ordinary skill in the
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`relevant field” is a hypothetical person to whom an expert in the relevant field
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`could assign a routine task with reasonable confidence that the task would be
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`successfully carried out.
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`I have been informed that the level of skill in the art is
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`evidenced by the prior art references. The prior art discussed herein
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`demonstrates that a person of ordinary skill in the art, at the time the ’978 patent
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`was filed, was aware of liquid crystal display structures, including techniques for
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`creating a uniform gap in the seal region between the two opposing substrates.
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`(19)
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`Based on my experience, l have an understanding of the
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`capabilities of a person of ordinary skill in the relevant filed.
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`l have supervised
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`and directed many such persons over the course of my career.
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`V.
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`Background of the Technology
`
`(20)
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`In an active matrix LCD, an image is divided into small elements
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`called pixels.
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`In a color active matrix LCD, each pixel is further divided into three
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`sub-pixels, one for each of the three primary colors red, green, and blue. Each
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`pixel (in a monochrome display) or sub-pixel (in a color display) contains a thin
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`film transistor (TFT), a capacitor, and a pixel electrode, all on the same glass
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`substrate called a backplane.
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`(21)
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`The backplane glass substrate is kept a small distance away from
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`another glass substrate, known as front—plane, which contains the color filters and
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`the display common electrode. The two glass substrates are bonded via a seal in
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`close proximity and along all the edges of the two glass substrates. The gap space
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`in between the two glass substrates is filled with a liquid crystal material.
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`(22)
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`To ensure high image quality certain approaches are been
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`followed during display construction in order to make a uniform gap between the
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`two glass substrates. These include the use of spacers and the formation of
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`dummy areas that would have the same height along the entire perimeter of the
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`sealing region.
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`(23)
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`In a pixel, the gate of a TFT is connected to a scan line, the drain
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`is connected to a signal line and the source is connected to the pixel electrode
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`and the storage capacitor. The TFT serves as a switch that, when turned ON via an
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`appropriate voltage of the scanning line, connects the storage capacitor to the
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`specific voltage of the signal line. When the TFT switch is turned OFF, current
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`cannot flow through it and thus, the voltage established at the storage capacitor
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`is maintained until the next frame period, at which time the TFT switch will be
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`turned on again in order to update the voltage stored in the capacitor.
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`(24)
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`The voltage stored in the pixel capacitor also appears to the pixel
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`electrode. This voltage sets an electric field across the liquid crystal material that
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`is between the pixel electrode and the common electrode; the higher the stored
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`voltage the higher the electric field. The magnitude of the electric field will
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`determine the optical properties of the LCD material and this, in turn, will
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`determine the amount of light that will pass through the pixel.
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`(25)
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`Individual pixels are switched by way of the TFTs in accordance
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`with scan and signal drive control circuitry.
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`In certain, active matrix LCDs the scan
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`and signal drive control circuitry are fabricated on the backplane glass substrate
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`at the periphery of the active matrix pixel array. Such circuitry typically consists
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`of a shift register fabricated with TFTs and wiring using the same materials as
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`those used in the array of pixels. For example, the wiring of a typical shift register
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`includes multiple, long conducting lines, along the side of the display the shift
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`register is driving, formed from the metal layer used in the formation of the signal
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`lines. These conducting lines are used as the power, ground or clock lines ofthe
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`shift register circuitry.
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`VI.
`
`The '978 Patent
`
`(26)
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`As shown below in Fig. 17, the '978 patent describes that prior art
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`active matrix LCD devices are known to include drive circuits (signal line drive
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`circuit 13 and scanning line drive circuit 14). These prior art devices are also
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`configured such that signal lines 15 and scanning lines 16 extend outside of a
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`sealing material region 17 of a substrate for connection to control and power
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`supply circuitry. (Ex. 1001, col. 2, ll. 3—10). Because lines 15 and 16 extend only
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`outside of the sealing material region on two sides of the sealing material region,
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`and these two sides are each opposite a drive circuit (13, 14) (having a different
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`physical height than lines 15 and 16), a non uniform gap formed about the
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`sealing region 17.
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`(Ex. 1001, col. 2, II. 47—49). This is because, when sealing the
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`substrate to another, an uneven pressure is applied in the sealing region in the
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`areas of varying step heights. That is to say, ”the step of the sealing material on
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`the peripheral drive circuit side is different from that of the sealing material on a
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`10
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`wiring extending side. Hence, in bonding the substrates together, because no
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`pressure is uniformly applied to the substrate, it is difficult to make an interval
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`between the substrates uniform. As a result, non uniformity occurs on display or
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`an image quality is deteriorated." Id. This non uniform gap is further described as
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`leading to shorting the scan and signal drive lines, thus causing display defects
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`such as line defects.
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`/11
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`(T————*—'\
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`l 1m
`'
`‘
`F‘
`l
`l
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`I;
`I
`1
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`161
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`”J 15/“
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`I
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`I
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`FlG.17
`(PHIURABT)
`
`(27)
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`As shown below in Fig. 1, in order to eliminate the uneven heights
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`caused by the asymmetrical lines and circuits about the sealing region, the ’978
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`patent describes an “interval maintaining means” or ”dummy wiring structure.”
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`The dummy wiring structure is designed to be electrically isolated from the signal
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`and scanning lines, and of a height in areas R3 and R4 that is ”nearly equal to the
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`height of the region in which the thickness of the matrix circuit is maximum." (i.e.
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`I
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`areas R1 and R2) (Ex. 1001, col. 4, II. 47—50; col. 6, M. 5—63).
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`11
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`FIG. 1
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`(28)
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`As shown below in Fig. 6 of the ’978 patent, the dummy wiring
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`structure, in some examples, is a laminate structure of layered dummy members
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`(301, 304).
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`(Ex. 1001, col. 4, II. 14—29). By the provision of the dummy wiring
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`structure, the interval or "gap" between substrates of the seal region in areas R1,
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`R2, R3 and R4 is equalized to facilitate a more consistent seal and high display
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`image quality. (Ex. 1001, Fig. 1, 3—15). As the dummy wiring patterns serve no
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`electrical function, they are not electrically connected to the remainder of the
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`pixel array, or to the scan or signal drive circuit, or to each other. (Ex. 1001, col. 7,
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`II. 58—64).
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`301, 302, 303
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`FIG. 6
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`VII.
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`Claim Interpretation
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`(29)
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`In proceedings before the USPTO, I understand that the claims of
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`an unexpired patent are to be given their broadest reasonable interpretation in
`
`view of the specification from the perspective of one skilled in the art. l have been
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`informed that the ’978 patent has not expired. In comparing the claims of the
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`’978 patent to the known prior art, I have carefully considered the '978 patent,
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`and the ’978 file history based upon my experience and knowledge in the relevant
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`field.
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`I have not encountered any “coined” terms or terms that require
`
`consideration of a special or explicitly defined meaning. Instead, the claim terms
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`of the ’978 patent are used in their ordinary and customary sense as one skilled in
`
`the relevant field would understand them.
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`(30)
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`lam informed that the '978 patent is a division of U.S. Patent
`
`Application No. 10/811,920, filed on Mar. 30, 2004, which is a division of U.S.
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`Patent Application No. 09/316,697, filed on May 21, 1999, which is a division of
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`U.S. Patent Application No. 08/768,066, filed on Dec. 16, 1996. Additionally, ’978
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`patent claims priority to a foreign patent, Japanese Patent Application No. 07—
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`350229, filed on Dec. 21, 1995.
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`I am further informed that this means that the
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`’978 patent is considered to have been filed on Dec. 21, 1995 for purposes of
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`determining whether a reference constitutes prior art. Thus, a reference will
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`13
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`qualify as prior art if it disclosed or suggested the claimed invention of the ’978
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`patent prior to Dec. 21, 1995.
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`(31)
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`I have been informed that a patent claim can be found
`
`unpatentable as obvious where the differences between the subject matter
`
`sought to be patented and the prior art are such that the subject matter as a
`
`whole would have been obvious at the time the invention was made to a person
`
`having ordinary skill in the relevant field.
`
`I understand that an obviousness
`
`analysis involves a consideration of (1) the scope and content of the prior art; (2)
`
`the differences between the claimed inventions and the prior art; (3) the level of
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`ordinary skill in the pertinent art; and (4) secondary considerations of non—
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`obviousness.
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`VIII. U.S. Patent No. 5,513,028 to Sono et al. (”Sono," Ex. 1003) , and in
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`combination with the Admitted Prior Art of the '978 patent
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`(32)
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`l have been asked to consider the Sono reference, and to compare
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`the teachings of Sono to claims 7 and 17 of the ’978 patent. Sono is directed to
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`an LCD device, the same field of endeavor as the '978 patent. Sono also attempts
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`to solve the very same problem described in the ’978 patent, in the very same
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`manner.
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`(33)
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`Figs. 16 and 17 of the ’978 patent (designated ”Prior Art" by the
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`14
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`Patentee) illustrate what I understand to be well established LCD structures that
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`were known to be in existence prior to the December 21, 1995. For example, the
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`very same standard LCD device structures are found in the Sono reference (e.g.,
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`Figs. 4, 7—8). As such, I have been informed that to the extent aspects of Figs 16-17
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`are referenced in claims 7 and 17, they are deemed to be ”old” or ”Admitted Prior
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`Art." And,gin any event, these features are also shown by Sono. I identify the first
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`8 paragraphs of claims 7 and 172 of the '978 patent as referencing such standard
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`features.
`
`(34)
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`Claims 7 and 17 of the ’978 patent allege to present entirely new
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`features at paragraph 9 of claims 7 and 17, which begins with the language ”at
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`least first and second conductive layers .
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`.
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`.”
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`(35)
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`Sono explains that LCD devices can exhibit a non uniform gap
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`about a seal area 32. This gap (shown below in Fig. 1 of Sono) is described as
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`being caused by the formation of the seal over peripheral circuits 31. (Ex. 1003,
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`col. 1, II. 36-45).
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`
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`2Claim 17 is identical to claim 7 in all respects but one, it recites an additional
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`”black matrix” element. This element is also admitted as prior art in the
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`background of the ’980 patent (Ex. 1001 Col. 2, II. 59-64). As with the other
`standard LCD device elements noted above, Sono describes the same element
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`(Ex. 1003 at Col. 3, II. 64-67).
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`15
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`FIG. 7 PP/OAJ ART
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`
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`(36)
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`The Sono patent describes how to create a uniform gap by
`
`forming a ”dummy area." ”More specifically, in said dummy area there may be
`
`formed dummy pixels of a same configuration, having same wirings, switching
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`elements, pixel electrodes, etc. as in the display area. In such case, the pixel
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`electrodes are preferably insulated electrically in order to avoid unnecessary
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`voltage application." (Ex. 1003, Sono, col. 3, II. 18—23). "By surrounding the
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`display area with a dummy area... image display with high quality can be
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`attained." (Ex. 1003, col. 4, II. 27—31).
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`(37)
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`Sono also describes that a uniform gap or step may be formed by
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`dummy circuits or wiring.
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`”Also in the present invention, said step may be
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`formed by the circuit elements or wiring provided in the peripheral area.” Sono,
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`(Ex. 1003, col. 3, II. 28-30). As shown below in annotated Fig. 7, (sectional
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`perspective shown adjacent in annotated Fig. 8) Sono remedies the unevenness
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`shown in Fig. 1 above by, adding a horizontal dummy scanning circuit 74 and a
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`16
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`vertical dummy scanning circuit 75. Each of the dummy circuits 74 and 75 are
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`formed by the same process, and have the same ”step" or height as that of the
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`actual horizontal and vertical scanning circuits 72 and 73. (Ex. 1003, Sono, col. 5,
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`ll. 1-13). ”Furthermore excellent producibility is ensured because the dummy
`
`circuits 74, 75 can be prepared in a same process as for the peripheral scanning
`
`circuits 72, 73." (Ex. 1003, Sono, col. 6, II. 33-36).
`
`(38)
`
`One skilled in the art would recognize that the horizontal and
`
`vertical scanning circuits 72 and 73 of Sono’s Fig. 7, are the same as the horizontal
`
`and vertical shift registers 5 and 6 of Sono’s Fig. 4; ”... a horizontal shift register 5;
`
`a vertical shift register 6,.." (Ex. 1003, Sono, col. 4, ll. 19—20). As such the dummy
`
`circuits 74 and 75 will also be dummy shift registers, i.e. circuits that would
`
`contain same wirings and devices as an ordinary shift register.
`
`HE. S
`
`
`
`17
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`CMI Exhibit 1005
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`Page 17
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`CMI Exhibit 1005
`Page 17
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`
`
`(39)
`
`As explained above in paragraph 25 , the wiring of a typical shift
`
`register includes multiple, long conducting lines, along the side of the display the
`
`shift register is driving, formed from the metal layer used in the formation of the
`
`signal lines. Therefore, an ordinary skilled in the art would recognize that a cross
`
`sectional view of a shift register will include the cross sections of the multiple
`
`conducting lines that run along the entire length of the shift register. The
`
`annotated Fig. 8 above shows the cross section of the multiple conducting lines
`
`which a person skilled in the art would recognize as been formed from the same
`
`layer as the signal lines. Therefore, dummy circuits 74 and 75 include at least first
`
`and second conductive layers formed from a same layer as the second conductive
`
`lines. Sono specifically states that ”...dummy circuits 74, 75 can be prepared in a
`
`same process as for the peripheral scanning circuits 72, 73.” (Ex. 1003, Col. 6,
`
`ll.
`
`35-37).
`
`(40)
`
`Sono further describes that the dummy area is formed of a same
`
`"configuration, having same wirings, switching elements, pixel electrodes etc. as
`
`in the display area... the manufacturing process of the pixels in the display area
`
`can be merely expanded and the additional steps are not required.” (Ex. 1003,
`
`Col. 3, II. 17-27) (emphasis added) As Sono has shown "[t]he liquid crystal sealing
`
`area may be provided on an area of a substantially same step height as that of the
`
`18
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`CMI Exhibit 1005
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`Page 18
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`CMI Exhibit 1005
`Page 18
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`
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`display area, and may naturally be provided non only on circuit elements but also
`
`on wirings or dummy areas of a same step height." Ex. 1003, col. 7 II. 38-41). "In
`
`addition the shape of the step, to be formed adjacent to the pixel area, may be
`
`made same as, substantially same as or similar to that of said pixel area by a
`
`dummy area, a circuit element or a wiring alone or by the combination thereof."
`
`(Ex.1003,Sono col., 7 II. 46-50) (emphasis added).
`
`(41)
`
`I see no discernible difference between the above
`
`described/illustrated ”dummy areas” of Sono and the ”dummy wirings"
`
`described in ’978 patent. Furthermore, I see no difference between the
`
`conductive layers within the dummy area of Sono and paragraph 9 of claims 7 and
`
`17 of the “978 patent, which require ”at least first and second conductive layers
`
`formed from a same layer as the plurality of second conductive lines, wherein at
`
`least a part of each of the first and second conductive layers is overlapped with
`
`the portion of the sealing member."
`
`(42)
`
`Paragraph 10 of claim 7 and paragraph 11 of claim 17 require: ”a
`
`length of the first conductive layer along the first direction and a length of the
`
`second conductive layer along the first direction are longer than a pitch of
`
`adjacent ones of the plurality of second conductive lines.” As illustrated by the
`
`annotated arrow of Fig. 7 below, Sono describes the length of the first and second
`
`19
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`CMI Exhibit 1005
`
`Page 19
`
`CMI Exhibit 1005
`Page 19
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`
`
`conductive layers being greater than a ”pitch," or distance between, adjacent
`
`second conductive lines (Fig. 4, (element 1); Fig. 7, vertical signal lines). As
`
`explained above in Paragraph 39, along the length of the dummy circuit 74 there
`
`will be the first and second conductive layers. As illustrated in Fig, 7, along the
`
`length of the dummy circuit 74 there will be many second conductive lines or
`
`column signal lines and thus along the first direction of the substrate both
`
`conductive layers are longer than the pitch of second conductive lines.
`
`Indeed,
`
`aside from the clear teaching from the figures below, Sono explicitly explains that
`
`”[t]he width of such step may vary depending upon the case, but, in case of said
`
`dummy pixels, sufficient effect can be attained with a width corresponding, fo_r
`
`
`
`exam le to five scannin lines or dis la lines.” (Ex. 1003, col. 3, II. 40-43).
`
`(emphasis added)
`
`FIG. 7
`
`72
`
`71
`
`76
`
` BI
`
`(43)
`
`The final paragraph of claims 7 and 17 require that “the first and
`
`second conductive layers are electrically isolated from both of the plurality of first
`
`20
`
`CMI Exhibit 1005
`
`Page 20
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`CMI Exhibit 1005
`Page 20
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`
`
`conductive lines and the plurality of second conductive lines, and wherein the
`
`first and second conductive layers are electrically isolated from each other." Sono
`
`describes that ”[e]ach dummy pixel is in an electrically insulated state, by not
`
`making the contact between the gate or source of the TFT element 3 and the
`
`scanning line 2 or the display line 1.” (Ex. 1003, col. 4, ll. 22—24). Dummy circuits
`
`74 and 75 of Fig. 7 include first and second conductive layers. For example, as
`
`shown in Fig. 7, dummy circuits 74 and 75 are shown as electrically isolated from
`
`the horizontal and vertical scan lines (i.e., first and second conductive lines). As
`
`there is no electrical function to the dummy circuits, naturally, the first and
`
`second conductive layers are electrically isolated from each other. Furthermore,
`
`as dummy structures are known in the art as being provided for structural
`
`purposes and that serve no electrical function, it is well understood that such
`
`structures are designed to be electrically isolated to reduce unnecessary power
`
`consumption and switching transients.
`
`(44)
`
`Having now explained my assessment of the scope and content of
`
`the APA and Sono, I find that the APA provides all of the elements of claims 7 and
`
`17 save those discussed above in paragraphs 33—42; however those features are
`
`clearly taught by Sono (along with the very same APA features).
`
`(45)
`
`I understand the APA to be naturally combinable with the
`
`21
`
`CMI Exhibit 1005
`
`Page 21
`
`CMI Exhibit 1005
`Page 21
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`
`
`teachings of Sono as both are directed to the same field of endeavor and both
`
`attempt to solve the same problem of non-uniform gap in the seal area between
`
`the two substrates of an LCD device. To account for the non—uniformity in the
`
`seal, Sono explains that dummy circuits or wiring patterns that are electrically
`
`insulated from active circuitry can be utilized to account for ”steps” in the heights
`
`of structures about the seal region. Likewise, Sono describes that the dummy
`
`circuits or wiring patterns should be dimensioned to account for the necessary
`
`geometries of the LCD device, and may be formed at the same time, layer-by layer
`
`with the active pixel region and the peripheral scanning circuits of the LCD device.
`
`(Ex. 1003, col. 3, II. 17-27; col. 4, II. 22—24; col. 5, M. 1-13; col. 6, II. 33—36; col., 7 II.
`
`46-50 and Figs 4—8.
`
`(46)
`
`As the dummy wiring pattern arrangement of Sono existed prior
`
`to the ’978 patent for solving the problem presented in the ’978 patent, it would
`
`have taken only ordinary skill to adopt this solution to account for a step created
`
`by circuit, scan or display line structure of an LCD device. As demonstrated by
`
`Sono, such equalization in structure dimensions was known to result in a uniform
`
`gap during LCD device construction, yielding an improved reliability, better image
`
`quality and display contrast, low power consumption, and excellent producibility
`
`without expansion of the LCD device size.
`
`22
`
`CMI Exhibit 1005
`
`Page 22
`
`CMI Exhibit 1005
`Page 22
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`
`
`IX.
`
`APA in view of U.S. Patent No. 5,504,601 to Watanabe et al. (”Watanabe,"
`
`Ex. 1004) and Sono
`
`(47)
`
`l have been asked to consider the admitted prior art of the ’978
`
`patent together with Watanabe and Sono, and to compare these combined
`
`teachings to claims 7 and 17 of the ’978 patent.
`
`(48)
`
`As noted above in paragraph 33, to the extent aspects of Figs 16—
`
`17 are referenced in claims 7 and 17, they are deemed to be "old” or ”Admitted
`
`Prior Art.” I identify the first 8 paragraphs of claims 7 and 173 as referencing such
`
`standard features of Figs. 16—17. Features not necessarily found in these figures,
`
`or described in the accompanying descriptions of these figures, begin at
`
`paragraph 9 of claims 7 and 17, which begins with the language ”at least first and
`
`second conductive layers. .
`
`(49)
`
`Watanabe is directed to an LCD device, the same field of
`
`endeavor as the ’978 patent. Watanabe also a describes (shows or teaches) how
`
`to solve the very same problem described in the '978 patent, in the very same
`
`3Claim 17 is identical to claim 7 in all respects but one, it recites an additional
`
`”black matrix” element. This element is also admitted as prior art in the
`
`background of the ’980 patent (Ex. 1001, Col. 2, II. 59—64). As with the other
`
`standard LCD device elements noted above, Sono describes the same element.
`
`(Ex. 1003, Col. 3, II. 64-67).
`
`23
`
`CMI Exhibit 1005
`
`Page 23
`
`CMI Exhibit 1005
`Page 23
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`
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`manner.
`
`(50)
`
`Watanabe explains that LCD devices can exhibit an unequal gap
`
`between two substrates (see generally Fig. 9 below of Watanabe showing the
`
`prior art). This unequal gap is described as being caused by the formation of the
`
`sealing member 511 over different elements of the display, such as the scanning
`
`lines 509 and signal lines 505. (Ex. 1004, col. 2, ll. 30-67; and col. 3, ll. 1-15).
`
`
`
`
`
`
`
`_
`
`j E! 505 =.
`L
`599
`
`
`
`
`Ԥ_J
`L
`
`L__ 505 ,
`
`
`509
`
`515
`
`507
`_
`
`503
`
`5
`
`505
`
`l
`
`j
`i
`
`515
`
`1‘1,
`
`513
`
`FIG. 9
`PRIOR ART
`
`(51)
`
`Watanabe accounts for the unevenness above by forming
`
`”substrate gap adjusting regions or layers" in areas under the sealing member.
`
`The substrate gap adjusting layers are also formed using the same elements as
`
`those of the display area, and when the substrate gap adjusting layers is
`
`conductive it should be patterned and insulated as to avoid short circuiting with
`
`24
`
`CMI Exhibit 1005
`
`Page 24
`
`CMI Exhibit 1005
`Page 24
`
`
`
`the scanning and signal lines. (Ex. 1004, col. 4, II. 37-39; col. 4, “47-54; col. 5, II.
`
`54—61).
`
`(52)
`
`As shown in annotated Fig. 5 below, Watanabe includes first and
`
`second substrate gap adjusting layers 25 and 27 having conductive layers to
`
`remedy the issues of unequal gaps between the two substrates. Substrate gap
`
`adjusting layers 25 and 27 are formed by the same materials of the display area,
`
`including the materials of scanning line 9,
`
`layer insulating film 201 (not shown in
`
`Fig.5), signal line 5, and protecting film 205 (not shown in Fig.5). By using the
`
`same materi
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