UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INNOLUX CORPORATION
`Petitioner,
`
`v.
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner.
`
`Case IPR2013-00038
`U.S. Patent 7,956,978
`
`PETITIONER’S REPLY TO RESPONSE OF THE PATENT OWNER
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INNOLUX CORPORATION
`Petitioner,
`
`v.
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner.
`
`Case IPR2013-00038
`U.S. Patent 7,956,978
`
`PETITIONER’S REPLY TO RESPONSE OF THE PATENT OWNER
`
`
`
`
`
`
`II. The '978 Patent is Unpatentable over the APA in view of Sono and Watanabe 11
`
`
`C. Sono discloses electrically isolated conductive layers .......................... 7
`
`D. Sono discloses conductive layers longer than a pitch ......................... 10
`
`A. One of ordinary skill would combine Watanabe with Sono ............... 11
`
`B. Watanabe discloses electrically isolated first and second conductive
`layers made from the same layer as the second conductive lines ....... 12
`
`
`
`
`
`TABLE OF CONTENTS
`
`
`
`
`
`I. Claim 7 and 17 of the '978 Patent are Unpatentable Over Sono .......................... 1
`
`
`A. Sono discloses first and second conductive layers ................................ 1
`
`B. Sono discloses first and second conductive layers formed from the
`same layer as the driving and scanning lines 1, 2 ................................. 5
`
`1. Watanabe's electrically isolated first and second conductive
`layers ............................................................................................. 12
`
`2. Watanabe's gap adjusting layers are made from the same layer
`as the second conductive line ........................................................ 14
`
`3. Watanabe's gap adjusting layers are longer than a pitch of
`adjacent second conductive lines .................................................. 14
`
`
`III. Conclusion ....................................................................................................... 16
`
`
`
`
`
`i
`
`
`
`
`
`EXHIBIT LIST
`
`Previously Filed
`
`
`Exhibit 1003
`
`U.S. Patent No. 5,513,028 to Sono et al. 1004.
`
`Exhibit 1004
`
`U.S. Patent No. 5,504,601 to Watanabe et al.
`
`Exhibit 1005
`
`Declaration of Miltiadis Hatalis, Ph.D.
`
`Exhibit 2011
`
`Declaration of Roger G. Stewart
`
` Currently Filed
`
`
`Exhibit 1012
`
`Exhibit 1013
`
`Exhibit 1014
`
`Deposition transcript of Miltiadis Hatalis, Ph.D. dated May
`20, 2013
`
`Declaration of Miltiadis Hatalis, Ph.D. in support of Innolux
`Corp.'s Opposition to Amendment and Reply
`
`Deposition transcript of Roger G. Stewart dated August 22,
`2013
`
`
`
`
`ii
`
`
`
`
`Petitioner Innolux Corporation ("Innolux") hereby provides its reply to
`
`
`
`Patent Owner Semiconductor Energy Laboratory Co., Ltd.'s ("SEL" or "Patent
`
`Owner") response to the Decision to Initiate Trial for Inter Partes Review of
`
`claims 7 and 17 of United States Patent No. 7,956,978 ("the '978 Patent").
`
`I.
`
`
`
`Claim 7 and 17 of the '978 Patent are Unpatentable Over Sono
`
`Sono discloses first and second conductive layers
`
`A.
`Sono teaches making the peripheral circuits (i.e. scanning, driving and
`
`dummy circuits 72-75) the same to achieve a uniform substrate-to-substrate gap
`
`claimed in the '978 patent. These peripheral circuits are made in the "same
`
`process," with the "same step" and, as shown in Figures 7 and 8, have the same
`
`physical layout dimensions. See Deposition transcript of Miltiadis Hatalis, Ph.D.
`
`dated May 20, 2013 ("Ex. 1012") at 17:23-18:17 and 146:2-9; Ex. 1003, col. 5, ll. 6-
`
`11 and col. 6, ll. 28-37 ("[E]xcellent producibility is ensured because the dummy
`
`circuits 74, 75 can be prepared in a same process as for the peripheral scanning
`
`circuits 72, 73.").
`
`
`
`Sono also teaches that "dummy pixels of a same configuration, having same
`
`wirings, switching elements, pixel electrodes etc. as in the display area…." Ex.
`
`1003, col. 3, ll. 17-27. While Petitioner does not rely on the dummy pixels of Sono
`
`for the disclosure of the claimed "first and second conductive lines," someone of
`
`ordinary skill in the art would understand that Sono's disclosure of making the
`
`dummy pixels exactly the same as the actual pixels would apply to creating dummy
`
`
`
`
`1
`
`
`
`
`circuits exactly the same as the real circuits. Declaration of Miltiadis Hatalis, Ph.D.
`
`in support of Innolux Corp.'s Opposition to Amendment ("Ex. 1013"), ¶¶ 35-39.
`
`
`
`Dr. Hatalis testified that a person of ordinary skill in the art would understand
`
`that the peripheral dummy circuit area includes long conductive layer runs along
`
`dummy shift register circuits, based on Sono's teaching that the dummy circuits
`
`mirror the peripheral shift register circuits 72 and 73. Ex. 1005, ¶¶ 25, 38, 39; see
`
`also Ex. 1012 at 16:18-18:17; Ex. 1013, ¶¶ 41, 43-45. SEL's expert agreed that it
`
`was known to use shift registers as drive circuits. Deposition transcript of Roger G.
`
`Stewart dated August 22, 2013 ("Ex. 1014") at 209:19-210:4. And, that such shift
`
`registers have long conductive layer runs including power lines, ground lines and
`
`clock lines. Ex. 1012 at 60:18-65:24 and 130:4-21; Ex. 1013, ¶¶ 43-45; Ex. 1014 at
`
`98:5-100:20. Mr. Stewart illustrated the long conductive runs contained in shift
`
`registers and agreed that these wirings span the length of the display. See Ex. 2011
`
`at p.44, ¶ 100 (showing long conductive runs contained in the shift registers); Ex.
`
`1014 at 98:5-100:20. These long conductive layer runs serve as the claimed first
`
`conductive layer (e.g., power line or Clock 1 line) and the second conductive layer
`
`(e.g., ground line or Clock 2 line). Ex. 1012 at 60:18-65:24 and 130:4-21.
`
`
`
`SEL argues that one of ordinary skill in the art would understand that forming
`
`the dummy circuits to have the "same step" means that they would have the same
`
`height under the sealant as scanning circuits 72 and 73, but not necessarily the same
`
`configuration. Resp. at 23. In doing so, SEL ignores Sono's express teaching that
`
`
`
`
`2
`
`
`
`
`the peripheral circuits 72-75 be made the same, and with the same step. Id., Ex.
`
`1005, ¶¶ 24-25; Figs. 7 and 8. For example, Sono shows an embodiment where
`
`scanning circuits 83 and 85 are formed using the same size and configuration as
`
`circuits 82 and 84. Id., Ex. 1005, Fig. 10. Sono also teaches that dummy circuits
`
`74, 75 are created during the same process used to create peripheral scanning
`
`circuits 72, 73 and that the sealant 76 overlaps circuits 72-75 to produce a uniform
`
`crystal gap between substrates 78 and 79. Ex. 1003, col. 6, ll. 28-37. Thus, Sono
`
`discloses to a person of ordinary skill in the art that dummy circuits 74, 75 should
`
`be made using the same process and the same configuration in order to achieve
`
`Sono's goal of excellent producibility of dummy circuits to insure a uniform gap
`
`across the substrate in the sealing area. Ex. 1013, ¶¶ 38-40.
`
`
`
`SEL fails to provide a reason why one would make the internal structure of
`
`dummy circuits 74 and 75 different than that of scanning circuits 72 and 73. To the
`
`contrary, one of ordinary skill in the art would know that the simplest way to create
`
`peripheral circuits having the same surface topology or step would be to use the
`
`same circuit. See Ex. 1012 at 18:1-19; Ex. 1013, ¶¶ 38-40. Using the same internal
`
`structures would have the advantages of symmetry and design efficiency, whereas
`
`making them different would require designing a new mask and changing the
`
`fabrication steps. Ex. 1012 at 18:8-17 and 162:3-163:15. There is no reason why
`
`one of ordinary skill would choose this more burdensome design. Id. at 163:10-15.1
`
`
`1 SEL asserts that there are differences between the scanning circuits 72 and 73.
`3
`
`
`
`
`
`
`
`SEL argues that creating dummy circuits with shift registers and long
`
`
`
`conductive layers contradicts Sono's objective of achieving uniform cell gap without
`
`expansion of chip size. Resp. at 24. According to SEL, one would not form the
`
`long conductive lines to save space because TFTs have the highest point and thus
`
`only the TFTs of the scanning circuits, and not the conductive runs (e.g., power,
`
`ground and clock lines), are needed to create the same step height. Id. SEL ignores
`
`that the highest points are those with the long conductive runs held over the TFTs.
`
`Ex. 1013, ¶ 41. In fact, the gap height is dominated by the thickness of the wirings,
`
`which is 90% of the thickness of the combined structure. Id. In addition, the
`
`wirings extend across the display while the TFTs are localized and thus provide less
`
`uniform coverage under the sealing area. As a result, removing either the TFT or
`
`the long conductive run from the dummy circuit, as SEL urges, would result in non-
`
`uniform cell gap and contrary to Sono's purpose for using dummy circuits. Id.
`
`
`
`Sono also does not disclose reducing chip size by modifying dummy circuits
`
`74, 75 to reduce their size. To the contrary, Sono explicitly teaches that dummy
`
`circuits 74, 75 are prepared using the same process as scanning circuits 72, 73. Ex.
`
`1003, col. 6, ll. 34-37. Sono teaches that the chip size can be reduced by placing the
`
`
`Resp. at 23. From this, SEL concludes that there must be differences between
`
`between circuits 72 and 73 and dummy circuits 74 and 75. SEL fails to explain how
`
`such differences, if true, detract from Sono's clear disclosure of forming the dummy
`
`circuits 74, 75 using the same process, at the same time as circuits 72, 73.
`4
`
`
`
`
`
`
`
`sealing material over scanning circuits 72, 73 and dummy circuits 74, 75 precisely
`
`because they are made to have the same size and configuration, and not by reducing
`
`the size or shape of the dummy circuits. Id., col. 6, ll. 28-37. SEL's suggestion that
`
`the process for creating dummy circuits 74, 75 should be modified in a way that
`
`would be different from the process for creating scanning circuits 72, 73 runs the
`
`risk of forming uneven steps and poor producibility between the two sets of circuits.
`
`Id.; Ex. 1013, ¶¶ 38-41. SEL's suggestion is contrary to Sono's express teaching.
`
`B.
`
`Sono discloses first and second conductive layers formed from
`the same layer as the driving and scanning lines 1, 2
`
`
`
`
`
`
`Sono teaches that minimal process steps should be used to create uniform
`
`wiring and metal steps across the sealant region. Ex. 1003, col. 3, ll. 1-6. Sono's
`
`teaching of using minimal process steps to create uniform wiring across the sealant
`
`gap suggests to one of ordinary skill in the art to make the peripheral circuits 72-75
`
`from the same layer as the driving and scanning lines 1, 2. See Pet. at 19-23; see
`
`also Decision at 15. Figure 8, for example, shows that there are lines in two
`
`different metal layers contained with the dummy circuit, which would correspond to
`
`the driving and scanning lines. Id., Fig. 8; Ex. 1013, ¶ 45. Figure 4 also shows that
`
`such driving and scanning lines 1, 2 extend from the display area to the shift
`
`registers. Extending the driving and scanning lines 1, 2 to form wirings within the
`
`dummy circuits minimizes the process steps. Ex. 1013, ¶ 45. Accordingly, a person
`
`of ordinary of skill would understand that the dummy circuits would contain wirings
`
`formed from the same layer as the driving and scanning lines 1, 2. Id.
`5
`
`
`
`
`
`
`
`SEL ignores these teachings and simply responds that Sono does not
`
`
`
`disclose how the scan and driving lines are formed and therefore it cannot
`
`disclose the claimed feature. Resp. at 27-30. SEL’s conclusion, however, is
`
`contrary to Sono's disclosure (discussed above) reflecting that a person of
`
`ordinary skill in the art would understand that the long power lines in the
`
`dummy circuits could be made of either the scanning or data line material, or
`
`both, as shown in Figure 8. Ex. 1012 at 69:18-70.2; Ex. 1013, ¶ 45.
`
`SEL next responds that Sono teaches away because dummy circuits 74
`
`and 75 have long edge lines traversing the sealant wherein metal-insulator-
`
`substrate interferences could allow more moisture to enter the pixel area. Resp.
`
`at 30-31. The long conductive lines in the dummy circuits, however, are shown
`
`in Figure 7 as being contained within the dummy circuit entirely under the
`
`sealing area and not extending beyond the sealing area. Ex. 1003, Fig. 7. SEL's
`
`own expert also depicts shift registers that have long conductive lines that do
`
`not extend beyond the circuit. Ex. 2011, at 44, ¶ 100. In this arrangement,
`
`contrary to SEL’s assertion, moisture would not enter at the metal-insulator-
`
`substrate. Ex. 1013, ¶ 48.
`
`
`
`SEL argues that Figure 8 of Sono fails to teach that dummy circuits are
`
`formed from the same layer as the second conductive lines because the
`
`"rectangular blocks" in elements 73 and 75 are transistors made of
`
`semiconductor substrate 78, not conductive metal layers. Resp. at 31-32.
`
`
`
`
`6
`
`
`
`
`However, Sono's disclosure indicates otherwise. Sono describes elements 73
`
`and 75 as corresponding to vertical scanning circuits and vertical dummy
`
`circuits, respectively, not TFT components as SEL alleges. See Ex. 1013, ¶¶
`
`41-42; see also Decision at 14 (citing Ex. 1003, col. 5, 11. 1-13; col. 6, ll. 27-
`
`37). Elements 73 and 75 relate to circuit regions (i.e. conductive layers) along
`
`the peripheries of the LCD lower substrate and under the sealant 76 as depicted
`
`in Figures 7 and 8. Id.; see also Ex. 1012 at 131:4-132:1 and 145:21-147:18.2
`
`Moreover, Sono discloses that the substrate can be glass, which is inconsistent
`
`with SEL’s interpretation of 73 and 75 being TFTs formed in a silicon substrate.
`
`Ex. 1003, col. 6, ll. 23-27; Ex. 1013, ¶ 42. Sono thus discloses wirings
`
`extending over the length of the silicon or glass substrate. Ex. 1013, ¶¶ 41-45.
`
`Sono discloses electrically isolated conductive layers
`
`C.
`Sono provides numerous teachings for electrically isolating different dummy
`
`
`
`
`
`structures from one another and from conducting lines. First, a person of ordinary
`
`skill in the art would be well aware that electrical isolation conserves power and that
`
`dummy circuits are naturally isolated because they are used for structural purposes
`
`
`2 The cross-section shown in Figure 8 is an arbitrary cross-section of Figure 7. An
`
`arbitrary line always will show the long conductive wirings extending across the
`
`substrate at any point along the substrate, but would not always show TFT cross-
`
`sections because they exist in insulated regions. Ex. 1013, ¶ 41. This further
`
`supports that elements 73 and 75 are long wirings and not portions of TFTs. Id.
`7
`
`
`
`
`
`
`
`and have no electrical function. Ex. 1005 at ¶ 47; Ex. 1012 at 78:15-79:14 and
`
`95:17-96:12. A person of ordinary skill in the art would understand that electric
`
`isolation or insulation means "not connected to electricity or to power." Ex. 1012 at
`
`96:21-24. SEL’s expert agreed with Dr. Hatalis. See Ex. 1014 at 15:20-16:4
`
`(“[Dummy structures] serve no electrical function within – within the display. They
`
`are always isolated from the power lines so they’re – they’re not powered.”). Thus,
`
`Sono's "dummy" structures would be understood by a person of ordinary skill in the
`
`art to have long conductive lines that are electrically isolated.3
`
`
`
`Sono also depicts isolated dummy circuits 74 and 75 in Figure 7 (which are
`
`isolated from the horizontal and vertical scan lines), and teaches "locally cutting off
`
`the wiring" within dummy pixel circuits to create electrical isolation from driving
`
`and scanning lines. Ex. 1003, col. 3, ll. 47-51; Ex. 1012 at 103:20-104:15. Sono's
`
`also discloses that the dummy areas include pixel electrodes having "the same
`
`configuration having the same wirings, switching elements, pixel electrodes etc. as
`
`in the display area" and that these dummy pixel electrodes are "preferably insulated
`
`electrically in order to avoid unnecessary voltage application." Ex. 1003, col .3, ll.
`
`17-23. While this discussion refers to dummy pixels, a person of ordinary skill in
`
`the art would understand that Sono's teaching regarding electrically isolating
`
`
`3 Sono goes into more detail with respect to the dummy pixels, but that teaching is
`
`equally applicable to dummy circuits. Ex. 1013, ¶¶ 34, 37-38, 43; see also Ex. 1012
`
`at 79:15-81:17 and 95:17-96:12.
`
`
`
`
`8
`
`
`
`
`dummy pixels applies with equal force to electrically isolating Sono's dummy
`
`circuits. Ex. 1013, ¶¶ 46-47; see also Ex. 1003, col. 3, ll. 46-53; col. 4, ll. 23-25; Ex.
`
`1012 at 99:20-100:17; 97:1-17; 101:3-102:20.
`
`
`
` SEL argues that even if the dummy circuits are electrically isolated from the
`
`external circuits, the internal wirings in the dummy circuits 74 and 75 would remain
`
`electrically interactive or connected to each other through a conductive path (i.e.
`
`connected through transistors). Resp. at 33-38. According to SEL, the power,
`
`ground and clock lines can convey an electrical charge between them even when
`
`disconnected from an external power source because "electrical isolation" means
`
`"no electrical interaction, free floating and not connected by a conductive path."
`
`Resp. at 36. This definition, however, is both inaccurate and improperly narrow.
`
`
`
`First, clock lines are always in electrical isolation, regardless of whether they
`
`are active or inactive. Ex. 1013, ¶ 46. Second, when a transistor switch or power is
`
`off, there must be electrical isolation (otherwise the transistor cannot serve its
`
`purpose). Id. However, based on SEL's unorthodox definition of "electrical
`
`isolation," it would not exist in either of these examples. Id. Because SEL's
`
`definition contradicts fundamental principles of transistor operation and does not
`
`comport with its ordinary and customary meaning, it should be rejected. 4 Id.
`
`
`4 Transistors have two states: open switch (OFF) and closed switch (ON). In the
`
`open switch state there is no current path and thus no current flow across the
`
`transistor. See Ex. 1012 at 101:3-102:20. A threshold voltage, of typically 1 Volt
`9
`
`
`
`
`
`
`
`Second, shift registers typically have at least two clock lines. Ex. 1013, ¶ 44;
`
`
`
`Ex. 1014 at 137:2-5. In the dummy circuits of Sono's Figure 7, these clock lines
`
`serve as the first and second conductive layers. Id. It is well known to those of
`
`ordinary skill in the art that clock lines are electrically isolated from one another.
`
`Id. Accordingly, a person of ordinary skill would understand that the clock lines in
`
`each of dummy circuits 74, 75 would be internally isolated from one another. Id.
`
`In addition, because the clock lines are connected to the gate electrode in TFTs, and
`
`because the TFTs in the dummy circuits are not powered, the TFTs in their off state
`
`further electrically isolate the clock lines in the dummy circuits from each other. Id.
`
`Sono discloses conductive layers longer than a pitch
`
`
`
`D.
`Sono discloses the internal structure of the dummy circuits, which mirror the
`
`
`
`
`
`peripheral shift registers 72 and 73, include long continuous conductive layers. Ex.
`
`1003, Figs. 7 and 8; Ex. 1005, ¶¶ 25, 38, 39; see also Ex. 1012 at 16:18-18:17,
`
`60:18-65:24, 130:4-21; Ex. 1014 at 98:5-100:20, 209:19-210:4; Ex. 2011 at p.44, ¶
`
`100 (showing long conductive runs contained within the exemplary shift registers).
`
`These runs would, by their nature, extend the length of the shift register and thus
`
`meet the claims’ requirement that they are longer than the pitch of adjacent
`
`
`or greater, must be applied in order to place the transistor in close switch state in
`
`which it can conduct electricity. See id. Thus, at voltages below the threshold
`
`voltage, the transistor is in the open state and cannot conduct electric current and is
`
`therefore electrically isolated.
`
`
`
`
`10
`
`
`
`
`conductive lines. Ex. 1014 at 105:8-24 (“In the working circuits, …they would
`
`extend for a long distance parallel to that edge of the display.”); Ex. 1013, ¶ 46; Ex.
`
`1012 at 64:15-65:23.
`
`
`
`A person of ordinary skill in the art also would understand that Sono's
`
`teaching regarding the width of the step in the dummy pixel region being greater
`
`than the pitch of adjacent second conductive lines is equally applicable to the width
`
`of the step in the dummy circuits of Sono. Ex. 1013, ¶¶ 34, 37-38. SEL contends
`
`that Sono's disclosure regarding the dummy pixels cannot be applied to the dummy
`
`circuits because "the dummy pixels and dummy circuits have different functions
`
`and are located in different parts of the display." Resp. at 40. However, the
`
`difference in function and location is irrelevant to Sono's teaching, which is
`
`structural (i.e., to form dummy structures of a certain length that create uniform
`
`height under the sealant). Ex. 1013, ¶ 37. A person of ordinary skill would not
`
`confine Sono's teaching to a single embodiment, as SEL urges. Id. Accordingly,
`
`Sono discloses the claimed feature that the length of the long clock lines in the
`
`dummy shift registers is longer than the pitch of adjacent conductive lines.
`
`
`
`II. The '978 Patent is Unpatentable over the APA in view of Sono and
`
`Watanabe
`
`A. One of ordinary skill would combine Watanabe with Sono
`SEL argues that one of ordinary skill would not combine Watanabe and Sono
`
`
`
`due to differences in layout, i.e. because the relative position of the driver circuits to
`
`
`
`
`11
`
`
`
`
`the sealing area is different. Resp. at 44-45. However, as SEL’s expert explained,
`
`“Sono, also, like Watanabe and the ‘978, was also concerned with maintaining a
`
`uniform gap as well.” Ex. 1014 at 61:12-14; see also 105:25-106:2 (“So someone
`
`practicing – Sono or Watanabe, they’re very concerned about the step height being
`
`equal.”). In short, Watanabe and Sono are both directed at forming gap adjusting
`
`structures to provide a uniform substrate gap in LCD devices, so one of ordinary
`
`skill in the art would naturally look to combine their teachings. Ex. 1013, ¶ 52.
`
`B. Watanabe discloses electrically isolated first and second conductive
`layers made from the same layer as the second conductive lines
`1. Watanabe's electrically isolated first and second
`conductive layers
`
`
`
`Watanabe suggests forming long metal gap adjusting layers 25 or 27 (shown
`
`in Figure 5) along and between the conducting lines 17 and 18. See Decision at 22;
`
`Ex. 1012 at 167:9-16. The Board also found that Watanabe’s long patterns satisfy
`
`the claims’ length requirement:
`
`"[S]uch long gap patterns reasonably suggest lengths greater than the pitch
`
`between at least lines 17 in Figure 5, because Watanabe describes the patterns
`
`as "long patterns along the lead portions""
`
`See Decision at 22. In other words, as shown in Figure 1, Watanabe's gap adjusting
`
`layers 25 and 27 can be long rectangles instead of the small squares shown in Figure
`
`5. See Ex. 1012 at 167:17-168:10 and 171:3-21.
`
`
`
`
`12
`
`
`
`
`Watanabe further teaches that "the substrate gap adjusting layers 25 and 27
`
`
`
`may be formed in long patterns along with the lead portions 13, 17, and 18 (without
`
`contacting them.)" Ex. 1004, col. 13, ll.45-49 (emphasis added). As such, the
`
`substrate gap adjusting layers are electrically isolated from the lead portions. Id.
`
`
`
`SEL's responds that that gap adjusting layers would not electrically isolated
`
`because they would be electrically connected through lead portion 13. Resp. at 57.
`
`But, Watanabe expressly states that the gap adjusting layers "may be formed in long
`
`patterns along with the lead portions 13, 17, and 18 (without contacting them.)"
`
`Ex. 1004, col. 13, ll. 45-49 (emphasis added). A person of ordinary skill in the art
`
`would understand that if the material used to fabricate the substrate gap adjusting
`
`layers 25 and 27 is made to be different than that of the lead lines 17 and 13,
`
`respectively, then the gap adjusting layers can cross over the lead lines because they
`
`are at a different height level within the device. Id.; see also Ex. 1012 at 175:11-
`
`176:16. For example, the embodiment shown in Watanabe's Figure 1 shows gap
`
`adjusting layer 21 and lead line 13, and the corresponding cross-section of Figure
`
`2B shows that each of these elements is at a different level with an insulating layer
`
`201 between them. Ex. 1004, Figs. 1 and 2B. In such an embodiment, there is no
`
`risk of short-circuiting so there is no restriction on the length of the gap adjusting
`
`layer. Ex. 1012 at 175:11-176:16. One of ordinary skill in the art would understand
`
`that gap adjusting layers and conductive lines can be formed at different height
`
`levels within the device. Id. Accordingly, Watanabe discloses gap adjusting layers
`
`
`
`
`13
`
`
`
`
`25 or 27 whose length exceeds the pitch of the adjacent lead lines 13 or 17 and
`
`which are electrically isolated from each other and the lead lines.
`
`2. Watanabe's gap adjusting layers are made from the same
`layer as the second conductive line
`
`
`
`Moreover, SEL acknowledges that the gap adjusting layers 25 and 27 are
`
`formed from the same layers as conducting lines 5, 9, 13, and 17. See Prelim. Resp.
`
`54-55 ("substrate gap adjusting layers 25 and 27 are formed from the same layers as
`
`scanning lines 9 (and the lead portions 17) and signal lines 5 (and lead portions
`
`13)") (citing Ex. 1004, col. 12, ll. 49-56); see also Decision at 23. However, SEL
`
`wrongly assumes, for example, that this precludes the gap adjusting layers 25 from
`
`extending beyond lines 5 and 13 because they would be at the same level and thus
`
`short-circuit. As explained above, however, Watanabe teaches that the gap
`
`adjusting layers can be made of the same metal layer as the scanning or signal lines
`
`as long as they are on different levels. See Ex. 1004, Figs. 1 and 2B (showing gap
`
`adjusting substrate 21 at a different level than lead portion 13). Ex. 1013, ¶ 53.
`
`3. Watanabe's gap adjusting layers are longer than a pitch of
`adjacent second conductive lines
`
`
`
`
`SEL asserts that Watanabe does not disclose gap adjusting layers longer than
`
`a pitch of adjacent second conductive lines. Resp. at 46-56. However, SEL's
`
`position is based on an interpretation of first and second directions that is not
`
`supported in the specification. Id. at 46-56 (relying entirely on expert's assertion).
`
`A person of ordinary skill in the art would understand that the first and second
`
`
`
`
`14
`
`
`
`
`direction is based on the formation sequence of the first and second conductive lines
`
`disclosed in the '978 patent specification. Ex. 1013, ¶ 54. Hence, the direction of
`
`the lines is based on the order in which they are formed. The '978 specification
`
`teaches that the scanning lines are formed first with the signal lines formed second.
`
`Ex. 1001, col. 7, ll. 65-col. 8, ll. 9; Fig. 1 (showing scanning lines 106 run
`
`horizontally across the substrate in a first direction and signal lines 105 run
`
`vertically across the substrate in a second direction). Watanabe's substrate gap
`
`adjusting layers 25 satisfy the claimed length for the first and second conductive
`
`layer because Watanabe teaches that such gap adjusting layers can be formed "in
`
`long patterns along with the lead portions 13, 17, and 18 (without contacting
`
`them)." Ex. 1004, col. 13, ll. 45-49; see also col., 11:63-64 ("the widths of the
`
`substrate gap adjusting layers 21 and 23 may be equal to the width of the sealing
`
`member 19."). Thus, Watanabe teaches that gap adjusting layers can made longer
`
`than a pitch of adjacent second conductive lines, shown as lines 5 in Watanabe. Id.,
`
`Fig. 5; Ex. 1013, ¶54.
`
`
`
`SEL also concedes that Watanabe's gap adjusting layers can be made of the
`
`same layers as the signal lines 5. Resp. at 47. These gap adjusting layers also
`
`overlap with a portion of the sealing member 19 adjacent to first side edge. See e.g.,
`
`Fig. 5; Ex. 1012 at 185:5-190:29; Ex. 1013, ¶53. For these reasons, claims 7 and 17
`
`are obvious over the Admitted Prior Art in view of Sono and Watanabe.
`
`
`
`
`15
`
`
`
`III. Conclusion
`
`
`
`
`
`For the reasons explained above, the Board should determine that claims
`
`7 and 17 of the '978 patent are obvious.
`
`Dated: September 23, 2013
`
`
`
`Respectfully submitted,
`
`
`
`
`
`
`
`
`
`
`/Scott A. McKeown/
`Scott A. McKeown (Reg. No. 42,866)
`Lead Counsel for Petitioner
`Oblon, Spivak, McClelland, Maier &
`Neustadt, LLP
`1940 Duke Street
`Alexandria, VA 22314
`Tel: (703) 412-6297
`Fax: (703) 413-2220
`SMcKeown@oblon.com
`
`Gregory S. Cordrey (Reg. No. 190,144)
`Back-up Counsel for Petitioner
`Jeffer Mangels Butler & Mitchell LLP
`3 Park Plaza, Suite 1100
`Irvine, CA 92614
`Tel: (949) 623-7236
`Fax: (888) 712-3345
`gxc@jmbm.com
`
`Stanley M. Gibson
`Admitted pro hac vice
`Jeffer Mangels Butler & Mitchell LLP
`3 Park Plaza, Suite 1100
`Irvine, CA 92614
`Tel: (310) 201-3548
`Fax: (310) 712-8548
`smg@jmbm.com
`
`
`16
`
`
`
`
`
`CERTIFICATE OF SERVICE
`
`I hereby certify that PETITIONER’S REPLY TO RESPONSE OF THE
`
`PATENT OWNER in connection with Inter Partes Review Case IPR2013-
`
`00038 was served on this 23rd day of September 2013 by electronic mail to
`
`Robinson Intellectual Property Law Office, P.C., Counsel for Patent Owner, at
`
`[erobinson@riplo.com], having a postal address at:
`
`Robinson Intellectual Property Law Office, P.C
`3975 Fair Ridge Drive
`Suite 20 North
`Fairfax, VA 22030
`
`
`
`
`
`/Scott A. McKeown/
`Scott A. McKeown (Reg. No. 42,866)
`
`
`
`
`
`
`17
`
`
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