IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
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`) TRIAL NO: IPR2013-00038
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`FILED ELECTRONICALLY
`) PER 37 C.F.R. § 42.6(ii)
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`In re Inter Partes Review of:
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`U.S. Patent No.
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`7,956,978
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`Issued:
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`Inventor:
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`Jun. 7, 2011
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`Hongyong Zhang
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`Application No.: 12/165,783
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`Filed:
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`Jul. 1, 2008
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`For: Semiconductor Energy
`Laboratory Co., Ltd.
`
`Mail Stop Patent Board (37 C.F.R. § 42.6(b)(2))
`Patent Trial and Appeal Board
`U.S.P.T.O.
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DECLARATION OF MILTIADIS HATALIS, Ph.D., IN SUPPORT OF
`INNOLUX CORP’S OPPOSITION TO MOTION TO AMEND AND
`REPLY TO RESPONSE OF PATENT OWNER
`
`I.
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`Background and Qualifications
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`(1) My name is Miltiadis Hatalis. I am currently a Professor at Lehigh
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`University in the Department of Electrical and Computer Engineering. I have
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`CMI Exhibit 1013
`Page 1
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`) TRIAL NO: IPR2013-00038
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`))
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`))
`
`))
`
`FILED ELECTRONICALLY
`) PER 37 C.F.R. § 42.6(ii)
`
`))
`
`In re Inter Partes Review of:
`
`U.S. Patent No.
`
`7,956,978
`
`Issued:
`
`Inventor:
`
`Jun. 7, 2011
`
`Hongyong Zhang
`
`Application No.: 12/165,783
`
`Filed:
`
`Jul. 1, 2008
`
`For: Semiconductor Energy
`Laboratory Co., Ltd.
`
`Mail Stop Patent Board (37 C.F.R. § 42.6(b)(2))
`Patent Trial and Appeal Board
`U.S.P.T.O.
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DECLARATION OF MILTIADIS HATALIS, Ph.D., IN SUPPORT OF
`INNOLUX CORP’S OPPOSITION TO MOTION TO AMEND AND
`REPLY TO RESPONSE OF PATENT OWNER
`
`I.
`
`Background and Qualifications
`
`(1) My name is Miltiadis Hatalis. I am currently a Professor at Lehigh
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`University in the Department of Electrical and Computer Engineering. I have
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`studied, taught, and practiced in the relevant flat panel display technology for over
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`25 years.
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`(2)
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`I received my Doctor of Philosophy (Ph.D.) degree in the field of
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`Electrical and Computer Engineering from Carnegie Mellon University in 1987.
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`The topic of my Ph.D. dissertation research was “Crystallization of Amorphous
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`Silicon Films and its Application in Bipolar and Thin Film Transistors.” I received
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`my Masters of Science (M.S.) degree in Electrical and Computer Engineering in
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`1984 from the State University of New York at Buffalo and my Bachelor of
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`Science (B.S.) degree in Physics in 1982 from the Aristotle University of
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`Thessaloniki in Greece.
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`(3) Upon receiving my Ph.D. degree, I joined the faculty of Lehigh
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`University in the Department of Electrical and Computer Engineering as an
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`Assistant Professor. I was promoted to the rank of Associate Professor with tenure
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`in 1991 and to the rank of Professor in 1995. From 1987-1992, I served as
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`Associate Director of Lehigh's “Microelectronics Research Laboratory.”
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`(4)
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`In 1992, I founded and became Director of the “Display Research
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`Laboratory,” which was the first academic laboratory in the United States
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`dedicated to research and development of Thin Film Transistors (TFTs) for Active
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`Matrix Liquid Crystal Displays (AMLCDs) and Active Matrix Organic Light
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`Emitting Diode (AMOLEDs) displays. As Director of Lehigh's “Display Research
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`Laboratory,” I have raised over $13 million through research contracts and grants
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`to support the laboratory's research and development activities on thin film
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`transistors and their application to flat panel displays. These contracts and grants
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`were funded by the Defense Advanced Research Program Agency (DARPA), the
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`Army Research Laboratory (ARL), the National Science Foundation (NSF), the
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`National Aeronautics and Space Administration (NASA), the State of
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`Pennsylvania, and a variety of industrial companies including IBM, Kodak, Sharp,
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`Corning, Northrop Grumman, Qualcomm, Air Products, Alcoa and others.
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`(5)
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`Since becoming a faculty member in 1987, I supervised the research
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`of eighteen Ph.D. dissertations in the technical field of TFTs and, along with my
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`graduate students, published over 150 technical publications in scientific journals
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`and conferences in the field of thin film transistors and their applications in flat
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`panel displays.1 In addition to the aforementioned Ph.D. dissertations, I have also
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`supervised a large number of graduate student master's theses and undergraduate
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`research projects. I currently supervise the research of three PhD students and one
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`post-doctoral research associate. I have taught a number of different
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`undergraduate and graduate level courses in the Electrical and Computer
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`Engineering department at the Lehigh University dealing with the physics,
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`1 More information on this subject can be found on my research group web
`pages: www.ece.lehigh.edu/DRL
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`technology, and the design of solid-state devices and circuits, including
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`“Semiconductor Material and Device Characterization,” “Introduction to VLSI
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`Circuits" and “Introduction to VLSI Design.”
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`(6) As part of my research, I utilize much of the same equipment and
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`many of the same fabrication processes that are relevant to U.S. Patent No.
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`7,956,978 (hereinafter referred to as the "’978 patent"), including: Plasma-
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`Enhanced Chemical Vapor Deposition (PECVD) for intrinsic hydrogenated-
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`amorphous silicon, silicon nitride and silicon dioxide films; sputter and e-beam
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`deposition tools for aluminum, indium-tin-oxide, tantalum and other metallic thin
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`films; photolithographic tools for spinning, exposure and developing photoresist;
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`as well as plasma or wet etching tools for removing various thin film materials
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`from the substrate. Furthermore, I also utilize several tools for the characterization
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`of the materials and structures used in thin film transistors including: optical
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`microscopes, Scanning Electron Microscopy (SEM), Transmission Electron
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`Microscopy (TEM), and Atomic Force Microscopy (AFM). I also utilize a variety
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`of electrical characterization techniques and instruments for testing the electrical
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`performance of completed TFT circuits and flat panel displays.
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`(7) As part of my research, I pioneered a technique for crystallizing
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`amorphous silicon. The technique I pioneered has been used in the manufacture of
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`small polysilicon TFT AMLCDs for projection displays. My research group in
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`collaboration with industrial laboratories has pioneered the use of polysilicon TFTs
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`in AMOLED displays; such displays are currently in production for a variety of
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`smart phones. In addition, many industrial and academic laboratories have
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`recently initiated R&D activities related to the fabrication of polysilicon thin film
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`transistors on flexible metal foil substrates and their application to flexible
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`displays. Such research flows from the accomplishments of my research group in
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`this technical field.
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`(8) My industrial experience includes work at the XEROX Palo Alto
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`Research Laboratory and various consulting projects with flat panel display
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`companies as well as companies producing equipment for the manufacture of flat
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`panel displays. All of these projects were related to the thin film transistors and
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`their application to flat panel displays.
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`(9)
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`I am a member of several professional organizations including the
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`Society for Information Display (SID), and the Electron Device Society of the
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`Institute of Electrical and Electronics Engineers (IEEE). I have also been the chair
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`or co-chair at numerous national and international conferences/symposiums
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`including several SID sponsored Workshops on Active Matrix Liquid Crystal
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`Displays and a Materials Research Society Symposium on Flat Panel Displays. I
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`have co-authored two book chapters, one dealing with the "Polysilicon TFT
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`Technology" and another on application of "Polysilicon TFTs in AMOLED
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`Displays." I have served as a reviewer for technical papers submitted to several
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`scientific journals and have also served as a reviewer for the National Science
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`Foundation Small Business Innovative Research (SBIR) program.
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`(10) A copy of my latest curriculum vitae (C.V.) is attached as
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`Appendix A and includes a list of my publications.
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`II. My Status as an Independent Expert Witness
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`(11)
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`I have been retained in this matter by Chimei Innolux Corp.
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`(“Petitioner”) to provide an analysis of the scope and content of the ‘978 patent
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`relative to the state of the art at the time of the earliest application underlying the
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`‘978 patent.
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`(12)
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`I am being compensated at the rate of $300 per hour for my work. My
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`fee is not contingent on the outcome of any matter or on any of the technical
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`positions I explain in this declaration. I have no financial interest in Petitioner.
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`(13)
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`I have been informed that Semiconductor Energy Laboratory Co., Ltd.
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`(hereinafter referred to as “Patentee”) owns the ‘978 patent. I have no financial
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`interest in the Patentee or the ‘978 patent nor have I ever had any contact with the
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`Patentee, or the inventor of the ‘978 patent, Hongyong Zhang.
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`III. Description of the Relevant Field and the Relevant Timeframe
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`(14)
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`I have carefully reviewed the ‘978 patent.
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`(15) For convenience, all of the information that I considered in arriving at
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`my opinions is listed in Appendix B.
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`(16) Based on my review of these materials, I believe that the relevant field
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`for purposes of the ‘978 patent is microelectronic fabrication processes and
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`devices related to flat panel displays and in particular to Active Matrix
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`Liquid Crystal Displays (AMLCD). I have been informed that the relevant
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`timeframe is March December 21, 1995.
`
`(17) As described in Section I above, I have extensive experience in the
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`relevant field. Based on my experience, I have a good understanding of the
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`relevant field in the relevant timeframe.
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`IV. The Person of Ordinary Skill in the Relevant Field and the Relevant
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`Timeframe
`
`(18)
`
`I have been informed that "a person of ordinary skill in the relevant
`
`field" is a hypothetical person to whom an expert in the relevant field could assign
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`a routine task with reasonable confidence that the task would be successfully
`
`carried out. I have been informed that the level of skill in the art is evidenced by
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`the prior art references. The prior art discussed herein demonstrates that a person
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`of ordinary skill in the art, at the time the '978 patent was filed, was aware of liquid
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`crystal display structures, including techniques for creating a uniform gap in the
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`seal region between the two opposing substrates.
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`(19) Based on my experience, I have an understanding of the capabilities
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`of a person of ordinary skill in the relevant filed. I have supervised and directed
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`many such persons over the course of my career.
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`V.
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`Background of the Technology
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`(20)
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`In an active matrix LCD, an image is divided into small elements
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`called pixels. In a color active matrix LCD , each pixel is further divided into three
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`sub-pixels, one for each of the three primary colors red, green, and blue. Each pixel
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`(in a monochrome display) or sub-pixel (in a color display) contains a thin film
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`transistor (TFT), a capacitor, and a pixel electrode, all on the same glass substrate
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`called a backplane.
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`(21) The backplane glass substrate is kept a small distance away from
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`another glass substrate, known as front-plane, which contains the color filters and
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`the display common electrode. The two glass substrates are bonded via a seal in
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`close proximity and along all the edges of the two glass substrates. The gap space
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`in between the two glass substrates is filled with a liquid crystal material.
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`(22) To ensure high image quality certain approaches are been followed
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`during display construction in order to make a uniform gap between the two glass
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`substrates. These include the use of spacers and the formation of dummy areas that
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`would have the same height along the entire perimeter of the sealing region.
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`(23)
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`In a pixel, the gate of a TFT is connected to a scan line, the drain is
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`connected to a signal line and the source is connected to the pixel electrode and the
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`storage capacitor. A TFT acts as a switch which requires a gate to source voltage
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`difference higher than a minimum value, known as threshold voltage, in order to
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`turn-on and allow current flow between its drain and source terminal. In other
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`words, when the gate to source voltage difference is higher than the device
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`threshold voltage, the TFT acts as a close switch thus establishing an electrical
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`connection between its source and drain terminals which enables current flow
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`between these two terminals. Otherwise the TFT acts as an open switch thus
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`keeping the source and drain terminals electrically isolated and current is
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`prevented from flowing between the source and drain terminals.When the TFT is
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`turned ON, the pixel storage capacitor is charged or discharged through the TFT
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`according to the voltage of the signal line and that voltage appears at the pixel
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`electrode. When the TFT is turned OFF, current cannot flow through it and the
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`electrical charges stored at the pixel storage capacitor maintain the voltage of the
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`pixel electrode. After the elapse of a time period known as the frame time, the
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`TFT switch is turned on again and the pixel electrode voltage is set again based on
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`the new signal line voltage. This fundamental operational principle of transistors,
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`i.e. to act as open or close switches and to realize electrical isolation, has enabled
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`the successful commercialization not only of AMLCD displays but also of a
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`plethora of other electronic systems that our information based society depends
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`upon.
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`(24) The pixel electrode voltage sets an electric field across the
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`liquid crystal material that is held between the pixel electrode and the
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`common electrode. The magnitude of this electric field will determine the
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`twist of liquid crystal which will affect its optical properties and, in turn,
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`this will determine the amount of light that will pass through the pixel.
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`(25) A row of pixels are switched by way of the scan line voltage which is
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`set by a scan or gate line drive circuitry. The voltages that appear on the signal
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`lines are set by another circuit known as the signal or data line drive circuitry.
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`Certain active matrix LCDs have integrated peripheral scanning circuits, i.e. scan
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`and signal drive circuits, that are fabricated on the glass substrate at the periphery
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`of the pixel array. Such scanning circuits typically consist of shift registers that
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`contain TFTs similar to the TFTs used in the pixels, and wirings that are formed
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`with the same materials used for the scan and signal lines. The wirings of a
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`typical shift register include multiple, long conducting lines, along the side of
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`the display that the shift register is located. These long conducting lines are
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`used in a shift register circuitry to form the power and ground lines, as well
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`as a plurality of clock lines all required for the proper operation of the shift
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`register. Since each of these long lines is used for a different purpose, these
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`lines are all electrically isolated from each other to ensure the proper
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`functionality of the shift register circuitry. For example if the clock lines
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`were not electrically isolated from each other, the wrong clock signals would
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`have been applied to different parts of the circuitry resulting in operational
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`failure. Furthermore, these long conducting lines need to have low resistance
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`so they are formed from the metal that has the lowest sheet resistance,
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`(typically that is the metal used to form the signal lines) and are formed wide
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`to further reduce their resistance, thus they occupy significant portion of the
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`shift register area. In general both the scan line and metal line metal layers
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`are used to form the wirings within a shift register or any other type of
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`circuits fabricated at the peripheral of the display.
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`VI. The ‘978 Patent
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`(26) As shown below in Fig. 17, the '978 patent describes that prior art
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`active matrix LCD devices are known to include drive circuits (signal line drive
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`circuit 13 and scanning line drive circuit 14). These prior art devices are also
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`configured such that signal lines 15 and scanning lines 16 extend outside of a
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`sealing material region 17 of a substrate for connection to control and power
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`supply circuitry. (Ex. 1001, col. 2, II. 3-10). Because lines 15 and 16 extend only
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`outside of the sealing material region on two sides of the sealing material region,
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`and these two sides are each opposite a drive circuit (13, 14) (having a different
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`physical height than lines 15 and 16), a non-uniform gap formed about the sealing
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`region 17. (Ex. 1001, col. 2, II. 47-49). This is because, when sealing the substrate
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`to another, an uneven pressure is applied in the sealing region in the areas of
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`varying step heights. That is to say, "the step of the sealing material on the
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`peripheral drive circuit side is different from that of the sealing material on a
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`wiring extending side. Hence, in bonding the substrates together, because no
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`pressure is uniformly applied to the substrate, it is difficult to make an interval
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`between the substrates uniform. As a result, non-uniformity occurs on display or an
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`image quality is deteriorated." Id. This non uniform gap is further described as
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`leading to shorting the scan and signal drive lines, thus causing display defects
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`such as line defects.
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`(27) As shown above in Fig. 1, in order to eliminate the uneven heights
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`caused by the asymmetrical lines and circuits about the sealing region, the ‘978
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`patent describes an “interval maintaining means” or “dummy wiring structure.”
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`The dummy wiring structure is designed to be electrically isolated from the signal
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`and scanning lines, and of a height in areas R3 and R4 that is “nearly equal to the
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`height of the region in which the thickness of the matrix circuit is maximum.” (i.e.,
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`areas R1 and R2) ‘978 patent, col. 4, ll. 47–50; col. 6, ll. 5-63.
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`(28) As shown below in Fig. 6. Of the ‘978 patent, the dummy wiring
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`structure, in some examples, is a laminate structure of layered dummy members
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`(301-304). ‘978 patent, col. 4, ll. 14–29. By the provision of the dummy wiring
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`structure, the interval or “gap” between substrates of the seal region in areas R1,
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`R2, R3 and R4 is equalized to facilitate a more consistent seal. ‘978 patent, Fig. 1,
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`3. As the dummy wiring patterns serve no electrical function, they are not
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`electrically connected to the remainder of the semiconductor circuit, or each
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`other.’978 patent, col. 7, ll. 58-64.
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`VII. Claim Interpretation
`
`(29)
`
`In proceedings before the USPTO, I understand that the claims of an
`
`unexpired patent are to be given their broadest reasonable interpretation in view of
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`the specification from the perspective of one skilled in the art. I have been
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`informed that the '978 patent has not expired. In comparing the claims of the '978
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`patent to the known prior art, I have carefully considered the '978 patent, and the
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`'978 file history based upon my experience and knowledge in the relevant field. I
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`have not encountered any "coined" terms or terms that require consideration of a
`
`special or explicitly defined meaning. Instead, the claim terms of the '978 patent
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`are used in their ordinary and customary sense as one skilled in the relevant field
`
`would understand them.
`
`(30)
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`I am informed that the '978 patent is a division of U.S. Patent
`
`Application No. 10/811,920, filed on Mar. 30, 2004, which is a division of U.S.
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`Patent Application No. 09/316,697, filed on May 21, 1999, which is a division of
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`U.S. Patent Application No. 08/768,066, filed on Dec. 16, 1996. Additionally, '978
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`patent claims priority to a foreign patent, Japanese Patent Application No.
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`07¬350229, filed on Dec. 21, 1995. I am further informed that this means that the
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`'978 patent is considered to have been filed on Dec. 21, 1995 for purposes of
`
`determining whether a reference constitutes prior art. Thus, a reference will qualify
`
`as prior art if it disclosed or suggested the claimed invention of the '978 patent
`
`prior to Dec. 21, 1995.
`
`(31)
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`I have been informed that a patent claim can be found unpatentable as
`
`obvious where the differences between the subject matter sought to be patented
`
`and the prior art are such that the subject matter as a whole would have been
`
`obvious at the time the invention was made to a person having ordinary skill in the
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`relevant field. I understand that an obviousness analysis involves a consideration of
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`(1) the scope and content of the prior art; (2) the differences between the claimed
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`inventions and the prior art; (3) the level of ordinary skill in the pertinent art; and
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`(4) secondary considerations of non-obviousness.
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`VIII. U.S. Patent No. 5,513,028 to Sono et. al. (“Sono,” Ex. 1003)
`
`(32)
`
`I have been asked to review the statements within the Patent Owner’s
`
`Response, Motion to Amend, and Mr. Stewart’s Declaration as they pertain to the
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`Sono patent and respond to those statements from the perspective of a person of
`
`ordinary skill in the art.
`
`(33) Sono explains that LCD devices can exhibit a non-uniform gap when
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`the seal area 32 is formed over peripheral circuits 31 and that “[u]nevenness in
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`color is generated if the distribution gap exceeds +0.1m.” (Ex. 1003, col. 1, ll. 36-
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`45). Furthermore, Sono explains that adjacent to the display area the absence of
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`pixel electrodes can also create unevenness which can affect the alignment control
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`film resulting in display characteristics that are inferior in the end portions of the
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`display area. (Ex. 1003, col. 1, ll. 18-35). “Near the end of the display area, the
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`film position becomes extremely low and the cell gap increases because of the
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`absence of the adjacent pixel electrode, so that the display characteristics become
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`inferior in such end portion of the display area.” (Ex. 1003, col. 1, ll. 31-35).
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`(34) The Sono patent teaches how to create a uniform cell gap and avoid
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`unevenness in both the seal area and around the display area by forming dummy
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`structures (“dummy pixels” or “dummy circuits”). Sono teaches the formation of
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`these structures within a “dummy area” which has a “step substantially the same as
`
`the step in the display area.” Furthermore, Sono teaches the formation of said
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`dummy area without adding any complexities to the manufacturing process. (Ex.
`
`1003, col. 3, ll. 14-17).
`
`(35) Sono teaches that the dummy area can be formed by dummy pixels.
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`“More specifically, in said dummy area, there may be formed dummy pixels of a
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`same configuration, having same wirings, switching elements, pixel electrodes etc.
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`as in the display area.” (Ex. 1003, col. 3, ll. 18-27). As described in Sono’s patent,
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`and is depicted schematically in Fig 4 (shown below), the dummy pixels within the
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`dummy area are formed the same as the pixels in the display area. The advantages
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`of Sono’s teachings are the formation of “same step” which is “easy in
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`manufacture, because the manufacturing process of the pixels can be merely
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`expanded and the additional steps are not required.” Ibid.
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`(36) Sono also teaches that “..said step may be formed by the circuit
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`elements or wiring provided in the peripheral area.” (Ex. 1003, col. 3, ll. 28-31).
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`For example, embodiment 5 of the Sono patent discloses a display with four circuit
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`elements in the peripheral area, i.e. scanning circuits 82-85 arranged along the four
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`sides of the display area. “ In the present embodiment, patterns 82-85 of a same
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`step height are positioned on the four sides of the display area 81, and are all
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`utilized as peripheral scanning circuits. Also this embodiment, like embodiment 4,
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`can achieve a uniform liquid crystal cell gap and a reduced chip size, because the
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`liquid crystal sealing area 86 is formed on the peripheral scanning circuits 82-85 of
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`same step height.” (Ex. 1003, col. 6, ll. 53-59). Figure 10 of Sono (shown below)
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`depicts the four scanning circuits 82-85 that are used to form the same step.
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`(37) The Sono patent also teaches that “dummy areas” may be formed with
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`“dummy circuits” in order to achieve a same step “[t]he liquid crystal display
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`device of the present invention can control the orientation of the liquid crystal to
`
`the end portions of the display area, thereby enabling to display image of high
`
`quality without unevenness over the entire display area, by the formation of steps
`
`such as dummy circuits in the surrounding area of the display area.” (Ex. 1003, col.
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`7, ll. 18-25). I strongly disagree with Patent Owner Response which alleges that
`
`dummy pixels and dummy circuits have different functions “the dummy pixels and
`
`dummy circuits have different functions and are located in different parts of the
`
`display.” Resp at 40. Some skilled in the art will recognize that Sono teaches that
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`both dummy pixels and dummy circuits serve to form “the same step” which
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`enables both proper control of the liquid crystal orientation to the end portions of
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`the display area and uniform cell gap and both are located in the surrounding area
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`of the display area. Figure 7 of Sono (shown above) depicts four circuits within the
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`liquid crystal seal area 76, two of which are dummy circuits: “…a horizontal
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`scanning circuit 72; a vertical scanning circuit 73 having a same step as that of said
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`horizontal scanning circuit 72; a horizontal dummy circuit 74 having a same step
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`as that of said horizontal scanning circuit 72; a vertical dummy circuit 75 having a
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`same step as that of said horizontal scanning circuit 72…” (Ex. 1003, col. 5, ll. 6-
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`11).
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`(38) One skilled in the art would recognize that the dummy circuits 74 and
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`75 are the same as the scanning circuits 72 and 73. In Figure 7 (shown above) it
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`can be seen that the area occupied by the dummy circuits 74, 75 is the same as the
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`area occupied by the scanning circuits 72, 73. Therefore all circuit components
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`(i.e. transistors and wirings) of the scanning circuits are also present in the dummy
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`circuits. If any components (e.g. wirings) were missing from the dummy circuits,
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`as alleged by Mr. Stewart, the area occupied by the dummy circuits would have
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`been less than that of the scanning circuits. Stewart Decl., ¶ 86. Not only the
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`dummy circuits are depicted having the same area as the scanning circuits but Sono
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`also discloses that “…excellent producibility is ensured because the dummy
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`circuits 74, 75 can be prepared in a same process as for the peripheral scanning
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`circuits 72, 73.” (Ex. 1003, col. 6, ll. 34-37). Since all circuits have the same size
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`19
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`CMI Exhibit 1013
`Page 19
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`and are prepared in a same process the dummy circuits contain all components (i.e.
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`transistors and wirings) and thus are the same as the scanning circuits. This will
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`ensure the “same step” and “excellent producibility” advantages that Sono
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`discloses.
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`(39) As stated above in paragraph (36) Sono discloses that when the
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`dummy areas are formed with dummy pixels, the dummy pixels are the same as
`
`the pixels in the display area, which results in the formation of “same step” which
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`is “easy in manufacture” because it adds “no further complexities to the
`
`manufacturing process” and “additional steps are not required.” (Ex. 1003, col. 3,
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`ll. 14-27). Likewise, one skilled in the art would recognize that when the dummy
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`areas are formed with dummy circuits, based on Sono’s teachings, the dummy
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`circuits are the same as the scanning circuits, in order to ensure the formation of
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`“same step” which is “easy in manufacture” because it adds “no further
`
`complexities to the manufacturing process” and “additional steps are not required.”
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`(40) Furthermore comparing Figures 7 and 10 of Sono (shown above) a
`
`person skilled in the art would recognize that circuit elements within the seal
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`region can be used either as scanning circuits or as dummy circuits. When all
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`circuit elements are used as scanning circuits, such as those depicted in Figure 10
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`of Sono, the ones on opposing sides of the display area 81 are the same in order to
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`ensure both the same functionality as well as the same step. A person skilled in the
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`20
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`CMI Exhibit 1013
`Page 20
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`art would likewise recognize that the dummy circuits 74, 75 will be formed the
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`same as the corresponding scanning circuits 72, 73 that are in opposing sides of the
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`pixel area 71. As discussed above, additional evidence that the Sono patent
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`teaches that the dummy circuits are the same as the scanning circuits include: a)
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`showing in Figure 7 all circuits to have the same size, and b) disclosing that the
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`same process is used for their fabrication, and c) comparing the figures 7 and 10
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`that correspond to the embodiments 4 and 5.
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`(41) A person skilled in the art would recognize that within a circuit the
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`size of the step will be dominated by the thickness of the metal wirings. In the
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`manufacture of liquid crystal display, at least two different metal layers separated
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`by insulating material are used (one for forming the scanning lines and the other
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`the data lines). Both of these metal layers are typically used to form the wirings
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`within a circuit element and both of these metal layers are significantly thicker than
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`the semiconductor layer used to form the TFTs; for example in case of TFTs
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`fabricated on glass substrates the signal line metal layer is least 10 times thicker
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`than the thin film semiconductor layer. Furthermore, the metal wirings within a
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`circuit, either scanning circuit or dummy circuit, occupy a significant portion of the
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`overall area of the circuit. Mr. Stewart in his deposition did acknowledge that in a
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`shift register circuitry the area occupied by the long conducting lines (discussed
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`above in paragraph 25), which he referred them as bus, is two to three time the area
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`21
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`CMI Exhibit 1013
`Page 21
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`occupied by the transistors “…the bus is -- is twice or three times as big as that --
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`those blocks.” Stewart Dep. at 101: 1-9. Mr. Stewart acknowledged that the blocks
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`in the shift register schematic shown in his declaration each contains a plurality of
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`transistors “…typically between 4 transistors and 20 transistors in each one of the
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`blocks, like SR1, SR2.” Stewart Dep. at 99: 15-24. Stewart Decl., ¶ 100. For the
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`above reasons, a person skilled in the art will be motivated to maintain the same
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`wiring design and thus form the same metal wiring, in both the scanning circuits
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`and dummy circuits. A person skilled in the art would not eliminate the metal
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`wirings from the dummy circuits as such omission will result in significant
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`unevenness in the seal area and defeat the purpose of forming the dummy circuits.
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`Omitting a wiring layer or modifying its design, so metal may exist only on top of
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`TFTs but not anywhere else (as suggested by Mr. Stewart), may create unevenness
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`in the seal region, introduce complexities in the manufacturing process2 and
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`additional steps (e.g. extra design steps); which are all outcomes that Sono
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`explicitly teaches away. Figure 8 of Sono (shown below) depicts a cross section
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`along an arbitrary line 8-8’ drawn in Figure 7. Since a scanning circuit contain
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`2 During the photolithographic processes the lithographic stepper equipment may
`
`need to hold and deal with more masks in order to define different metal wiring
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`patterns in opposite sides of the seal region. This will slow down the lithographic
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`processes resulting in higher manufacturing cost.
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`22
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`CMI Exhibit 1013
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`
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`long wirings patterns along its entire length while TFTs are only located in selected
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`areas, an arbitrary cross section as that shown in Figure 8 of Sono shows the long
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`conductive wirings extending along the edge of substrate. Such an arbitrary cross
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`section would not show a TFT cross-sections (as alleged by Mr. Stewart) because
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`TFTs only exist in isolated regions. This further supports that within the dummy
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`circuit 75 as in the scanning circuit 73 are long wirings made by the
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`aforementioned two metal layers. Therefore the wiring of the dummy circuits as
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`shown in Fig. 8 is the same as that of the scanning circuits yielding the same step
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`and thus the uniform liquid crystal gap depicted in Figure 8. Even though Mr.
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`Stewart and I do disagree on what is depicted in Sono’s Figure 8, we both agree
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`that Sono depicts a symmetry in the content of the dummy circuit 75 and scanning
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`circuit 73. Therefore, a person skilled in the art will recognize that all components
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`(TFTs and wirings) of a scanning circuit also exist within a dummy circuit.
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`(42)
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`I disagree with Mr. Stewart’s opinion, that elements 73 and 75
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`shown in Figure 8 of Sono, are source and drain regions formed in a silicon
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`CMI Exhibit 1013
`Page 23
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`semiconductor substrate 78. Stewart Decl., ¶ 94. The annotated Figure 9D of
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`Sono (shown above), depicts that the semiconductor substrate 78 of Figure 8, is
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`a multilayer structure containing a thin silicon layer 102 on top of three
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`different insulating layers: an oxide layer 103, a nitride layer 105 and another
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`oxide layer 104; the TFTs are formed on the thin silicon film 102. (Ex. 1003,
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`col. 5, ll. 44-67 and col. 6, ll. 1-22). Figures 9A-D of Sono depict a series of
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`unique fabrication steps that remove all but a thin layer which is
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